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| 101 innovation drive san jose, ca 95134 (408) 544-7000 http://www.altera.com stratix device handbook, volume 1 s5v1-3.4
copyright ? 2006 altera corporation. all righ ts reserved. altera, the programmable solu tions company, the stylized altera logo, specific device des- ignations, and all other words and logos that are identified as tr ademarks and/or service marks ar e, unless noted otherwise, th e trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. al- tera products are protected under numerous u.s. and foreign patents and pending app lications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice . altera assumes no responsibility or liability arising out of t he ap- plication or use of any info rmation, product, or service desc ribed herein except as expressly agreed to in writing by altera corporation. altera customers are advised to obtain the latest ve rsion of device specifications before relying on any published in- formation and before placing orders for products or services . ii altera corporation altera corporation iii contents chapter revision dates .......................................................................... vii about this handb ook .............................................................................. ix how to find information ........................................................................................................ ................ ix how to contact altera .......................................................................................................... ................... ix typographic conventions ........................................................................................................ ................ x section i. stratix de vice family data sheet revision history ............................................................................................................... ............. part i?1 chapter 1. introduction introduction ................................................................................................................... ......................... 1?1 features ....................................................................................................................... ............................ 1?2 chapter 2. stratix architecture functional description ......................................................................................................... ................. 2?1 logic array blocks ............................................................................................................. ................... 2?3 lab interconnects .............................................................................................................. .............. 2?4 lab control signals ............................................................................................................ ............. 2?5 logic elements ................................................................................................................. ...................... 2?6 lut chain & register chain ..................................................................................................... ..... 2?8 addnsub signal ................................................................................................................. ................ 2?8 le operating modes ............................................................................................................. ........... 2?8 clear & preset logic control ................................................................................................... ..... 2?13 multitrack interconnect ........................................................................................................ ............. 2?14 trimatrix memory ............................................................................................................... ................ 2?21 memory modes ................................................................................................................... ............ 2?22 clear signals .................................................................................................................. .................. 2?24 parity bit support ............................................................................................................. .............. 2?24 shift register support ......................................................................................................... ........... 2?25 memory block size .............................................................................................................. ........... 2?26 independent clock mode ......................................................................................................... ..... 2?44 input/output clock mode ........................................................................................................ ... 2?46 read/write clock mode .......................................................................................................... ..... 2?49 single-port mode ............................................................................................................... ............. 2?51 multiplier block ............................................................................................................... ............... 2?57 adder/output blocks ............................................................................................................ ....... 2?61 modes of operation ............................................................................................................. .......... 2?64 iv altera corporation contents stratix device handbook, volume 1 dsp block interface ............................................................................................................ ............ 2?70 plls & clock networks .......................................................................................................... ........... 2?73 global & hierarchical clocking ................................................................................................. .. 2?73 enhanced & fast plls ........................................................................................................... ........ 2?81 enhanced plls .................................................................................................................. ............. 2?87 fast plls ...................................................................................................................... ............ ...... 2?100 i/o structure .................................................................................................................. ........... ......... 2?104 double-data rate i/o pins ...................................................................................................... ... 2?111 external ram interfacing ....................................................................................................... .... 2?115 programmable drive strength ................................................................................................... 2 ?119 open-drain output .............................................................................................................. ........ 2?120 slew-rate control .............................................................................................................. .......... 2?120 bus hold ....................................................................................................................... ........... ...... 2?121 programmable pull-up resistor ................................................................................................ 2? 122 advanced i/o standard support .............................................................................................. 2?12 2 differential on-chip termination ............................... .............................................................. 2? 127 multivolt i/o interface ........................................................................................................ ....... 2?129 high-speed differential i/o support ............................................................................................ 2?130 dedicated circuitry ............................................................................................................ .......... 2?137 byte alignment ................................................................................................................. ............ 2?140 power sequencing & hot socketing ............................................................................................... 2?140 chapter 3. configuration & testing ieee std. 1149.1 (jtag) bounda ry-scan support ........ ........... ........... ........... ........... ......... ......... ...... 3?1 signaltap ii embedded logic analyzer ............................................................................................ 3?5 configuration .................................................................................................................. ....................... 3?5 operating modes ................................................................................................................ .............. 3?5 configuring stratix fpgas with jrunner .................................................................................... 3?7 configuration schemes .......................................................................................................... ......... 3?7 partial reconfiguration ................... ..................................................................................... ............ 3?7 remote update configuration modes .......................... ................................................................ 3?8 stratix automated single event upset (seu) detection ........... ........... ........... ........... ............ ........ 3?12 custom-built circuitry ......................................................................................................... ......... 3?13 software interface ............................................................................................................. .............. 3?13 temperature sensing diode ...................................................................................................... ......... 3?13 chapter 4. dc & switching characteristics operating conditions ........................................................................................................... ................ 4?1 power consumption .............................................................................................................. ............. 4?17 timing model ................................................................................................................... ............ ........ 4?19 preliminary & final timing ..................................................................................................... ..... 4?19 performance .................................................................................................................... ................ 4?20 internal timing parameters ..................................................................................................... ..... 4?22 external timing parameters ..................................................................................................... .... 4?33 stratix external i/o timing .................................................................................................... ...... 4?36 i/o timing measurement methodology .................................................................................... 4?60 external i/o delay parameters ........... ....................................................................................... .. 4?66 altera corporation v contents contents maximum input & output clock rates ...................................................................................... 4?76 high-speed i/o specification ................................................................................................... ........ 4?87 pll specifications ............................................................................................................. ........... ........ 4?94 dll specifications ............................................................................................................. ................ 4?102 chapter 5. reference & ordering information software ....................................................................................................................... ........................... 5?1 device pin-outs ................................................................................................................ ..................... 5?1 ordering information ........................................................................................................... ................ 5?1 index vi altera corporation contents stratix device handbook, volume 1 altera corporation vii chapter revision dates the chapters in this book, stratix device handbook, volume 1 , were revised on the following dates. where chapters or groups of chapters are av ailable separately, part numbers are listed. chapter 1. introduction revised: july 2005 part number: s51001-3.2 chapter 2. stratix architecture revised: july 2005 part number: s51002-3.2 chapter 3. configuration & testing revised: july 2005 part number: s51003-1.3 chapter 4. dc & switching characteristics revised: january 2006 part number: s51004-3.4 chapter 5. reference & ordering information revised: september 2004 part number: s51005-2.1 viii altera corporation chapter revision dates stratix device handbook, volume 1 altera corporation ix about this handbook this handbook provides comprehe nsive information about the altera ? stratix family of devices. how to find information you can find more information in the following ways: the adobe acrobat find feature, wh ich searches the text of a pdf document. click the binoculars toolba r icon to open the find dialog box. acrobat bookmarks, which serve as an additional table of contents in pdf documents. thumbnail icons, which provide miniature previews of each page, provide a link to the pages. numerous links, shown in green text, which allow you to jump to related information. how to contact altera for the most up-to-date information about altera products, go to the altera world-wide web site at www.altera.com . for technical support on this product, go to www.altera.com/mysupport . for additional information about altera products, consult the sources shown below. information type usa & canada all other locations technical support www.altera.com/mysupport/ www.altera.com/mysupport/ (800) 800-epld (3753) (7:00 a.m. to 5:00 p.m. pacific time) +1 408-544-8767 7:00 a.m. to 5:00 p.m. (gmt -8:00) pacific time product literature www.altera.com www.altera.com altera literature services literature@altera.com literature@altera.com non-technical customer service (800) 767-3753 + 1 408-544-7000 7:00 a.m. to 5:00 p.m. (gmt -8:00) pacific time ftp site ftp.altera.com ftp.altera.com x altera corporation typographic conventions stratix device handbook, volume 1 typographic conventions this document uses the typogr aphic conventions shown below. visual cue meaning bold type with initial capital letters command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. example: save as dialog box. bold type external timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and softw are utility names are shown in bold type. examples: f max , \qdesigns directory, d: drive, chiptrip.gdf file. italic type with initial capital letters document titles are shown in italic ty pe with initial capital letters. example: an 75: high-speed board designs. italic type internal timing parameters and variables are shown in italic type. examples: t pia , n + 1. variable names are enclosed in angle br ackets (< >) and shown in italic type. example: altera corporation section i?1 section i. stratix device family data sheet this section provides the data sheet specifications for stratix ? devices. they contain feature definitions of the internal architecture, configuration and jtag boundary-scan testing information, dc operating conditions, ac timing parameters, a reference to power consumption, and ordering information for stratix devices. this section contains the following chapters: chapter 1, introduction chapter 2, stratix architecture chapter 3, configuration & testing chapter 4, dc & switching characteristics chapter 5, reference & ordering information revision history the table below shows th e revision history for chapters 1 through 5 . chapter date/version changes made 1 july 2005, v3.2 minor content changes. september 2004, v3.1 updated table 1?6 on page 1?5 . april 2004, v3.0 main section page numbers changed on first page. changed pci-x to pci-x 1.0 in ?features? on page 1?2 . global change from signaltap to signaltap ii. the dsp blocks in ?features? on page 1?2 provide dedicated implementation of multipliers that are now ?faster than 300 mhz.? january 2004, v2.2 updated -5 speed grade device information in table 1-6. october 2003, v2.1 add -8 speed grade device information. july 2003, v2.0 format changes throughout chapter. section i?2 altera corporation stratix device family data sheet stratix device handbook, volume 1 2 july 2005 v3.2 added ?clear signals? section. updated ?power sequencing & hot socketing? section. format changes. september 2004, v3.1 updated fast regional clock networks description on page 2?73 . deleted the word preliminary from the ?specification for the maximum time to relock is 100 s? on page 2?90 . added information about differential sstl and hstl outputs in ?external clock outputs? on page 2?92 . updated notes in figure 2?55 on page 2?93 . added information about m counter to ?clock multiplication & division? on page 2?101 . updated note 1 in table 2?58 on page 2?101 . updated description of ?clock multiplication & division? on page 2?88 . updated table 2?22 on page 2?102 . added references to an 349 and an 329 to ?external ram interfacing? on page 2?115 . table 2?25 on page 2?116 : updated the table, updated notes 3 and 4. notes 4, 5, and 6, are now notes 5, 6, and 7, respectively. updated table 2?26 on page 2?117 . added information about pci compliance to page 2?120 . table 2?32 on page 2?126 : updated the table and deleted note 1. updated reference to device pin-outs now being available on the web on page 2?130 . added notes 4 and 5 to table 2?36 on page 2?130 . updated note 3 in table 2?37 on page 2?131 . updated note 5 in table 2?41 on page 2?135 . april 2004, v3.0 added note 3 to rows 11 and 12 in table 2?18 . deleted ?stratix and stratix gx device pll availability? table. added i/o standards row in table 2?28 that support max and min strength. row clk [1,3,8,10] was removed from ta b l e 2 ? 3 0 . added checkmarks in enhanced column for lvpecl, 3.3-v pcml, lvds, and hypertransport technology rows in table 2?32 . removed the left and right i/o banks row in table 2?34 . changed rclk values in figures 2?50 and 2?51 . external ram interfac ing section replaced. november 2003, v2.2 added 672-pin bga package information in table 2?37 . removed support for series and parallel on-chip termination. termination technology renamed diff erential on-chip termination. updated the number of channels per pll in tables 2-38 through 2- 42. updated figures 2?65 and 2?67 . october 2003, v2.1 updated ddr i information. updated table 2?22 . added tables 2?25 , 2?29 , 2?30 , and 2?72 . updated figures 2?59 , 2?65 , and 2?67 . updated the lock detect section. chapter date/version changes made altera corporation section i?3 stratix device family data sheet 2 july 2003, v2.0 added reference on page 2-73 to figures 2-50 and 2-51 for rclk connections. updated ranges for epll post-scale and pre-scale dividers on page 2-85. updated pll reconfiguration frequency from 25 to 22 mhz on page 2-87. new requirement to assert are set signal each pll when it has to re- acquire lock on either a new cloc k after loss of lock (page 2-96). updated max input frequency for clk[1,3,8,10] from 462 to 500, table 2-24. renamed impedance matching to series termination throughout. updated naming convention for dqs pins on page 2-112 to match pin tables. added ddr sdram performance specification on page 2-117. added external reference resistor values for terminator technology (page 2-136). added terminator technology specification on pages 2-137 and 2- 138. updated tables 2-45 to 2-49 to reflect pll cross-bank support for high speed differential c hannels at full speed. wire bond package performance s pecification for ?high? speed channels was increased to 624 mbps from 462 mbps throughout chapter. 3 july 2005, v1.3 updated ?operating modes? section. updated ?temperature sensing diode? section. updated ?ieee std. 1149.1 (jtag) boundary-scan support? section. updated ?configuration? section. january 2005, v1.2 updated limits for jtag chain of devices. september 2004, v1.1 added new section, ?stratix automated single event upset (seu) detection? on page 3?12 . updated description of ?custom-built ci rcuitry? on page 3?13 . april 2003, v1.0 no new changes in stratix device handbook v2.0. 4 january 2006, v3.4 added table 4?135 . july 2005, v3.3 updated tables 4?6 and 4?30 . updated tables 4?103 through 4?108 . updated tables 4?114 through 4?124 . updated table 4?129 . added table 4?130 . chapter date/version changes made section i?4 altera corporation stratix device family data sheet stratix device handbook, volume 1 4 january 2005, 3.2 updated rise and fall input values. september 2004, v3.1 updated note 3 in table 4?8 on page 4?4 . updated table 4?10 on page 4?6 . updated table 4?20 on page 4?12 through table 4?23 on page 4?13 . added rows v il(ac) and v ih(ac) to each table. updated table 4?26 on page 4?14 through table 4?29 on page 4?15 . updated table 4?31 on page 4?16 . updated description of ?external timing parameters? on page 4?33 . updated table 4?36 on page 4?20 . added signals t outco , t xz , and t zx to figure 4?4 on page 4?33 . added rows t m512clkensu and t m512clkenh to table 4?40 on page 4?24 . added rows t m4clkensu and t m4clkenh to table 4?41 on page 4?24 . updated note 2 in table 4?54 on page 4?35 . added rows t mramclkensu and t mramclkenh to table 4?42 on page 4?25 . updated table 4?46 on page 4?29 . updated table 4?47 on page 4?29 . chapter date/version changes made altera corporation section i?5 stratix device family data sheet 4 table 4?48 on page 4?30 : added rows t m512clksensu and t m512clkenh , and updated symbol names. updated power-up current (iccint) required to power a stratix device on page 4?17 . updated table 4?37 on page 4?22 through table 4?43 on page 4?27 . table 4?49 on page 4?31 : added rows t m4kclkensu , t m4kclkenh , t m4kbesu , and t m4kbeh, deleted rows t m4kraddrasu and t m4kraddrh , and updated symbol names. table 4?50 on page 4?31 : added rows t mramclkensu , t mramclkenh , t mrambesu , and t mrambeh , deleted rows t mramaddrasu and t mramraddrh , and updated symbol names. table 4?52 on page 4?34 : updated table, deleted ?conditions? column, and added rows t xz and t zx . table 4?52 on page 4?34 : updated table, deleted ?conditions? column, and added rows t xz and t zx . table 4?53 on page 4?34 : updated table and added rows t xzpll and t zxpll . updated note 2 in table 4?53 on page 4?34 . table 4?54 on page 4?35 : updated table, deleted ?conditions? column, and added rows t xzpll and t zxpll . updated note 2 in table 4?54 on page 4?35 . deleted note 2 from table 4?55 on page 4?36 through table 4?66 on page 4?41 . updated table 4?55 on page 4?36 through table 4?96 on page 4?56 . added rows t xz , t zx , t xzpll , and t zxpll. added note 4 to table 4?101 on page 4?62 . deleted note 1 from table 4?67 on page 4?42 through table 4?84 on page 4?50 . added new section ?i/o timing measurement methodology? on page 4?60 . deleted note 1 from table 4?67 on page 4?42 through table 4?84 on page 4?50 . deleted note 2 from table 4?85 on page 4?51 through table 4?96 on page 4?56 . added note 4 to table 4?101 on page 4?62 . table 4?102 on page 4?64 : updated table and added note 4. updated description of ?external i/o delay parameters? on page 4?66 . added note 1 to table 4?109 on page 4?73 and table 4?110 on page 4?74 . updated table 4?103 on page 4?66 through table 4?110 on page 4?74 . deleted note 2 from table 4?103 on page 4?66 through table 4?106 on page 4?69 . added new paragraph about output adder delays on page 4?68 . updated table 4?110 on page 4?74 . added note 1 to table 4?111 through table 4?113 on page 4?75 . chapter date/version changes made section i?6 altera corporation stratix device family data sheet stratix device handbook, volume 1 4 updated table 4?123 on page 4?85 through table 4?126 on page 4?92 . updated note 3 in table 4?123 on page 4?85 . table 4?125 on page 4?88 : moved to correct order in chapter, and updated table. updated table 4?126 on page 4?92 . updated table 4?127 on page 4?94 . updated table 4?128 on page 4?95 . april 2004, v3.0 table 4?129 on page 4?96 : updated table and added note 10. updated table 4?131 and table 4?132 on page 4?100 . updated table 4?110 on page 4?74 . updated table 4?123 on page 4?85 . updated table 4?124 on page 4?87 . through table 4?126 on page 4?92 . added note 10 to table 4?129 on page 4?96 . moved table 4?127 on page 4?94 to correct order in the chapter. updated table 4?131 on page 4?100 through table 4?132 on page 4?100 . deleted t xz and t zx from figure 4?4 . waveform was added to figure 4?6 . the minimum and maximum duty cycle values in note 3 of table 4?8 were moved to a new ta b l e 4 ? 9 . changes were made to values in sstl-3 class i and ii rows in table 4?17 . note 1 was added to table 4?34 . added t su_r and t su_c rows in table 4?38 . changed table 4?55 title from ?ep1s10 column pin fast regional clock external i/o timing parameters? to ?ep1s10 external i/o timing on column pins using fast regional clock networks.? changed values in tables 4?46 , 4?48 to 4?51 , 4?128 , and 4?131 . added t areset row in tables 4?127 to 4?132 . deleted -5 speed grade column in tables 4?117 to 4?119 and 4?122 to 4?123 . fixed differential waveform in figure 4?1 . added ?definition of i/o skew? section. added t su and t co_c rows and made changes to values in t pre and t clkhl rows in table 4?46 . values changed in the t su and t h rows in table 4?47 . values changed in the t m4kclkhl row in table 4?49 . values changed in the t mramclkhl row in table 4?50 . added ta b l e 4 ? 5 1 to ?internal timing parameters? section. the timing information is preliminary in tables 4?55 through 4?96 . table 4?111 was separated into 3 tables: tables 4?111 to 4?113 . november 2003, v2.2 updated tables 4?127 through 4?129 . chapter date/version changes made altera corporation section i?7 stratix device family data sheet 4 october 2003, v2.1 added -8 speed grade information. updated performance information in table 4?36 . updated timing information in tables 4?55 through 4?96 . updated delay information in tables 4?103 through 4?108 . updated programmable delay information in tables 4?100 and 4?103 . july 2003, v2.0 updated clock rates in tables 4?114 through 4?123 . updated speed grade information in the introduction on page 4-1. corrected figures 4-1 & 4-2 and table 4-9 to reflect how vid and vod are specified. added note 6 to table 4-32. updated stratix performance table 4-35. updated ep1s60 and ep1s80 timing parameters in tables 4-82 to 4- 93. the stratix timing models are final for all devices. updated stratix ioe programmable delay chains in tables 4-100 to 4- 101. added single-ended i/o standard output pin delay adders for loading in table 4-102. added spec for fpll[10..7]clk pins in tables 4-104 and 4-107. updated high-speed i/o specification for j=2 in tables 4-114 and 4- 115. updated epll specification and fast pll specification in tables 4- 116 to 4-120. 5 september 2004, v2.1 updated reference to device pin-outs on page 5?1 to indicate that device pin-outs are no longer incl uded in this manual and are now available on the altera web site. april 2003, v1.0 no new changes in stratix device handbook v2.0. chapter date/version changes made section i?8 altera corporation stratix device family data sheet stratix device handbook, volume 1 altera corporation 1?1 july 2005 1. introduction introduction the stratix ? family of fpgas is based on a 1.5-v, 0.13-m, all-layer copper sram process, with densities of up to 79,040 logic elements (les) and up to 7.5 mbits of ram. stratix devi ces offer up to 22 digital signal processing (dsp) blocks with up to 176 (9-bit 9-bit) embedded multipliers, optimized for dsp applications that enable efficient implementation of high -performance filters an d multipliers. stratix devices support various i/o standards and also offer a complete clock management solution with its hierar chical clock structure with up to 420-mhz performance and up to 12 phase-locked loops (plls). the following shows the main sections in the stratix device family data sheet: section page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 logic array blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3 logic elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?6 multitrack interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 trimatrix memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?21 digital signal proces sing block . . . . . . . . . . . . . . . . . . . . . . . . 2?52 plls & clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?73 i/o structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?104 high-speed differential i/o support. . . . . . . . . . . . . . . . . . 2?130 power sequencing & hot socketing . . . . . . . . . . . . . . . . . . . 2?140 ieee std. 1149.1 (jtag) boundary-s can support. . . . . . . . . . 3?1 signaltap ii embedded logic analyzer . . . . . . . . . . . . . . . . . 3?5 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5 temperature sensing diode. . . . . . . . . . . . . . . . . . . . . . . . . . . 3?13 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?17 timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?19 software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 device pin-outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1 s51001-3.2 1?2 altera corporation stratix device handbook, volume 1 july 2005 features features the stratix family offers the following features: 10,570 to 79,040 les; see table 1?1 up to 7,427,520 ram bits (928,440 byte s) available without reducing logic resources trimatrix tm memory consisting of three ram block sizes to implement true dual-port memory and first-in first-out (fifo) buffers high-speed dsp blocks provide dedicated implementation of multipliers (faster than 300 mhz), multiply-ac cumulate functions, and finite impulse response (fir) filters up to 16 global clocks with 22 clocking resources per device region up to 12 plls (four enhanced plls and eight fast plls) per device provide spread spectrum, programmable bandwidth, clock switch- over, real-time pll reconfiguratio n, and advanced multiplication and phase shifting support for numerous single-ended and differential i/o standards high-speed differential i/o support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (mbps) support for high-speed networking and communications bus standards including rapidio, ut opia iv, csix, hypertransport tm technology, 10g ethernet xsbi, spi-4 phase 2 (pos-phy level 4), and sfi-4 differential on-chip termination support for lvds support for high-speed external memory, including zero bus turnaround (zbt) sram, quad data rate (qdr and qdrii) sram, double data rate (ddr) sdram, ddr fast cycle ram (fcram), and single data rate (sdr) sdram support for 66-mhz pci (64 and 32 bit) in -6 and faster speed-grade devices, support for 33-mhz pci (64 and 32 bit) in -8 and faster speed-grade devices support for 133-mhz pci-x 1.0 in -5 speed-grade devices support for 100-mhz pci-x 1.0 in -6 and faster speed-grade devices support for 66-mhz pci-x 1.0 in -7 speed-grade devices support for multiple intellectual property megafunctions from altera megacore ? functions and altera megafunction partners program (ampp sm ) megafunctions support for remote configuration updates altera corporation 1?3 july 2005 stratix device handbook, volume 1 introduction table 1?1. stratix device features ? ep1s10, ep1s20, ep1s25, ep1s30 feature ep1s10 ep1s20 ep1s25 ep1s30 les 10,570 18,460 25,660 32,470 m512 ram blocks (32 18 bits) 94 194 224 295 m4k ram blocks (128 36 bits) 60 82 138 171 m-ram blocks (4k 144 bits) 1 2 2 4 total ram bits 920,448 1,669,248 1,944,576 3,317,184 dsp blocks 6 101012 embedded multipliers (1) 48 80 80 96 plls 6 6 6 10 maximum user i/o pins 426 586 706 726 table 1?2. stratix device featur es ? ep1s40, ep1s60, ep1s80 feature ep1s40 ep1s60 ep1s80 les 41,250 57,120 79,040 m512 ram blocks (32 18 bits) 384 574 767 m4k ram blocks (128 36 bits) 183 292 364 m-ram blocks (4k 144 bits) 4 6 9 total ram bits 3,423,744 5,215,104 7,427,520 dsp blocks 14 18 22 embedded multipliers (1) 112 144 176 plls 12 12 12 maximum user i/o pins 822 1,022 1,238 note to ta b l e s 1 ? 1 and 1?2 : (1) this parameter lists the total number of 9 9-bit multipliers for each device. for the total number of 18 18-bit multipliers per device, divide the total number of 9 9-bit multipliers by 2. for the total number of 36 36-bit multipliers per device, divide the total number of 9 9-bit multipliers by 8. 1?4 altera corporation stratix device handbook, volume 1 july 2005 features stratix devices are available in space-saving fineline bga ? and ball-grid array (bga) packages (see tables 1?3 through 1?5 ). all stratix devices support vertical migration within the same package (for example, you can migrate between the ep1s10, ep 1s20, and ep1s25 devices in the 672- pin bga package). vertical migrat ion means that you can migrate to devices whose dedicated pins, configur ation pins, and power pins are the same for a given package across device densities. for i/o pin migration across densities, you must cross-reference the available i/o pins using the device pin-outs for all planned de nsities of a given package type to identify which i/o pins ar e migrational. the quartus ? ii software can automatically cross reference and place all pins except differential pins for migration when given a device migration list. you must use the pin- outs for each device to verify the differential placement migration. a future version of the quartus ii soft ware will support differential pin migration. table 1?3. stratix package options & i/o pin counts device 672-pin bga 956-pin bga 484-pin fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga ep1s10 345 335 345 426 ep1s20 426 361 426 586 ep1s25 473 473 597 706 ep1s30 683 597 726 ep1s40 683 615 773 822 ep1s60 683 773 1,022 ep1s80 683 773 1,203 note to ta b l e 1 ? 3 : (1) all i/o pin counts include 20 dedicated clock input pins ( clk[15..0]p , clk0n , clk2n , clk9n , and clk11n ) that can be used for data inputs. table 1?4. stratix bga package sizes dimension 672 pin 956 pin pitch (mm) 1.27 1.27 area (mm 2 ) 1,225 1,600 length width (mm mm) 35 35 40 40 altera corporation 1?5 july 2005 stratix device handbook, volume 1 introduction stratix devices are available in up to four speed grades, -5, -6, -7, and -8, with -5 being the fastest. table 1?6 shows stratix device speed-grade offerings. table 1?5. stratix fineli ne bga package sizes dimension 484 pin 672 pin 780 pin 1,020 pin 1,508 pin pitch (mm) 1.00 1.00 1.00 1.00 1.00 area (mm 2 ) 529 729 841 1,089 1,600 length width (mm mm) 23 23 27 27 29 29 33 33 40 40 table 1?6. stratix device speed grades device 672-pin bga 956-pin bga 484-pin fineline bga 672-pin fineline bga 780-pin fineline bga 1,020-pin fineline bga 1,508-pin fineline bga ep1s10 -6, -7 -5, -6, -7 -6, -7 -5, -6, -7 ep1s20 -6, -7 -5, -6, -7 -6, -7 -5, -6, -7 ep1s25 -6, -7 -6, -7, -8 -5, -6, -7 -5, -6, -7 ep1s30 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7 ep1s40 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7 -5, -6, -7 ep1s60 -6, -7 -5, -6, -7 -6, -7 ep1s80 -6, -7 -5, -6, -7 -5, -6, -7 1?6 altera corporation stratix device handbook, volume 1 july 2005 features altera corporation 2?1 july 2005 2. stratix architecture functional description stratix ? devices contain a two-dimensional row- and column-based architecture to implement custom logic. a series of column and row interconnects of varying length and speed provide signal interconnects between logic array bloc ks (labs), memory block structures, and dsp blocks. the logic array consists of labs, wi th 10 logic elements (les) in each lab. an le is a small unit of logic providing efficient implementation of user logic functions. labs are grouped into rows and columns across the device. m512 ram blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). these blocks prov ide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 mhz. m512 blocks are grouped into columns across the device in between certain labs. m4k ram blocks are true dual-port me mory blocks with 4k bits plus parity (4,608 bits). these blocks provide dedicated true dual-port, simple dual-port, or single-por t memory up to 36-bits wide at up to 291 mhz. these blocks are grouped into columns across the device in between certain labs. m-ram blocks are true dual-port me mory blocks with 512k bits plus parity (589,824 bits). these blocks provide dedicated true dual-port, simple dual-port, or single-port me mory up to 144-bits wide at up to 269 mhz. several m-ram blocks are located individually or in pairs within the device?s logic array. digital signal processing (dsp) blocks can implem ent up to either eight full-precision 9 9-bit multipliers, four full-precision 18 18-bit multipliers, or one full -precision 36 36-bit mul tiplier with add or subtract features. these blocks also contain 18-bit input shift registers for digital signal processing applications, including fir and infinite impulse response (iir) filters. dsp blocks are grouped into two columns in each device. each stratix device i/o pin is fed by an i/o element (ioe) located at the end of lab rows and columns around the periphery of the device. i/o pins support numerous single-ended and differ ential i/o standards. each ioe contains a bidirectional i/o buffer and six registers for registering input, output, and output -enable signals. when used with s51002-3.2 2?2 altera corporation stratix device handbook, volume 1 july 2005 functional description dedicated clocks, these registers provide exceptional performance and interface support with external memory devi ces such as ddr sdram, fcram, zbt, and qdr sram devices. high-speed serial interface channels support transfers at up to 840 mbps using lvds, lvpecl, 3.3-v pcml, or hypertransport technology i/o standards. figure 2?1 shows an overview of the stratix device. figure 2?1. stratix block diagram m512 ram blocks for dual-port memory, shift registers, & fifo buffers dsp blocks for multiplication and full implementation of fir filters m4k ram blocks for true dual-port memory & other embedded memory functions ioes support ddr, pci, gtl+, sstl-3, sstl-2, hstl, lvds, lvpecl, pcml, hypertransport & other i/o standards ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes ioes labs labs ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs ioes ioes labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs labs dsp block m-ram block altera corporation 2?3 july 2005 stratix device handbook, volume 1 stratix architecture the number of m512 ram, m4k ram, and dsp blocks varies by device along with row and column numbers and m-ram blocks. table 2?1 lists the resources available in stratix devices. logic array blocks each lab consists of 10 les, le carry chains, lab control signals, local interconnect, lut chain, and register chain connection lines. the local interconnect transfers signals between les in the same lab. lut chain connections transfer the output of one le?s lut to the adjacent le for fast sequential lut connections within the same lab. register chain connections transfer the ou tput of one le?s register to the adjacent le?s register within an lab. the quartus ? ii compiler places associated logic within an lab or adjacent labs, allowing the use of local, lut chain, and register chain connections for performance and area efficiency. figure 2?2 shows the stratix lab. table 2?1. stratix device resources device m512 ram columns/blocks m4k ram columns/blocks m-ram blocks dsp block columns/blocks lab columns lab rows ep1s10 4 / 94 2 / 60 1 2 / 6 40 30 ep1s20 6 / 194 2 / 82 2 2 / 10 52 41 ep1s25 6 / 224 3 / 138 2 2 / 10 62 46 ep1s30 7 / 295 3 / 171 4 2 / 12 67 57 ep1s40 8 / 384 3 / 183 4 2 / 14 77 61 ep1s60 10 / 574 4 / 292 6 2 / 18 90 73 ep1s80 11 / 767 4 / 364 9 2 / 22 101 91 2?4 altera corporation stratix device handbook, volume 1 july 2005 logic array blocks figure 2?2. stratix lab structure lab interconnects the lab local interconnect can drive les within the same lab. the lab local interconnect is driven by column and row interconnects and le outputs within the same lab. ne ighboring labs, m512 ram blocks, m4k ram blocks, or dsp blocks from th e left and right can also drive an lab?s local interconnect through the direct link connection. the direct link connection feature minimi zes the use of row and column interconnects, providing higher performance and flexibility. each le can drive 30 other les through fast local and direct link interconnects. figure 2?3 shows the direct link connection. direct link interconnect from adjacent block direct link interconnect to adjacent block row interconnects of variable speed & length column interconnects of variable speed & length three-sided architecture?local interconnect is driven from either side by columns & labs, & from above by rows local interconnect lab direct link interconnect from adjacent block direct link interconnect to adjacent block altera corporation 2?5 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?3. direct link connection lab control signals each lab contains dedicated logic for driving control signals to its les. the control signals include two clocks, two clock enables, two asynchronous clears, synchronous cl ear, asynchronous preset/load, synchronous load, and add/subtract control signals. this gives a maximum of 10 control signals at a ti me. although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. each lab can use two clocks and two clock enable signals. each lab?s clock and clock enable signals are linked. for exampl e, any le in a particular lab using the labclk1 signal will also use labclkena1 . if the lab uses both the rising and falling edges of a clock, it also uses both lab-wide clock signals. de-asserting th e clock enable signal will turn off the lab-wide clock. each lab can use two asynchronous clear signals and an asynchronous load/preset signal. the as ynchronous load acts as a preset when the asynchronous load data input is tied high. lab direct link interconnect to right direct link interconnect from right lab, trimatrix memory block, dsp block, or ioe output direct link interconnect from left lab, trimatrix memory block, dsp block, or ioe output local interconnect direct link interconnect to left 2?6 altera corporation stratix device handbook, volume 1 july 2005 logic elements with the lab-wide addnsub control signal, a single le can implement a one-bit adder and subtractor. this saves le resources and improves performance for logic functions such as dsp correlators and signed multipliers that alternate between addition and subtraction depending on data. the lab row clocks [7..0] and lab local interconnect generate the lab- wide control signals. the multitrack tm interconnect?s inherent low skew allows clock and control signal di stribution in addition to data. figure 2?4 shows the lab control signal generation circuit. figure 2?4. lab-wide control signals logic elements the smallest unit of logic in the st ratix architecture, the le, is compact and provides advanced feat ures with efficient logic utilization. each le contains a four-input lut, which is a function generator that can implement any function of four variable s. in addition, each le contains a programmable register and carry chain with carry select capability. a single le also supports dynamic single bit addition or subtraction mode selectable by an lab-wide control signal. each le drives all types of interconnects: local, row, column, lut chain, register chain, and direct link interconnects. see figure 2?5 . labclkena1 labclk2 labclk1 labclkena2 asyncload or labpre syncload dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect labclr1 labclr2 synclr addnsub 8 altera corporation 2?7 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?5. stratix le each le?s programmable register can be configured for d, t, jk, or sr operation. each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. global signals, general-purpose i/o pins, or any internal logic can drive the register?s clock and clear control signals. ei ther general-purpose i/o pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. the asynchronous load data input comes from the data3 input of the le. for combinator ial functions, the register is bypassed and the output of the lut dr ives directly to the outputs of the le. each le has three outputs that drive the local, row, and column routing resources. the lut or register ou tput can drive these three outputs independently. two le outputs drive column or row and direct link routing connections and one drives local interconnect resources. this allows the lut to drive one output while the register drives another output. this feature, called register packing, improves device utilization because the device can use the register and the lut for unrelated labclk1 labclk2 labclr2 labpre/aload carry-in1 carry-in0 lab carry-in clock & clock enable select lab carry-out carry-out1 carry-out0 look-up ta b l e (lut) carry chain row, column, and direct link routing row, column, and direct link routing programmable register prn/ald clrn d q ena register bypass packed register select chip-wide reset labclkena1 labclkena2 synchronous load and clear logic lab-wide synchronous load lab-wide synchronous clear asynchronous clear/preset/ load logic data1 data2 data3 data4 lut chain routing to next le labclr1 local routing register chain output a data addnsub register feedback register chain routing from previous le 2?8 altera corporation stratix device handbook, volume 1 july 2005 logic elements functions. another special packing mo de allows the register output to feed back into the lut of the same le so that the register is packed with its own fan-out lut. this provides another mechanism for improved fitting. the le can also drive out registered and unregistered versions of the lut output. lut chain & register chain in addition to the three general routing outputs, the les within an lab have lut chain and register chain ou tputs. lut chain connections allow luts within the same lab to cascad e together for wide input functions. register chain outputs allow register s within the same lab to cascade together. the register chain output allows an lab to use luts for a single combinatorial function and the register s to be used for an unrelated shift register implementation. these resources speed up connections between labs while saving local in terconnect resources. see ?multitrack interconnect? on page 2?14 for more information on lut chain and register chain connections. addnsub signal the le?s dynamic adder/subtractor feature saves logic resources by using one set of les to implement both an adder and a subtractor. this feature is controlled by the lab-wide control signal addnsub . the addnsub signal sets the lab to perform either a + b or a ? b. the lut computes addition, and subtraction is computed by adding the two?s complement of the intended subtractor . the lab-wide signal converts to two?s complement by inverting the b bits within the lab and setting carry-in = 1 to add one to the least si gnificant bit (lsb). the lsb of an adder/subtractor must be placed in the first le of the lab, where the lab-wide addnsub signal automatic ally sets the carry-in to 1. the quartus ii compiler automatically plac es and uses the adder/subtractor feature when using adder/subtra ctor parameterized functions. le operating modes the stratix le can operate in one of the following modes: normal mode dynamic arithmetic mode each mode uses le resources differently. in each mode, eight available inputs to the le?the four data inputs from the lab local interconnect; carry-in0 and carry-in1 from the previous le; the lab carry-in from the previous carry-chain lab; and the register chain connection? are directed to different destinatio ns to implement the desired logic function. lab-wide signals provid e clock, asynchronous clear, altera corporation 2?9 july 2005 stratix device handbook, volume 1 stratix architecture asynchronous preset lo ad, synchronous clear, synchronous load, and clock enable control for the register. these lab-wide signals are available in all le modes. the addnsub control signal is allowed in arithmetic mode. the quartus ii software, in conjunct ion with parameterized functions such as library of parameterized mo dules (lpm) function s, automatically chooses the appropriate mode for co mmon functions such as counters, adders, subtractors, and arithmetic functions. if required, you can also create special-purpose functions that specify which le operating mode to use for optimal performance. normal mode the normal mode is suitable for general logic applications and combinatorial functions. in normal mo de, four data inputs from the lab local interconnect are inputs to a four-input lut (see figure 2?6 ). the quartus ii compiler automaticall y selects the carry-in or the data3 signal as one of the inputs to th e lut. each le can use lut chain connections to drive its combinatorial ou tput directly to the next le in the lab. asynchronous load data fo r the register comes from the data3 input of the le. les in normal mode support packed registers. figure 2?6. le in normal mode note to figure 2?6 : (1) this signal is only allowed in normal mode if the le is at the end of an adder/subtractor chain. data1 4-input lut data2 data3 cin (from cout of previous le) data4 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) aload (lab wide) ald/pre clrn d q ena a data sclear (lab wide) sload (lab wide) register chain connection lut chain connection register chain output row, column, and direct link routing row, column, and direct link routing local routing register feedback (1) 2?10 altera corporation stratix device handbook, volume 1 july 2005 logic elements dynamic arithmetic mode the dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. an le in dynamic arithmetic mode uses four 2-input luts configurable as a dynamic adder/subtractor. the first two 2-input luts compute two summations based on a possible carry-in of 1 or 0; the other two luts generate carry outputs for the two chains of the ca rry select circuitry. as shown in figure 2?7 , the lab carry-in signal selects either the carry-in0 or carry-in1 chain. the selected chain?s logic level in turn determines which parallel sum is generated as a combinatorial or registered output. for example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1 . the other two luts use the data1 and data2 signals to generate two possible carry-out signals?one for a carry of 1 and the other for a carry of 0. the carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. les in arithmetic mode can drive out registered and unregistered versions of the lut output. the dynamic arithmetic mode also of fers clock enable, counter enable, synchronous up/down control, sync hronous clear, sy nchronous load, and dynamic adder/subtrac tor options. the lab local interconnect data inputs generate the counter enable and synchronous up/down control signals. the synchronous clear and synchronous load options are lab- wide signals that affect all registers in the lab. the quartus ii software automatically places any registers that are not used by the counter into other labs. the addnsub lab-wide signal controls whether the le acts as an adder or subtractor. altera corporation 2?11 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?7. le in dynamic arithmetic mode note to figure 2?7 : (1) the addnsub signal is tied to the carry input for the first le of a carry chain only. carry-select chain the carry-select chain provides a very fast carry-select function between les in arithmetic mode. the carry-sel ect chain uses th e redundant carry calculation to increase the speed of ca rry functions. the le is configured to calculate outputs for a possible carry-in of 1 and carry-in of 0 in parallel. the carry-in0 and carry-in1 signals from a lower-order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the lut and the next port ion of the carry chain. carry-select chains can begin in any le within an lab. the speed advantage of the carry-select chain is in the parallel pre- computation of carry chains. si nce the lab carry-in selects the precomputed carry ch ain, not every le is in th e critical path. only the propagation delay between lab carry-in generation (le 5 and le 10) are now part of the critical path. this feature allows the stratix architecture to implement high-speed counters, adders , multipliers, pa rity functions, and comparators of arbitrary width. data1 lut data2 data3 addnsub (lab wide) clock (lab wide) ena (lab wide) aclr (lab wide) ald/pre clrn d q ena a data register chain connection lut lut lut carry-out1 carry-out0 lab carry-in carry-in0 carry-in1 (1) sclear (lab wide) sload (lab wide) lut chain connection register chain output row, column, and direct link routing row, column, and direct link routing local routing aload (lab wide) register feedback 2?12 altera corporation stratix device handbook, volume 1 july 2005 logic elements figure 2?8 shows the carry-select circuitry in an lab for a 10-bit full adder. one portion of the lut generates the sum of two bits using the input signals and the appr opriate carry-in bit; the sum is routed to the output of the le. the register can be bypassed for simple adders or used for accumulator functions. another portion of the lut generates carry- out bits. an lab-wide carry in bit selects which chain is used for the addition of given inputs. the ca rry-in signal for each chain, carry-in0 or carry-in1 , selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. th e final carry-out signal is routed to an le, where it is fed to local, row, or column interconnects. the quartus ii compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. parameterized functions such as lpm functions autom atically take advantage of carry chains for the appropriate functions. the quartus ii compiler creates carr y chains longer than 10 les by linking labs together automatically. for enhanced fitting, a long carry chain runs vertically a llowing fast horizontal connections to trimatrix ? memory and dsp blocks. a carry chai n can continue as far as a full column. altera corporation 2?13 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?8. carry select chain clear & preset logic control lab-wide signals control the logic for the register?s clear and preset signals. the le directly supports an asynchronous clear and preset function. the register preset is achi eved through the asynchronous load of a logic high. the direct asynchro nous preset does not require a not- gate push-back technique. stratix devices support simultaneous preset/ le4 le3 le2 le1 a1 b1 a2 b2 a3 b3 a4 b4 sum1 sum2 sum3 sum4 le10 le9 le8 le7 a7 b7 a8 b8 a9 b9 a10 b10 sum7 le6 a6 b6 sum6 le5 a5 b5 sum5 sum8 sum9 sum10 01 01 lab carry-in lab carry-out lut lut lut lut data1 lab carry-in data2 carry-in0 carry-in1 carry-out0 carry-out1 sum 2?14 altera corporation stratix device handbook, volume 1 july 2005 multitrack interconnect asynchronous load, and clear signals. an asynchronous clear signal takes precedence if both signals are as serted simultaneously. each lab supports up to two clears and one preset signal. in addition to the clear and preset ports, stratix devices provide a chip- wide reset pin ( dev_clrn ) that resets all registers in the device. an option set before compilation in the qu artus ii software controls this pin. this chip-wide reset overrides all other control signals. multitrack interconnect in the stratix architecture, connecti ons between les, trimatrix memory, dsp blocks, and device i/o pins are provided by the multitrack interconnect structur e with directdrive tm technology. the multitrack interconnect consists of continuous , performance-optimi zed routing lines of different lengths and speeds used for inter- and intra-design block connectivity. the quartus ii compiler au tomatically places critical design paths on faster interconnects to improve design performance. directdrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. the multitrack interconnect and directdrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycl es that typically follow design changes and additions. the multitrack interconnect consists of row and column interconnects that span fixed distances. a routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. dedicated row interconnects route signals to and from labs, dsp blocks, and trimatrix memory within the same row. these row resources include: direct link interconnects between labs and adjacent blocks. r4 interconnects traversing four blocks to the right or left. r8 interconnects traversing eigh t blocks to the right or left. r24 row interconnects for high-speed access across the length of the device. the direct link interconnect allows an lab, dsp block, or trimatrix memory block to drive into the local in terconnect of its left and right neighbors and then back into itself . only one side of a m-ram block interfaces with direct link and row interconnects. this provides fast communication between adjacent labs and/or blocks without using row interconnect resources. the r4 interconnects span four labs, three labs and one m512 ram block, two labs and one m4k ram block, or two labs and one dsp block to the right or left of a source lab. these resources are used for fast altera corporation 2?15 july 2005 stratix device handbook, volume 1 stratix architecture row connections in a four-lab region . every lab has its own set of r4 interconnects to drive either left or right. figure 2?9 shows r4 interconnect connections from an lab. r4 interconnects can drive and be driven by dsp blocks and ram blocks and horizontal ioes. for lab interfacing, a primary lab or lab neighbor can drive a given r4 interconnect. for r4 interconnects th at drive to the right, the primary lab and right neighbor can drive on to the interconnect. for r4 interconnects that drive to the left, the primary lab and its left neighbor can drive on to the interconnect. r4 interconnects can drive other r4 interconnects to extend the range of labs they can drive. r4 interconnects can also drive c4 an d c16 interconnects for connections from one row to another. additional ly, r4 interconnects can drive r24 interconnects. figure 2?9. r4 interconnect connections notes to figure 2?9 : (1) c4 interconnects can drive r4 interconnects. (2) this pattern is repeated for every lab in the lab row. the r8 interconnects span eight la bs, m512 or m4k ram blocks, or dsp blocks to the right or left from a sour ce lab. these resources are used for fast row connections in an eight-lab region. every lab has its own set of r8 interconnects to drive either left or right. r8 interconnect connections between labs in a row are similar to the r4 connections shown in figure 2?9 , with the exception that they connect to eight labs to the right or left, not four. like r4 interconnects, r8 interconnects can drive and be driven by all types of architecture blocks. r8 interconnects primary lab (2) r4 interconnect driving left adjacent lab can drive onto another lab's r4 interconnect c4, c8, and c16 column interconnects (1) r4 interconnect driving right lab neighbor lab neighbor 2?16 altera corporation stratix device handbook, volume 1 july 2005 multitrack interconnect can drive other r8 interconnects to ex tend their range as well as c8 interconnects for row-to-row connections. one r8 interconnect is faster than two r4 interconnects connected together. r24 row interconnects span 24 labs and provide the fastest resource for long row connections between labs, trimatrix memory, dsp blocks, and ioes. the r24 row interconnects can cross m-ram blocks. r24 row interconnects drive to other row or column interconnects at every fourth lab and do not drive directly to lab local interconnects. r24 row interconnects drive lab local interconnects via r4 and c4 interconnects. r24 interconnects can drive r24, r4, c16, and c4 interconnects. the column interconnect operates si milarly to the row interconnect and vertically routes signals to and from labs, trimatrix memory, dsp blocks, and ioes. each column of labs is served by a dedicated column interconnect, which vertically routes signals to and from labs, trimatrix memory and dsp blocks, and horizontal ioes. these column resources include: lut chain interconne cts within an lab register chain intercon nects within an lab c4 interconnects traversing a distance of four blocks in up and down direction c8 interconnects traversing a dist ance of eight blocks in up and down direction c16 column interconnects for high -speed vertical routing through the device stratix devices include an enhanced interconnect structure within labs for routing le output to le input connections faster using lut chain connections and register chain conne ctions. the lut chain connection allows the combinatorial output of an le to directly drive the fast input of the le right below it, bypassing the local interconnect. these resources can be used as a high-speed connecti on for wide fan-in functions from le 1 to le 10 in the same lab. the register chain connection allows the register output of one le to connect directly to the register input of the next le in the lab for fast shift registers. the quartus ii compiler automatically takes advantage of th ese resources to improve utilization and performance. figure 2?10 shows the lut chain and register chain interconnects. altera corporation 2?17 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?10. lut chain & register chain interconnects the c4 interconnects span four labs , m512, or m4k blocks up or down from a source lab. every lab has its own set of c4 interconnects to drive either up or down. figure 2?11 shows the c4 interconnect connections from an lab in a column. the c4 interconnects can drive and be driven by all types of architecture bloc ks, including dsp blocks, trimatrix memory blocks, and vertical ioes. for lab interconnection, a primary lab or its lab neighbor can drive a given c4 interconnect. c4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. le 1 le 2 le 3 le 4 le 5 le 6 le 7 le 8 le 9 le 10 lut chain routing to adjacent le local interconnect register chain routing to adjacen t le's register input local interconnect routing among les in the lab 2?18 altera corporation stratix device handbook, volume 1 july 2005 multitrack interconnect figure 2?11. c4 interc onnect connections note (1) note to figure 2?11 : (1) each c4 interconnect can drive either up or down four rows. c4 interconnect drives local and r 4 interconnects up to four rows adjacent lab can drive onto neighboring lab's c4 interconnect c4 interconnect driving up c4 interconnect driving down lab row interconnect local interconnect altera corporation 2?19 july 2005 stratix device handbook, volume 1 stratix architecture c8 interconnects span eight labs, m512, or m4k blocks up or down from a source lab. every lab has its own set of c8 interconnects to drive either up or down. c8 interconnect connections between the labs in a column are similar to the c4 connections shown in figure 2?11 with the exception that they connect to eigh t labs above and below. the c8 interconnects can drive and be driven by all types of architecture blocks similar to c4 interconnects. c8 interconnects can drive each other to extend their range as well as r8 interconnects for column-to-column connections. c8 interconnects are fa ster than two c4 interconnects. c16 column interconnects span a length of 16 labs and provide the fastest resource for long column connections between labs, trimatrix memory blocks, dsp blocks, and ioes. c16 interconnects can cross m- ram blocks and also drive to row and column interconnects at every fourth lab. c16 interconnects drive lab local interconnects via c4 and r4 interconnects and do not drive lab local interconnects directly. all embedded blocks communicate with the logic array similar to lab- to-lab interfaces. each block (i.e., trimatrix memory and dsp blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. these blocks also have direct link interconnects for fast co nnections to and from a neighboring lab. all blocks are fed by the row lab clocks, labclk[7..0] . 2?20 altera corporation stratix device handbook, volume 1 july 2005 multitrack interconnect table 2?2 shows the stratix device?s routing scheme. table 2?2. stratix devi ce routing scheme source destination lut chain register chain local interconnect direct link interconnect r4 interconnect r8 interconnect r24 interconnect c4 interconnect c8 interconnect c16 interconnect le m512 ram block m4k ram block m-ram block dsp blocks column ioe row ioe lut chain v register chain v local interconnect vvvvvvv direct link interconnect v r4 interconnect vvvvv r8 interconnect vvv r24 interconnect vvvv c4 interconnect vv v c8 interconnect vvv c16 interconnect vvvv le vvvvvv vv m512 ram block vvvv vv m4k ram block vvvv vv m-ram block vv dsp blocks vvvv vv column ioe vvvv row ioe v vvvvv altera corporation 2?21 july 2005 stratix device handbook, volume 1 stratix architecture trimatrix memory trimatrix memory consists of three types of ram blocks: m512, m4k, and m-ram blocks. although these me mory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple du al-port, and single-port ram, rom, and fifo buffers. table 2?3 shows the size and features of the different ram blocks. table 2?3. trimatrix memory features (part 1 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (12836bits) m-ram block (4k 144 bits) maximum performance (1) (1) (1) true dual-port memory vv simple dual-port memory vvv single-port memory vvv shift register vv rom vv (2) fifo buffer vvv byte enable vv parity bits vvv mixed clock mode vvv memory initialization vv simple dual-port memory mixed width support vvv true dual-port memory mixed width support vv power-up conditions outputs cl eared outputs cleared outputs unknown register clears input and output registers input and output registers output registers mixed-port read- during-write unknown output/old data unknown output/old data unknown output 2?22 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory 1 violating the setup or hold time on the address registers could corrupt the memory contents. this applies to both read and write operations. memory modes trimatrix memory blocks include inpu t registers that synchronize writes and output registers to pipeline designs and improve system performance. m4k and m-ram memory blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. figure 2?12 shows true dual-port memory. figure 2?12. true dual-port memory configuration configurations 512 1 256 2 128 4 64 8 64 9 32 16 32 18 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 16k 36 8k 64 8k 72 4k 128 4k 144 notes to ta b l e 2 ? 3 : (1) see table 4?36 for maximum performance information. (2) the m-ram block does not support memory initializations. however, the m-ram block can emulate a rom function using a dual-port ram bock. the stratix device must write to the dual-port memory once and then disable the write-enable ports afterwards. table 2?3. trimatrix memory features (part 2 of 2) memory feature m512 ram block (32 18 bits) m4k ram block (12836bits) m-ram block (4k 144 bits) data a [ ] address a [ ] wren a clock a clocken a q a [ ] aclr a data b [ ] address b [ ] wren b clock b clocken b q b [ ] aclr b ab altera corporation 2?23 july 2005 stratix device handbook, volume 1 stratix architecture in addition to true dual-port memory , the memory blocks support simple dual-port and single-por t ram. simple dual-port memory supports a simultaneous read and write and can ei ther read old data before the write occurs or just read the don?t care bits. single-port me mory supports non- simultaneous reads and writes, but the q[] port will output the data once it has been written to the memory (if the outputs are not registered) or after the next rising edge of the clock (if the outputs are registered). for more information, see chapter 2, trimatrix embedded memory blocks in stratix & stratix gx devices of the stratix device handbook, volume 2 . figure 2?13 shows these different ram memory port configurations for trimatrix memory. figure 2?13. simple dual-port & singl e-port memory configurations note to figure 2?13 : (1) two single-port memory blocks can be implemented in a single m4k block as long as each of the two independent block sizes is equal to or less than half of the m4k block size. the memory blocks also enable mixed-width data ports for reading and writing to the ram ports in dual-por t ram configuration. for example, the memory block can be wr itten in 1 mode at port a and read out in 16 mode from port b. data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr data[ ] address[ ] wren inclock inclocken inaclr q[ ] outclock outclocken outaclr single-port memory (1) simple dual-port memory 2?24 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory trimatrix memory architecture can implement pipelined ram by registering both the input and outp ut signals to the ram block. all trimatrix memory block inputs are registered providing synchronous write cycles. in synchronous operatio n, the memory block generates its own self-timed strobe write enable ( wren ) signal derived from the global or regional clock. in contrast, a circuit using asynchronous ram must generate the ram wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren signal. the output registers can be bypassed. flow-through reading is possible in the simple dual-port mo de of m512 and m4k ram blocks by clocking the read enable and read ad dress registers on the negative clock edge and bypassing the output registers. two single-port memory blocks can be implemented in a single m4k block as long as each of the two indepe ndent block sizes is equal to or less than half of the m4k block size. the quartus ii software automatically implements larger memory by combining multiple trimatrix memory blocks. for example, two 256 16-bit ram blocks can be co mbined to form a 256 32-bit ram block. memory performance does n ot degrade for memory blocks using the maximum number of words availa ble in one memory block. logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. to create a la rger high-speed memory block, the quartus ii software automatically co mbines memory blocks with le control logic. clear signals when applied to input registers, the asynchronous clear signal for the trimatrix embedded memory immediately clears the input registers. however, the output of the memory block does not show the effects until the next clock edge. when applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately. parity bit support the memory blocks support a parity bit for each byte. the parity bit, along with internal le logic, can implement parity checking for error detection to ensure data integrity. you can also use parity-size data words to store user-specified control bits . in the m4k and m-ram blocks, byte enables are also available for data in put masking during write operations. altera corporation 2?25 july 2005 stratix device handbook, volume 1 stratix architecture shift register support you can configure embedded memory blocks to implement shift registers for dsp applications such as pseudo-random number generators, multi- channel filtering, auto-correlation, and cross-correlation functions. these and other dsp applications require local data storage, traditionally implemented with standard flip-flops, which can quickly consume many logic cells and routing resources for la rge shift registers. a more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation with th e dedicated circuitry. the size of a w m n shift register is determined by the input data width ( w ), the length of the taps ( m ), and the number of taps ( n ). the size of a w m n shift register must be less than or equal to the maximum number of memory bits in the resp ective block: 576 bits for the m512 ram block and 4,608 bits for the m4 k ram block. the total number of shift register outputs (number of taps n width w ) must be less than the maximum data width of the ram bl ock (18 for m512 blocks, 36 for m4k blocks). to create larger shift regist ers, the memory blocks are cascaded together. data is written into each address locati on at the falling edge of the clock and read from the address at the rising edge of the clock. the shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. figure 2?14 shows the trimatrix memory block in the shift register mode. 2?26 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?14. shift register memory configuration memory block size trimatrix memory provides three different memory sizes for efficient application support. the large number of m512 blocks are ideal for designs with many shallow first-in fi rst-out (fifo) buffers. m4k blocks provide additional resources for ch annelized functions that do not require large amounts of storage. the m-ram blocks provide a large single block of ram ideal for data packet storage. the different-sized blocks allow stratix devices to effici ently support variable-sized memory in designs. the quartus ii software automatical ly partitions the user-defined memory into the embedded memory bloc ks using the most efficient size combinations. you can also manually assign the memory to a specific block size or a mixture of block sizes. m -bit shift register w w m -bit shift register m -bit shift register m -bit shift register w w w w w w w m n shift register n numbe r of taps altera corporation 2?27 july 2005 stratix device handbook, volume 1 stratix architecture m512 ram block the m512 ram block is a simple dual-port memory block and is useful for implementing small fifo buffers, dsp, and clock domain transfer applications. each block contains 576 ram bits (including parity bits). m512 ram blocks can be configured in the following modes: simple dual-port ram single-port ram fifo rom shift register when configured as ram or rom, you can use an initialization file to pre-load the memory contents. the memory address depths and outp ut widths can be configured as 512 1, 256 2, 128 4, 64 8 (64 9 bits with parity), and 32 16 (32 18 bits with parity). mixed-widt h configurations are also possible, allowing different read and write widths. table 2?4 summarizes the possible m512 ram block configurations. when the m512 ram block is configured as a shift register block, a shift register of size up to 576 bits is possible. the m512 ram block can also be configured to support serializer and deserializer applications. by using the mixed-width support in combination with ddr i/o standards, the block can function as a serdes to support low-speed serial i/o standards using global or regional clocks. see ?i/o structure? on page 2?104 for details on dedicated serdes in stratix devices. table 2?4. m512 ram block configur ations (simple dual-port ram) read port write port 512 1 256 2 128 4 64 8 32 16 64 9 32 18 512 1 v v vvv 256 2 v v vvv 128 4 vvv v 64 8 vv v 32 16 vvv v 64 9 v 32 18 v 2?28 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory m512 ram blocks can have different cl ocks on its inputs and outputs. the wren , datain , and write address registers are all clocked together from one of the two cl ocks feeding the block. the read address, rden , and output registers can be clocked by ei ther of the two cl ocks driving the block. this allows the ram block to operate in read/write or input/output clock modes. only the ou tput register can be bypassed. the eight labclk signals or local interconnect can drive the inclock , outclock , wren , rden , inclr , and outclr signals. because of the advanced interconnect between th e lab and m512 ram blocks, les can also control the wren and rden signals and the ram clock, clock enable, and asynchronous clear signals. figure 2?15 shows the m512 ram block control signal generation logic. the ram blocks within st ratix devices have local interconnects to allow les and interconnects to drive into ram blocks. the m512 ram block local interconnect is driven by the r4, r8, c4, c8, and direct link interconnects from adjacent labs. the m512 ram blocks can communicate with labs on either the left or righ t side through these row interconnects or with lab columns on the left or right side with the column interconnects. up to 10 direct link input connections to the m512 ram block are possible from the left adjacent labs and another 10 possible from the right adjacent lab. m512 ram outputs can also connect to left and right labs throug h 10 direct link interconnects. the m512 ram block has equal opportunity for access and performance to and from labs on either its left or right side. figure 2?16 shows the m512 ram block to logic array interface. altera corporation 2?29 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?15. m512 ram block control signals inclocken outclock inclock outclocken rden wren dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect local interconnect inclr outclr 8 local interconnect local interconnect 2?30 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?16. m512 ram block lab row interface m4k ram blocks the m4k ram block includes support for true dual-port ram. the m4k ram block is used to implement buffer s for a wide variety of applications such as storing processor code, im plementing lookup schemes, and implementing larger memory applications. each block contains 4,608 ram bits (including parity bits). m4k ram blocks can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo rom shift register when configured as ram or rom, you can use an initialization file to pre-load the memory contents. dataout m512 ram block datain clocks 10 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab small ram block local interconnect region c4 and c8 interconnects r4 and r8 interconnects control signals address lab row clocks 2 8 altera corporation 2?31 july 2005 stratix device handbook, volume 1 stratix architecture the memory address depths and outp ut widths can be configured as 4,096 1, 2,048 2, 1,024 4, 512 8 (or 512 9 bits), 256 16 (or 256 18 bits), and 128 32 (or 128 36 bits). the 128 32- or 36-bit configuration is not available in the true dual-port mode. mixed-width configurations are also possible, allowing different read and write widths. tables 2?5 and 2?6 summarize the possible m4k ram block configurations. when the m4k ram block is configured as a shift register block, you can create a shift register up to 4,608 bits ( w m n ). table 2?5. m4k ram block confi gurations (simple dual-port) read port write port 4k 12k 21k 4 512 8 256 16 128 32 512 9 256 18 128 36 4k 1 vvvv v v 2k 2 vvvv v v 1k 4 vvvv v v 512 8 vvvv v v 256 16 vvvv v v 128 32 vvvv v v 512 9 vv v 256 18 vv v 128 36 vv v table 2?6. m4k ram block confi gurations (true dual-port) port a port b 4k 12k 21k 4 512 8 256 16 512 9 256 18 4k 1 vvvvv 2k 2 vvvvv 1k 4 vvvvv 512 8 vvvvv 256 16 vvvvv 512 9 vv 256 18 vv 2?32 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory m4k ram blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. the byte enables al low the input data to be masked so the device can write to specific bytes. the unwritten bytes retain the previous written value. table 2?7 summarizes the byte selection. the m4k ram blocks allow for differ ent clocks on their inputs and outputs. either of the two clocks feeding the block can clock m4k ram block registers ( renwe , address, byte enable, datain , and output registers). only the output register can be bypassed. the eight labclk signals or local interconnects can drive the control signals for the a and b ports of the m4k ram block. les can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr_b , clocken_a , and clocken_b signals, as shown in figure 2?17 . the r4, r8, c4, c8, and direct link interconnects from adjacent labs drive the m4k ram block local inte rconnect. the m4k ram blocks can communicate with labs on either the left or righ t side through these row resources or with lab columns on either the right or left with the column resources. up to 10 direct link inpu t connections to the m4k ram block are possible from the left adjacent labs and another 10 possible from the right adjacent lab. m4k ram block outputs can also connect to left and right labs through 10 direct link interconnects each. figure 2?18 shows the m4k ram block to logic array interface. table 2?7. byte enable for m4k blocks notes (1) , (2) byteena[3..0] datain 18 datain 36 [0] = 1 [8..0] [8..0] [1] = 1 [17..9] [17..9] [2] = 1 ? [26..18] [3] = 1 ? [35..27] notes to ta b l e 2 ? 7 : (1) any combination of byte enables is possible. (2) byte enables can be used in the sa me manner with 8-bit words, i.e., in 16 and 32 modes. altera corporation 2?33 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?17. m4k ram bl ock control signals figure 2?18. m4k ram block lab row interface clocken_a renwe_a clock_a alcr_a alcr_b renwe_b dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect local interconnect clocken_b clock_b 8 local interconnect local interconnect local interconnect local interconnect local interconnect dataout m4k ram block datain address 10 direct link interconnect from adjacent lab direct link interconnect to adjacent lab direct link interconnect from adjacent lab direct link interconnect to adjacent lab m4k ram block local interconnect region c4 and c8 interconnects r4 and r8 interconnects lab row clocks clocks byte enable control signals 8 2?34 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory m-ram block the largest trimatrix memory block, the m-ram block, is useful for applications where a large volume of data must be stored on-chip. each block contains 589,824 ram bits (inc luding parity bits). the m-ram block can be configured in the following modes: true dual-port ram simple dual-port ram single-port ram fifo ram you cannot use an initialization file to initialize the contents of a m-ram block. all m-ram block contents powe r up to an undefined value. only synchronous operation is supported in the m-ram block, so all inputs are registered. output registers ca n be bypassed. the memory address and output width can be configured as 64k 8 (or 64k 9 bits), 32k 16 (or 32k 18 bits), 16k 32 (or 16k 36 bits), 8k 64 (or 8k 72 bits), and 4k 128 (or 4k 144 bits). the 4k 128 configuration is unavailable in true dual-port mode because there are a total of 144 data output drivers in the block. mixed-widt h configurations are al so possible, allowing different read and write widths. tables 2?8 and 2?9 summarize the possible m-ram block configurations: table 2?8. m-ram block configur ations (simple dual-port) read port write port 64k 932k 18 16k 36 8k 72 4k 144 64k 9 vvvv 32k 18 vvvv 16k 36 vvvv 8k 72 vvvv 4k 144 v altera corporation 2?35 july 2005 stratix device handbook, volume 1 stratix architecture the read and write operation of the memory is controlled by the wren signal, which sets the ports into either read or write modes. there is no separate read enable ( re ) signal. writing into ram is controlled by both the wren and byte enable ( byteena ) signals for each port. the default value for the byteena signal is high, in which case writing is controlled only by the wren signal. the byte enables are available for th e 18, 36, and 72 modes. in the 144 simple dual-port mode, the two sets of byteena signals ( byteena_a and byteena_b ) are combined to form the necessary 16 byte enables. tables 2?10 and 2?11 summarize the byte selection. table 2?9. m-ram block confi gurations (true dual-port) port a port b 64k 932k 18 16k 36 8k 72 64k 9 vvvv 32k 18 vvvv 16k 36 vvvv 8k 72 vvvv table 2?10. byte enable for m-ram blocks notes (1) , (2) byteena[3..0] datain 18 datain 36 datain 72 [0] = 1 [8..0] [8..0] [8..0] [1] = 1 [17..9] [17..9] [17..9] [2] = 1 ? [26..18] [26..18] [3] = 1 ? [35..27] [35..27] [4] = 1 ? ? [44..36] [5] = 1 ? ? [53..45] [6] = 1 ? ? [62..54] [7] = 1 ? ? [71..63] 2?36 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory similar to all ram blocks, m-ram bloc ks can have different clocks on their inputs and output s. all input registers? renwe , datain , address, and byte enable registers?are clocke d together from either of the two clocks feeding the block. the output register can be bypassed. the eight labclk signals or local interconnect can drive the control signals for the a and b ports of the m-ram block. les can also control the clock_a , clock_b , renwe_a , renwe_b , clr_a , clr _b , clocken_a , and clocken_b signals as shown in figure 2?19 . table 2?11. m-ram combined byte selection for 144 mode notes (1) , (2) byteena[15..0] datain 144 [0] = 1 [8..0] [1] = 1 [17..9] [2] = 1 [26..18] [3] = 1 [35..27] [4] = 1 [44..36] [5] = 1 [53..45] [6] = 1 [62..54] [7] = 1 [71..63] [8] = 1 [80..72] [9] = 1 [89..81] [10] = 1 [98..90] [11] = 1 [107..99] [12] = 1 [116..108] [13] = 1 [125..117] [14] = 1 [134..126] [15] = 1 [143..135] notes to tables 2?10 and 2?11 : (1) any combination of byte enables is possible. (2) byte enables can be used in the sa me manner with 8-bit words, i.e., in 16, 32, 64, and 128 modes. altera corporation 2?37 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?19. m-ram block control signals one of the m-ram block?s horizontal sides drive the address and control signal (clock, renwe, byteena, etc.) inputs. typically, the horizontal side closest to the device perimeter contains the interfaces. the one exception is when two m-ram blocks are paired ne xt to each other. in this case, the side of the m-ram block opposite the common side of the two blocks contains the input interface. the top and bottom sides of any m-ram block contain data input and output in terfaces to the logic array. the top side has 72 data inputs and 72 data ou tputs for port b, and the bottom side has another 72 data inputs and 72 data outputs for port a. figure 2?20 shows an example floorplan for the ep1s60 device and the location of the m-ram interfaces. clocken_a clock_b clock_a clocken_b aclr_a aclr_b dedicated row lab clocks local interconnect local interconnect local interconnect local interconnect renwe_a renwe_b 8 local interconnect local interconnect local interconnect local interconnect 2?38 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?20. ep1s60 device with m-ram interface locations note (1) note to figure 2?20 : (1) device shown is an ep1s60 device. the number and position of m-ram blocks varies in other devices. the m-ram block local interconnect is driven by the r4, r8, c4, c8, and direct link interconnects from ad jacent labs. for independent m-ram blocks, up to 10 direct link address and control signal input connections to the m-ram block are possible from the left adjacent labs for m-ram m-ram block m-ram block dsp blocks dsp blocks m4k blocks m512 blocks labs m-ram block m-ram block m-ram block m-ram block m-ram pairs interface to top, bottom, and side opposite of block-to-block border. independent m-ram blocks interface to top, bottom, and side facing device perimeter for easy access to horizontal i/o pins. altera corporation 2?39 july 2005 stratix device handbook, volume 1 stratix architecture blocks facing to the left, and another 10 possible from the right adjacent labs for m-ram blocks facing to the right. for column interfacing, every m-ram column unit connects to the ri ght and left column lines, allowing each m-ram column unit to communicat e directly with three columns of labs. figures 2?21 through 2?23 show the interface between the m-ram block and the logic array. 2?40 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?21. left-facing m-ram to interconnect interface notes (1) , (2) notes to figure 2?21 : (1) only r24 and c16 interconnects cross the m-ram block boundaries. (2) the right-facing m-ram block has interf ace blocks on the right side, but none on the left. b1 to b6 and a1 to a6 orientation is clipped across the vertical axis for right-facing m-ram blocks. m-ram block port b port a row unit interface allows lab rows to drive address and control signals to m-ram block column interface block allows lab columns to drive datain and dataout to and from m-ram block labs in row m-ram boundary labs in column m-ram boundary m512 ram block columns column interface block drives to and from c4 and c8 interconnects lab interface blocks r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 altera corporation 2?41 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?22. m-ram row unit interface to interconnect lab row interface block m-ram block 10 up to 24 addressa addressb renwe_a renwe_b byteena a [ ] byteena b [ ] clocken_a clocken_b clock_a clock_b aclr_a aclr_b m-ram block to lab row interface block interconnect region r4 and r8 interconnects c4 and c8 interconnects direct link interconnects 2?42 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?23. m-ram column unit interface to interconnect 12 12 column interface block m-ram block to lab row interface block interconnec t region datain dataout lab lab lab c4 and c8 interconnects m-ram block altera corporation 2?43 july 2005 stratix device handbook, volume 1 stratix architecture table 2?12 shows the input and output data signal connections for the column units (b1 to b6 and a1 to a6). it also shows the address and control signal input connections to the row units (r1 to r11). table 2?12. m-ram row & column interface unit signals unit interface block input signals output signals r1 addressa[7..0] r2 addressa[15..8] r3 byte_enable_a[7..0] renwe_a r4 - r5 - r6 clock_a clocken_a clock_b clocken_b r7 - r8 - r9 byte_enable_b[7..0] renwe_b r10 addressb[15..8] r11 addressb[7..0] b1 datain_b[71..60] dataout_b[71..60] b2 datain_b[59..48] dataout_b[59..48] b3 datain_b[47..36] dataout_b[47..36] b4 datain_b[35..24] dataout_b[35..24] b5 datain_b[23..12] dataout_b[23..12] b6 datain_b[11..0] dataout_b[11..0] a1 datain_a[71..60] dataout_a[71..60] a2 datain_a[59..48] dataout_a[59..48] a3 datain_a[47..36] dataout_a[47..36] a4 datain_a[35..24] dataout_a[35..24] a5 datain_a[23..12] dataout_a[23..12] a6 datain_a[11..0] dataout_a[11..0] 2?44 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory independent clock mode the memory blocks implement indepe ndent clock mode for true dual- port memory. in this mode, a separate clock is available for each port (ports a and b). clock a controls all registers on the port a side, while clock b controls all registers on the port b side. each port, a and b, also supports independent clock enables and asynchronous clear signals for port a and b registers. figure 2?24 shows a trimatrix memory block in independent clock mode. altera corporation 2?45 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?24. independent clock mode notes (1) , (2) notes to figure 2?24 (1) all registers shown have asynchronous clear ports. (2) violating the setup or hold time on the address registers could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out clken a clock a d ena q wren a 8 lab row clocks q a [ ] 8 data b [ ] address b [ ] clken b clock b wren b q b [ ] ena ab ena d q d ena q byteena a [ ] byte enable a byte enable b byteena b [ ] ena d q ena d q ena d q d q write pulse generator write pulse generator 2?46 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory input/output clock mode input/output clock mode can be im plemented for both the true and simple dual-port memory modes. on ea ch of the two ports, a or b, one clock controls all registers for inputs into the memory block: data input, wren , and address. the other clock co ntrols the block?s data output registers. each memory block port, a or b, also supports independent clock enables and asynchronous cl ear signals for input and output registers. figures 2?25 and 2?26 show the memory block in input/output clock mode. altera corporation 2?47 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?25. input/output clock m ode in true dual-port mode notes (1) , (2) notes to figure 2?25 : (1) all registers shown have asynchronous clear ports. (2) violating the setup or hold time on the address registers could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 ( 2 ) 512 8 1,024 4 2,04 8 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out clken a clock a d ena q wren a 8 lab row clocks q a [ ] 8 data b [ ] address b [ ] clken b clock b wren b q b [ ] ena ab ena d q ena d q ena d q d q d ena q byteena a [ ] byte enable a byte enable b byteena b [ ] ena d q write pulse generator write pulse generator 2?48 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?26. input/output clock mode in simple dual-port mode notes (1) , (2) notes to figure 2?26 : (1) all registers shown except the rden register have asynchronous clear ports. (2) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out outclken inclken wrclock rdclock wren rden 8 lab row clocks to multitrac k interconnect d ena q byteena[ ] byte enable write pulse generator altera corporation 2?49 july 2005 stratix device handbook, volume 1 stratix architecture read/write clock mode the memory blocks implement read/w rite clock mode for simple dual- port memory. you can use up to two cl ocks in this mode. the write clock controls the block?s data inputs, wraddress , and wren . the read clock controls the data output, rdaddress , and rden . the memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. figure 2?27 shows a memory block in read/write clock mode. 2?50 altera corporation stratix device handbook, volume 1 july 2005 trimatrix memory figure 2?27. read/write clock m ode in simple dual-port mode notes (1) , (2) notes to figure 2?27 : (1) all registers shown except the rden register have asynchronous clear ports. (2) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,04 8 2 4,096 1 data in read address write address write enable read enable data out outclken inclken wrclock rdclock wren rden 8 lab row clocks to multitrac k interconnect d ena q byteena[ ] byte enable write pulse generator altera corporation 2?51 july 2005 stratix device handbook, volume 1 stratix architecture single-port mode the memory blocks also support single-port mode, used when simultaneous reads and writes are not required. see figure 2?28 . a single block in a memory block can support up to two single-port mode ram blocks in the m4k ram bloc ks if each ram block is less than or equal to 2k bits in size. figure 2?28. single-port mode note (1) note to figure 2?28 : (1) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q d ena q data[ ] address[ ] ram/rom 256 16 512 8 1,024 4 2,04 8 2 4,096 1 data in address write enable data out outclken inclken inclock outclock write pulse generator wren 8 lab row clocks to multitrac k interconnect 2?52 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block digital signal processing block the most commonly used dsp function s are finite impuls e response (fir) filters, complex fir filter s, infinite impulse response (iir) filters, fast fourier transform (fft) functions, direct cosine transform (dct) functions, and correlators. all of th ese blocks have the same fundamental building block: the multiplier. additionally, some applications need specialized operations such as mul tiply-add and multiply-accumulate operations. stratix devices provide dsp blocks to meet the arithmetic requirements of these functions. each stratix device has two column s of dsp blocks to efficiently implement dsp functions faster than le-based implementations. larger stratix devices have more dsp blocks per column (see table 2?13 ). each dsp block can be configur ed to support up to: eight 9 9-bit multipliers four 18 18-bit multipliers one 36 36-bit multiplier as indicated, the stratix dsp block can support one 36 36-bit multiplier in a single dsp block. this is true for any matched sign multiplications (either unsigned by unsigned or signed by signed), but the capabilities for dynamic and mixed sign multiplications are handled differently. the following list provides the largest func tions that can fit into a single dsp block. 36 36-bit unsigned by unsigned multiplication 36 36-bit signed by signed multiplication 35 36-bit unsigned by signed multiplication 36 35-bit signed by unsigned multiplication 36 35-bit signed by dynamic sign multiplication 35 36-bit dynamic sign by signed multiplication 35 36-bit unsigned by dy namic sign multiplication 36 35-bit dynamic sign by unsigned multiplication 35 35-bit dynamic sign multiplicati on when the sign controls for each operand are different 36 36-bit dynamic sign multiplication when the same sign control is used for both operands 1 this list only shows functions that can fit into a single dsp block. multiple dsp blocks can support larger multiplication functions. figure 2?29 shows one of the columns with surrounding lab rows. altera corporation 2?53 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?29. dsp blocks arranged in columns dsp block column 8 lab rows dsp block 2?54 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block table 2?13 shows the number of dsp blocks in each stratix device. dsp block multipliers can optionally feed an adder/subtractor or accumulator within the block depend ing on the configuration. this makes routing to les easier, saves le routing resources, and increases performance, because al l connections and blocks are within the dsp block. additionally, the dsp bloc k input registers can efficiently implement shift registers for fir filter applications. figure 2?30 shows the top-level diagram of the dsp block configured for 18 18-bit multiplier mode. figure 2?31 shows the 9 9-bit multiplier configuration of the dsp block. table 2?13. dsp blocks in stratix devices notes (1) , (2) device dsp blocks total 9 9 multipliers total 18 18 multipliers total 36 36 multipliers ep1s10 6 48 24 6 ep1s20 10 80 40 10 ep1s25 10 80 40 10 ep1s30 12 96 48 12 ep1s40 14 112 56 14 ep1s60 18 144 72 18 ep1s80 22 176 88 22 notes to ta b l e 2 ? 1 3 : (1) each device has either the number of 9 9-, 18 18-, or 36 36-bit multipliers shown. the total number of multipliers for each device is not the sum of all the multipliers. (2) the number of supported multiply fu nctions shown is base d on signed/signed or unsigned/unsigned implementations. altera corporation 2?55 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?30. dsp block diagram for 18 18-bit configuration adder/ subtractor/ accumulator 2 adder/ subtractor/ accumulator 1 summation opt ion a l p i pe lin e reg i ster stage m ul t i p li er stage o u tp u t se l ect ion m ul t i p l e x er opt ion a l o u tp u t reg i ster stage clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena opt ion a l ser i a l s hi ft reg i ster in p u ts fr o m pre viou s dsp b lo c k opt ion a l stage c on f i g u rab l e as a cc u m ul at o r o r d yn am i c a dder / s u btract o r s u mmat ion stage f o r a dd in g fou r m ul t i p li ers to get h er opt ion a l in p u t reg i ster stage wi t h para ll e l in p u t o r s hi ft reg i ster c on f i g u rat ion opt ion a l ser i a l s hi ft reg i ster o u tp u ts t o n e x t dsp b lo c k in t h e c olu m n to multitrack interconnect 2?56 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block figure 2?31. dsp block diagram for 9 9-bit configuration clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 1a summation summation clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 1b clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 2a clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena adder/ subtractor/ 2b clrn dq ena clrn dq ena clrn dq ena output selection multiplexer to multitrack interconnect altera corporation 2?57 july 2005 stratix device handbook, volume 1 stratix architecture the dsp block consists of the following elements: multiplier block adder/output block multiplier block the dsp block multiplier block cons ists of the input registers, a multiplier, and pipeline register fo r pipelining multiply-accumulate and multiply-add/subtract functions as shown in figure 2?32 . figure 2?32. multiplier sub-bloc k within stratix dsp block note to figure 2?32 : (1) these signals can be unregister ed or registered once to match data path pipelines if required. clrn dq ena data a data b result to adder blocks shiftout b shiftout a shiftin a shiftin b aclr[3..0] clock[3..0] ena[3..0] optional multiply-accumulate and multiply-add pipeline sign_a (1) sign_b (1) clrn dq ena clrn dq ena 2?58 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block input registers a bank of optional input registers is located at the input of each multiplier and multiplicand inputs to the multi plier. when these registers are configured for parallel data inputs, they are driven by regular routing resources. you can use a clock signal, asynchronous clear signal, and a clock enable signal to independently co ntrol each set of a and b inputs for each multiplier in the ds p block. you select these control signals from a set of four different clock[3..0] , aclr[3..0] , and ena[3..0] signals that drive the entire dsp block. you can also configure the input registers for a shift register application. in this case, the input registers feed the multiplier and drive two dedicated shift output lines: shiftouta and shiftoutb . the shift outputs of one multiplier block direct ly feed the adjacent multiplier block in the same dsp block (or the next dsp block) as shown in figure 2?33 , to form a shift register chain. this chai n can terminate in an y block, that is, you can create any length of shift regi ster chain up to 224 registers. you can use the input shift registers for fir filter applications. one set of shift inputs can provide data for a filter, and the other are coefficients that are optionally loaded in serial or para llel. when implementing 9 9- and 18 18-bit multipliers, you do not need to implement external shift registers in lab les. you implement all the filter circuitry within the dsp block and its routing resources, savi ng le and general routing resources for general logic. external registers are needed for shift register inputs when using 36 36-bit multipliers. altera corporation 2?59 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?33. multiplier sub-blocks usin g input shift register connections note (1) note to figure 2?33 : (1) either data a or data b input can be set to a parallel input for constant coefficient multiplication. clrn dq ena data a data b a[n] b[n] clrn dq ena clrn dq ena clrn dq ena data a data b a[n e 1] b[n e 1] clrn dq ena clrn dq ena clrn dq ena data a data b a[n e 2] b[n e 2] clrn dq ena clrn dq ena 2?60 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block table 2?14 shows the summary of input register modes for the dsp block. multiplier the multiplier supports 9 9-, 18 18-, or 36 36-bit multiplication. each dsp block supports eight possible 9 9-bit or smaller multipliers. there are four multiplier blocks available for multipliers larger than 9 9 bits but smaller than 18 18 bits. there is one multiplier block available for multipliers larger than 18 18 bits but smaller than or equal to 36 36 bits. the ability to have several small multipliers is useful in applications such as video processing. large mult ipliers greater than 18 18 bits are useful for applications such as the mantissa multiplication of a single- precision floating-point number. the multiplier operands can be sign ed or unsigned numbers, where the result is signed if either input is signed as shown in table 2?15 . the sign_a and sign_b signals provide dynamic control of each operand?s representation: a logic 1 indicates the operand is a signed number, a logic 0 indicates the operand is an unsigned number. these sign signals affect all multipliers and adders within a si ngle dsp block and you can register them to match the data path pipeline. the multipliers are full precision (that is, 18 bits for the 18-bit multiply , 36-bits for the 36-bit multiply, and so on) regardless of whether sign_a or sign_b set the operands as signed or unsigned numbers. table 2?14. input register modes register input mode 9 9 18 18 36 36 parallel input vvv shift register input vv table 2?15. multiplier signed representation data a data b result unsigned unsigned unsigned unsigned signed signed signed unsigned signed signed signed signed altera corporation 2?61 july 2005 stratix device handbook, volume 1 stratix architecture pipeline/post multiply register the output of 9 9- or 18 18-bit mult ipliers can optionally feed a register to pipeline multiply-accu mulate and multiply-add/ subtract functions. for 36 36-bit multipliers, this register will pipeline the multiplier function. adder/output blocks the result of the multiplier sub-blocks are sent to the adder/output block which consist of an adder/subtrac tor/accumulator unit , summation unit, output select multiplexer, and output registers. the results are used to configure the adder/output block as a pure output, accu mulator, a simple two-multiplier adder, four-multiplier adder, or final stage of the 36-bit multiplier. you can configure the adder/output bloc k to use output registers in any mode, and must use output registers for the accumulator. the system cannot use adder/output blocks independently of the multiplier. figure 2?34 shows the adder and output stages. 2?62 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block figure 2?34. adder/o utput blocks note (1) notes to figure 2?34 : (1) adder/output block shown in figure 2?34 is in 18 18-bit mode. in 9 9-bit mode, there are four adder/subtractor blocks and two summation blocks. (2) these signals are either not registered, registered once , or registered twice to match the data path pipeline. adder/ subtractor/ accumulator1 summation result a result b result c result d addnsub1 ( 2 ) accum_sload0 ( 2 ) addnsub3 ( 2 ) si g na ( 2 ) si g nb ( 2 ) accum_sload1 ( 2 ) a cc u m ul at o r f eedbac k a cc u m ul at o r f eedbac k overflow0 adder/ subtractor/ accumulator2 o u tp u t se l ect io n m ul t i p l e x er o u tp u t reg i ster b lo c k overflow1 altera corporation 2?63 july 2005 stratix device handbook, volume 1 stratix architecture adder/subtractor/accumulator the adder/subtractor/accumulator is the first level of the adder/output block and can be used as an accumul ator or as an adder/subtractor. adder/subtractor each adder/subtractor/accumulator block can perform addition or subtraction using the addnsub independent control signal for each first- level adder in 18 18-bit mode. there are two addnsub[1..0] signals available in a dsp block for any configuration. for 9 9-bit mode, one addnsub[1..0] signal controls the top two one-level adders and another addnsub[1..0] signal controls the bottom two one-level adders. a high addnsub signal indicates addition, and a low signal indicates subtraction. the addnsub control signal can be unregistered or registered once or twice when feed ing the adder blocks to match data path pipelines. the signa and signb signals serve the same function as the multiplier block signa and signb signals. the only difference is that these signals can be registered up to two times. these signals are tied to the same signa and signb signals from the multiplier and must be connected to the same clocks and control signals. accumulator when configured for accumulation, th e adder/output block output feeds back to the accumulator as shown in figure 2?34 . the accum_sload[1..0] signal synchronously loads the multiplier result to the accumulator output. this signal can be unregistered or registered once or twice. additionally, the overflow signal indicates the accumulator has overflowed or underflowed in accumulation mode. this signal is always registered and must be externally latched in les if the design requires a latched overflow signal. summation the output of the adder/subtract or/accumulator block feeds to an optional summation block. this bloc k sums the outputs of the dsp block multipliers. in 9 9-bit mode, there are two su mmation blocks providing the sums of two sets of four 9 9-bi t multipliers. in 18 18-bit mode, there is one summation providing the sum of one set of four 18 18-bit multipliers. 2?64 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block output selection multiplexer the outputs from the various elemen ts of the adder/output block are routed through an output selection multiplexer. based on the dsp block operational mode and user settings, the multiplexer selects whether the output from the multiplier, the adder/subtractor/accumulator, or summation block feeds to the output. output registers optional output registers for the dsp block outputs are controlled by four sets of control signals: clock[3..0] , aclr[3..0] , and ena[3..0] . output registers can be used in any mode. modes of operation the adder, subtractor, and accumulate functions of a dsp block have four modes of operation: simple multiplier multiply-accumulator two-multipliers adder four-multipliers adder 1 each dsp block can only support one mode. mixed modes in the same dsp block is not supported. simple multiplier mode in simple multiplier mode, the dsp block drives the multiplier sub-block result directly to the output with or without an output register. up to four 18 18-bit multipliers or eight 9 9-bit multipliers can drive their results directly out of one dsp block. see figure 2?35 . altera corporation 2?65 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?35. simple multiplier mode note to figure 2?35 : (1) these signals are not registered or regist ered once to match the data path pipeline. dsp blocks can also implement one 36 36-bit multiplier in multiplier mode. dsp blocks use four 18 18-bit multipliers combined with dedicated adder and internal shift circuitry to achieve 36-bit multiplication. the input shift regist er feature is not available for the 36 36-bit multiplier. in 36 36-bit mo de, the device can use the register that is normally a multiplier-result-out put register as a pipeline stage for the 36 36-bit multiplier. figure 2?36 shows the 36 36-bit multiply mode. clrn dq ena data a data b data out shiftout b shiftout a shiftin a shiftin b aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena clrn dq ena 2?66 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block figure 2?36. 36 36 multiply mode notes to figure 2?36 : (1) these signals are not registered or registered once to match the pipeline. (2) these signals are not registered, registered once, or registered twice for latency to match the pipeline. clrn dq ena a[17..0] a[17..0] b[17..0] b[17..0] a[35..18] a[35..18] b[35..18] b[35..18] aclr clock ena si g na (1) si g nb (1) clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena data ou t 36 36 multiplier adder si g na ( 2 ) si g nb ( 2 ) altera corporation 2?67 july 2005 stratix device handbook, volume 1 stratix architecture multiply-accumulator mode in multiply-accumulator mode (see figure 2?37 ), the dsp block drives multiplied results to the adder/subtra ctor/accumulator block configured as an accumulator. you can implement one or two multiply-accumulators up to 18 18 bits in one dsp block. the first and third multiplier sub- blocks are unused in this mode, beca use only one multiplier can feed one of two accumulators. the multiply-ac cumulator output can be up to 52 bits?a maximum of a 36-bit result with 16 bits of accumulation. the accum_sload and overflow signals are only available in this mode. the addnsub signal can set the accumulator for decimation and the overflow signal indicates underflow condition. figure 2?37. multiply -accumulate mode notes to figure 2?37 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) these signals are not registered, regi stered once, or registered twice for la tency to match the data path pipeline. two-multipliers adder mode the two-multipliers adder mode uses the adder/subtractor/accumulator block to add or subtract the outputs of the multiplier block, which is useful for applications such as fft functions and complex fir filters. a clrn dq ena clrn dq ena data a data b data out overflow shiftout b shiftout a shiftin a shiftin b aclr clock ena signa (1) signb (1) clrn dq ena clrn dq ena accumulator addnsub (2) signa (2) signb (2) accum_sload (2) 2?68 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block single dsp block can implement tw o sums or differences from two 18 18-bit multipliers each or four s ums or differences from two 9 9-bit multipliers each. you can use the two-multipliers adder mode for complex multiplications, which are written as: (a + jb) (c + jd) = [(a c) ? (b d)] + j [(a d) + (b c)] the two-multipliers adder mode allows a single dsp block to calculate the real part [(a c) ? (b d)] using one subtractor and the imaginary part [(a d) + (b c)] using one adder, fo r data widths up to 18 bits. two complex multiplications are possible for data widths up to 9 bits using four adder/subtractor/accumulator blocks. figure 2?38 shows an 18-bit two-multipliers adder. figure 2?38. two-multipliers adder m ode implementing complex multiply four-multipliers adder mode in the four-multipliers adder mode, th e dsp block adds the results of two first -stage adder/subtractor bl ocks. one sum of four 18 18-bit multipliers or two different sums of tw o sets of four 9 9-bit multipliers can be implemented in a single dsp block. the product width for each multiplier must be the same size. th e four-multipliers adder mode is useful for fir filter applications. figure 2?39 shows the four multipliers adder mode. subtractor 36 36 18 18 18 37 a 18 (a c) ? (b d) (real part) adder 36 36 18 18 37 a 18 18 18 (a d) + (b c) (imaginary part) 18 18 18 dsp block c b d d b c altera corporation 2?69 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?39. four-multipliers adder mode notes to figure 2?39 : (1) these signals are not registered or regist ered once to match the data path pipeline. (2) these signals are not registered, regi stered once, or registered twice for la tency to match the data path pipeline. clrn dq ena data a data b shiftin a shiftin b aclr clock ena si g na (1) si g nb (1) clrn dq ena clrn dq ena clrn dq ena data a data b clrn dq ena clrn dq ena adder/subtractor clrn dq ena data a data b clrn dq ena clrn dq ena clrn dq ena data a data b shiftout b shiftout a clrn dq ena clrn dq ena adder/subtractor addnsub1 ( 2 ) si g na ( 2 ) si g nb ( 2 ) clrn dq ena data ou t addnsub3 ( 2 ) summation 2?70 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block for fir filters, the dsp block combines the four-multipliers adder mode with the shift register inputs. one set of shift inputs contains the filter data, while the other holds the coefficients loaded in serial or parallel. the input shift register eliminates the need for shift registers external to the dsp block (i.e., implemented in les). th is architecture simplifies filter design since the dsp block implemen ts all of the filter circuitry. one dsp block can implement an entire 18-bit fir filter with up to four taps. for fir filters larger than four taps, dsp blocks can be cascaded with additional adder stages implemented in les. table 2?16 shows the different number of multipliers possible in each dsp block mode according to size. these modes allow the dsp blocks to implement numerous applications for dsp including ffts, complex fir, fir, and 2d fir filters, equalizers, iir, correlators, matrix multiplication and many other functions. dsp block interface stratix device dsp block outputs can cascade down within the same dsp block column. dedicated connections between dsp blocks provide fast connections between the shift register inputs to cascade the shift register chains. you can cascade dsp blocks for 9 9- or 18 18-bit fir filters larger than four taps, with additional adder stages implemented in les. if the dsp block is configured as 36 36 bits, the adder, subtractor, or accumulator stages are implemented in les. each dsp block can route the shift register chain out of the bloc k to cascade two full columns of dsp blocks. table 2?16. multiplier size & c onfigurations per dsp block dsp block mode 9 9 18 18 36 36 (1) multiplier eight multipliers with eight product outputs four multipliers with four product outputs one multiplier with one product output multiply-accumulator two multiply and accumulate (52 bits) two multiply and accumulate (52 bits) ? two-multipliers adder four sums of two multiplier products each two sums of two multiplier products each ? four-multipliers adder two sums of four multiplier products each one sum of four multiplier products each ? note to table 2?16 : (1) the number of supported multiply functions shown is based on signed/sig ned or unsigned/unsigned implementations. altera corporation 2?71 july 2005 stratix device handbook, volume 1 stratix architecture the dsp block is divided into eight bl ock units that interface with eight lab rows on the left and right. each block unit can be considered half of an 18 18-bit multiplier sub-block with 18 inputs and 18 outputs. a local interconnect region is associated with each dsp block. like an lab, this interconnect region can be fed with 10 direct link interconnects from the lab to the left or right of the dsp block in the same row. all row and column routing resources can access the dsp block?s local interconnect region. the outputs also work sim ilarly to lab outputs as well. nine outputs from the dsp block can drive to the left lab through direct link interconnects and nine can drive to the right lab though direct link interconnects. all 18 outputs can drive to all types of row and column routing. outputs can drive right- or left-column routing. figures 2?40 and 2?41 show the dsp block interfaces to lab rows. figure 2?40. dsp block interconnect interface a1[17..0] b1[17..0] a2[17..0] b2[17..0] a3[17..0] b3[17..0] a4[17..0] b4[17..0] oa[17..0] ob[17..0] oc[17..0] od[17..0] oe[17..0] of[17..0] og[17..0] oh[17..0] dsp b lo c k m ul t it rac k in terc onn ec t m ul t it rac k in terc onn ect 2?72 altera corporation stratix device handbook, volume 1 july 2005 digital signal processing block figure 2?41. dsp block interface to interconnect a bus of 18 control signals feeds the entire dsp block. these signals include clock[0..3] clocks, aclr[0..3] asynchronous clears, ena[1..4] clock enables, signa , signb signed/unsigned control signals, addnsub1 and addnsub3 addition and subtraction control signals, and accum_sload[0..1] accumulator synchronous loads. the lab lab row interface block dsp block row structure 10 [17..0] [17..0] dsp b lo c k t o la b r ow in terface b lo c k in terc onn ect reg ion 1 8 in p u ts per r ow 1 8 o u tp u ts per r ow r 4 a n d r8 in terc onn ects c 4 a n d c8 in terc onn ects d i rect link in terc onn ect fr o m a djace n t la b nin e d i rect link o u tp u ts t o a djace n t la bs d i rect link in terc onn ect fr o m a djace n t la b 18 18 18 control 3 9 9 10 altera corporation 2?73 july 2005 stratix device handbook, volume 1 stratix architecture clock signals are routed from lab row clocks and are generated from specific lab rows at the dsp block interface. the lab row source for control signals, data inputs, and outputs is shown in table 2?17 . plls & clock networks stratix devices provide a hierarchical clock structure and multiple plls with advanced features. the large number of clocking resources in combination with the clock synthesi s precision provid ed by enhanced and fast plls provides a comple te clock management solution. global & hierarchical clocking stratix devices provide 16 dedicated global clock networks, 16 regional clock networks (four per device quadrant), and 8 dedicated fast regional clock networks (for ep1s10, ep 1s20, and ep1s25 devices), and 16 dedicated fast regional clock networks (for ep1s30 ep1s40, and ep1s60, and ep1s80 devices). th ese clocks are organized into a hierarchical clock structure that allo ws for up to 22 clocks per device region with low skew and delay. this hierarchical clocking scheme provides up to 48 unique clock domains within stratix devices. table 2?17. dsp block signal sources & destinations lab row at interface control signals generated data inputs data outputs 1 signa a1[17..0] oa[17..0] 2 aclr0 accum_sload0 b1[17..0] ob[17..0] 3 addnsub1 clock0 ena0 a2[17..0] oc[17..0] 4 aclr1 clock1 ena1 b2[17..0] od[17..0] 5 aclr2 clock2 ena2 a3[17..0] oe[17..0] 6 sign_b clock3 ena3 b3[17..0] of[17..0] 7 clear3 accum_sload1 a4[17..0] og[17..0] 8 addnsub3 b4[17..0] oh[17..0] 2?74 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks there are 16 dedicated clock pins ( clk[15..0] ) to drive either the global or regional clock networks . four clock pins drive each side of the device, as shown in figure 2?42 . enhanced and fast pll outputs can also drive the global and region al clock networks. global clock network these clocks drive throughout the entire device, feeding all device quadrants. the global clock networks can be used as clock sources for all resources within the device?ioes, les, dsp blocks, and all memory blocks. these resources can also be used for control signals, such as clock enables and synchronous or asynchrono us clears fed from the external pin. the global clock networks can al so be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. figure 2?42 shows the 16 dedicated clk pins driving global clock networks. altera corporation 2?75 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?42. global clocking note (1) note to figure 2?42 : (1) the corner fast plls can also be driv en through the global or regional clock networks. the global or regional clock in put to the fast pll can be driven by an output from another pll, a pin-driven gl obal or regional clock, or internally- generated global signals. regional clock network there are four regional clock networks within each quadrant of the stratix device that are driven by the same dedicated clk[15..0] input pins or from pll outputs. from a top view of the silicon, rclk[0..3] are in the top left quadrant, rclk[8..11] are in the top-right quadrant, rclk[4..7] are in the bottom-left quadrant, and rclk[12..15] are in the bottom-right quadrant. the region al clock networks only pertain to the quadrant they drive into. the re gional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant. rclk cannot be driven by internal logic. the clk clock pins symmetrically drive the rclk networks within a particular quadrant, as shown in figure 2?43 . see figures 2?50 and 2?51 for rclk connections from plls and clk pins. global clock [15..0] clk[15..12] clk[3..0] clk[7..4] clk[11..8] global clock [15..0] 2?76 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks figure 2?43. regional clocks fast regional clock network in ep1s25, ep1s20, and ep 1s10 devices, there are two fast regional clock networks, fclk[1..0] , within each quadrant, fed by input pins that can connect to fast regional clock networks (see figure 2?44 ). in ep1s30 and larger devices, there are two fast re gional clock networks within each half-quadrant (see figure 2?45 ). dual-purpose fclk pins drive the fast clock networks. all devices have eight fclk pins to drive fast regional clock networks. any i/o pin can drive a clock or control signal onto any fast regional clock network with the ad dition of a delay. this signal is driven via the i/o interconnect. the fa st regional clock networks can also be driven from internal logic elements. rc lk[1..0] rc lk[4.. 5 ] rc lk[ 6 ..7] rc lk[1 2 ..13] rc lk[ 2 ..3] rc lk[11..10] rc lk[14..1 5 ] rc lk[9.. 8 ] clk[15..12] clk[3..0] clk[7..4] clk[11..8] reg ion a l c lo c k s o nly dr iv e a de vi ce qu adra n t fr o m spec i f i ed c lk p in s o r p ll s wi t hin t h at qu adra n t altera corporation 2?77 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?44. ep1s25, ep1s20 & ep1s10 devi ce fast clock pi n connections to fast regional clocks notes to figure 2?44 : (1) this is a set of two multiplexers. (2) in addition to the fclk pin inputs, there is also an input from the i/o interconnect. fclk[1..0] fclk[1..0] fclk[1..0] fclk[1..0] fclk[1..0] fclk[7..6] fclk[5..4] fclk[3..2] 22 22 22 22 (1), (2) (1), (2) (1), (2) (1), (2) 2?78 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks figure 2?45. ep1s30 device fast regiona l clock pin connections to fast regional clocks notes to figure 2?45 : (1) this is a set of two multiplexers. (2) in addition to the fclk pin inputs, there is also an input from the i/o interconnect. combined resources within each region, there are 22 dist inct dedicated clocking resources consisting of 16 global clock lines, fo ur regional clock lines, and two fast regional clock lines. multiplexers are used with these clocks to form eight bit busses to drive lab row clocks, co lumn ioe clocks, or row ioe clocks. another multiplexer is used at the lab level to select two of the eight row clocks to feed the le regi sters within the lab. see figure 2?46 . fclk[1..0] fclk4 fclk5 fclk2 fclk3 fclk6 fclk7 fclk0 fclk1 (1), (2) (1), (2) (1), (2) (1), (2) (1), (2) (1), (2) (1), (2) (1), (2) altera corporation 2?79 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?46. regional clock bus ioe clocks have horizontal and vertical block regi ons that are clocked by eight i/o clock signals chosen from the 22 quadrant or half-quadrant clock resources. figures 2?47 and 2?48 show the quadrant and half- quadrant relationship to the i/o cloc k regions, respectively. the vertical regions (column pins) have less cloc k delay than the horizontal regions (row pins). clock [21..0] vertical i/o cell io_clk[7..0] lab row clock [7..0] horizontal i/o cell io_clk[7..0] global clock network [15..0] fast re g ional clock network [1..0] re g ional clock network [3..0] c lo c k s av a il ab l e t o a qu adra n t o r h a l f -qu adra n t 2?80 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks figure 2?47. ep1s10, ep1s20 & ep1s 25 device i/o clock groups io_clkc[7..0] io_clkf[7..0] io_clke[7..0] io_clka[7..0] io_clkb[7..0] io_clkd[7..0] io_clkh[7..0] io_clkg[7..0] 8 8 22 clocks in the quadrant 22 clocks in the quadrant 22 clocks in the quadrant 22 clocks in the quadrant 8 8 8 8 8 8 i/o clock region s altera corporation 2?81 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?48. ep1s30, ep1s40, ep1s60, ep1s80 device i/o clock groups you can use the quartus ii software to control whether a clock input pin is either global, regional, or fast regional. the quartus ii software automatically selects the clocking resources if not specified. enhanced & fast plls stratix devices provide robust clock management and synthesis using up to four enhanced plls and eight fast plls. these plls increase performance and provid e advanced clock interfacing and clock- frequency synthesis. with features such as clock switchover, spread spectrum clocking, programmable band width, phase and delay control, and pll reconfiguration, the stratix device?s enhanced plls provide you with complete control of your clocks and system timing. the fast plls io_clkj[7: 0 ] io_clki[7: 0 ] io_clka[7: 0 ] io_clkb[7: 0 ] 8 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 22 clocks in the half-quadrant 8 8 8 i/o clock region s io_clkl[7: 0 ] io_clkk[7: 0 ] io_clkc[7: 0 ] io_clkd[7: 0 ] 888 8 8 8 8 8 8 8 8 8 io_clke[7: 0 ] io_clkf[7: 0 ] io_clkg[7: 0 ] io_clkh[7: 0 ] io_clkn[7: 0 ] io_clkm[7: 0 ] io_clkp[7: 0 ] io_clko[7: 0 ] 2?82 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for hi gh-speed differential i/o support. enhanced and fast plls work togeth er with the stratix high-speed i/o and advanced clock architecture to pr ovide significant improvements in system performance and bandwidth. the quartus ii software enables the plls and their fe atures without requiring any external devices. table 2?18 shows the plls available for each stratix device. table 2?18. stratix device pll availability device fast plls enhanced plls 1234 7 8 9105 (1) 6 (1) 11 (2) 12 (2) ep1s10 vvvv vv ep1s20 vvvv vv ep1s25 vvvv vv ep1s30 vvvv v (3) v (3) v (3) v (3) vv ep1s40 vvvv v (3) v (3) v (3) v (3) vvv (3) v (3) ep1s60 vvvvv v v v vvvv ep1s80 vvvvv v v v vvvv notes to table 2?18 : (1) plls 5 and 6 each have eight single-e nded outputs or four differential outputs. (2) plls 11 and 12 each have one single-ended output. (3) ep1s30 and ep1s40 devices do not support these plls in the 780-pin fineline bga ? package. altera corporation 2?83 july 2005 stratix device handbook, volume 1 stratix architecture table 2?19 shows the enhanced pll and fast pll features in stratix devices. table 2?19. stratix pll features feature enhanced pll fast pll clock multiplication and division m /( n post-scale counter) (1) m /(post-scale counter) (2) phase shift down to 156.25-ps increments (3) , (4) down to 125-ps increments (3) , (4) delay shift 250-ps increments for 3 ns clock switchover v pll reconfiguration v programmable bandwidth v spread spectrum clocking v programmable duty cycle vv number of internal clock outputs 6 3 (5) number of external clock outputs f our differential/eight singled-ended or one single-ended (6) (7) number of feedback clock inputs 2 (8) notes to table 2?19 : (1) for enhanced plls, m, n , range from 1 to 512 and post-scale counters g, l, e range from 1 to 1024 with 50% duty cycle. with a non-50% duty cycle the post-scale counters g, l, e range from 1 to 512. (2) for fast plls, m and post-scale counters range from 1 to 32. (3) the smallest phase shif t is determined by the voltage controlle d oscillator (vco) period divided by 8. (4) for degree increments, stratix devices can shift a ll output frequencies in in crements of at least 45 . smaller degree increments are possible depending on the frequency and divide parameters. (5) plls 7, 8, 9, and 10 have two output ports per pll. plls 1, 2, 3, and 4 have three output ports per pll. (6) every stratix device has two enhanced plls (plls 5 and 6) with either eight sing le-ended outputs or four differential outputs each. two additional enhanced plls (plls 11 and 12) in ep1s80, ep1s60, and ep1s40 devices each have one single-ended output. devices in the 780 p in fineline bga packages do not support plls 11 and 12. (7) fast plls can drive to any i/o pin as an external clock. for high-speed differential i/o pins, the device uses a data channel to generate txclkout . (8) every stratix device has two enhanced plls with one sing le-ended or differential ex ternal feedback input per pll. 2?84 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks figure 2?49 shows a top-level diagram of the stratix device and pll floorplan. figure 2?49. pll locations fpll7clk fpll10cl k fpll9clk clk[8..11] fpll8clk clk[3..0] 7 1 2 8 10 4 3 9 11 5 12 6 clk [ 7..4 ] clk[15..12] p ll s altera corporation 2?85 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?50 shows the global and regional clocking from the pll outputs and the clk pins. figure 2?50. global & regional clock connections fr om side pins & fast pll outputs note (1) , (2) notes to figure 2?50 : (1) plls 1 to 4 and 7 to 10 are fast plls. plls 5, 6, 11, and 12 are enhanced plls. (2) the global or regional clocks in a fast pll?s quadrant can drive the fast pll input. a pin or other pll must drive the global or regional source. the source cannot be driven by internally generated logic before driving the fast pll. figure 2?51 shows the global and regional clocking from enhanced pll outputs and top clk pins. 2 clk0 clk1 clk2 clk3 g0 fpll7clk g1 g2 g3 rclk0 rclk1 rclk4 rclk5 g10 g11 g8 g9 rclk9 rclk8 rclk15 rclk14 g lo ba l c lo c k s reg ion a l c lo c k s pll 7 l 0 l 1 g 0 pll 1 pll 2 fpll8clk pll 8 2 clk10 clk11 clk8 clk9 fpll10cl k pll 10 pll 4 pll 3 fpll9clk pll 9 reg ion a l c lo c k s l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 2?86 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks figure 2?51. global & regional cl ock connections from top cloc k pins & enhanced pll outputs note (1) notes to figure 2?51 : (1) plls 1 to 4 and 7 to 10 are fast plls. plls 5, 6, 11, and 12 are enhanced plls. (2) clk4 , clk6 , clk12 , and clk14 feed the corresponding pll?s inclk0 port. (3) clk5 , clk7 , clk13 , and clk15 feed the corresponding pll?s inclk1 port. (4) the ep1s40 device in the 780-pin fineline bga package does not support plls 11 and 12. g12 g13 g14 g15 rclk10 rclk11 rclk2 rclk3 g7 g6 g5 g4 rclk13 rclk12 rclk7 rclk6 pll 12 l0 l1 g0 g1 g2 g3 clk7 clk6 clk5 clk4 pll 6 g0 g1 g2 g3 l0 l1 pll 11 l0 l1 g0 g1 g2 g3 clk13 clk12 clk14 clk15 pll 5 g0 g1 g2 g3 l0 l1 e[0..3] pll12_out pll6_ou t[3..0] pll11_out pll5_out[3..0] pll5_fb pll6_fb g lo ba l c lo c k s reg ion a l c lo c k s reg ion a l c lo c k s (1) ( 2 ) (1) ( 2 ) ( 2 ) ( 2 ) (1) (1) altera corporation 2?87 july 2005 stratix device handbook, volume 1 stratix architecture enhanced plls stratix devices contain up to four enhanced plls with advanced clock management features. figure 2?52 shows a diagram of the enhanced pll. figure 2?52. stratix enhanced pll notes to figure 2?52 : (1) external feedback is available in plls 5 and 6. (2) this single-ended external output is available from the g 0 counter for plls 11 and 12. (3) these four counters and external outputs are available in plls 5 and 6. (4) this connection is only available on ep1s40 and larger st ratix devices. for example, plls 5 and 11 are adjacent and plls 6 and 12 are adjacent. the ep1s40 device in the 780-pin fineline bga package does not support plls 11 and 12. /n char g e pump vco / g 0 / g 1 / g 2 /e0 8 4 g lo ba l c lo c k s /e1 /e2 i/ o b u ffers (3) /e3 t t t t t t t t lock detect to i/o buffers or g eneral routin g inclk0 inclk1 fbin pfd / g 3 /l1 /l0 from adjacent pll /m spread spectrum i/o buffers ( 2 ) (1) loop filter & filter pr o grammab l e ti me de l a y on e ac h p ll p o rt p o st - sca l e c oun ters clock switch-over circuitry p h ase f re qu e n c y detect o r v co p h ase se l ect ion se l ectab l e at e ac h p ll o u tp u t p o rt v co p h ase se l ect ion a ffect in g all o u tp u ts t t t t reg ion a l c lo c k s 4 2?88 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks clock multiplication & division each stratix device enhanced pll provides clock synthesis for pll output ports using m /( n post-scale counter) scaling factors. the input clock is divided by a pre-scale divider, n , and is then multiplied by the m feedback factor. the control loop drives the vco to match f in ( m / n ). each output port has a unique post-scale counter that divides down the high-frequency vco. for multiple pll outputs with different frequencies, the vco is set to the least common multiple of the output frequencies that meets its frequency specifications. then, the post-scale dividers scale down the output frequency for each output port. for example, if output frequencies required from one pll are 33 and 66 mhz, set the vco to 330 mhz (the least comm on multiple in the vco?s range). there is one pre-scale counter, n , and one multiply counter, m , per pll, with a range of 1 to 512 on each. there are two post-scale counters ( l ) for regional clock output po rts, four counters ( g ) for global clock output ports, and up to four counters ( e ) for external clock outputs, all ranging from 1 to 1024 with a 50% duty cycle setting. the post-scale counters range from 1 to 512 with any non-50% duty cycle setting. the quartus ii software automatically chooses the a ppropriate scaling factors according to the input frequency, multiplication, and division values entered. clock switchover to effectively develop high-reliability network systems, clocking schemes must support multiple clocks to provide redundancy. for this reason, stratix device enhanced plls support a flexible clock switchover capability. figure 2?53 shows a block diagram of the switchover circuit.the switchover circuit is co nfigurable, so you can define how to implement it. clock-sense circuitry automatically switches from the primary to secondary clock for pll reference when the primary clock signal is not present. altera corporation 2?89 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?53. clock switchover circuitry there are two possible ways to use the clock switchover feature. use automatic switchover circuitry for switching between inputs of the same frequency. for example, in applications that require a redundant clock with the same freq uency as the primary clock, the switchover state machine generates a signal that controls the multiplexer select in put on the bottom of figure 2?53 . in this case, the secondary clock becomes the reference clock for the pll. use the clkswitch input for user- or system-controlled switch conditions. this is possible for same-frequency switchover or to switch between inputs of different frequencies. for example, if inclk0 is 66 mhz and inclk1 is 100 mhz, you must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies with a frequency difference of more than 20%. th is feature is us eful when clock sources can originate from multi ple cards on the backplane, requiring a system-controlled swit chover between frequencies of operation. you can use clkswitch together with the lock signal to trigger the switch from a clock that is running but becomes unstable and cannot be locked onto. n counter clkloss inclk0 inclk1 clk1_bad clk0_bad clkswitch pfd fbclk clock sense smclksw enhanced pll active clock switch-over state machine t muxout 2?90 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks during switchover, the pll vco cont inues to run and will either slow down or speed up, generating freque ncy drift on the pll outputs. the clock switchover transiti ons without any glitches. after the switch, there is a finite resynchronization period to lock onto new clock as the vco ramps up. the exact amount of time it takes for the pll to relock relates to the pll configuration and ma y be adjusted by using the programmable bandwidth feature of th e pll. the specification for the maximum time to relock is 100 s. f for more information on clock switchover, see an 313, implementing clock switchover in stra tix & stratix gx devices . pll reconfiguration the pll reconfiguration feature enables system logic to change stratix device enhanced pll counters and delay elements without reloading a programmer object file ( .pof ). this provides considerable flexibility for frequency synthesis, allowing real-t ime pll frequency and output clock delay variation. you can sweep the pll output frequencies and clock delay in prototype environments. th e pll reconfiguration feature can also dynamically or intelligently control system clock speeds or t co delays in end systems. clock delay elements at each pll outp ut port implement variable delay. figure 2?54 shows a diagram of the overall dynamic pll control feature for the counters and the clock delay elements. the config uration time is less than 20 s for the enhanced pll using a input shift clock rate of 22 mhz. the charge pump, loop filt er components, and phase shifting using vco phase taps cannot be dynamically adjusted. altera corporation 2?91 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?54. dynamically program mable counters & delays in stratix device enhanced plls pll reconfiguration data is shifted into serial registers from the logic array or external devices. the pll input shift data uses a reference input shift clock. once the last bit of the se rial chain is clocked in, the register chain is synchronously loaded into the pll configuration bits. the shift circuitry also provides an asynchronous clear for the serial registers. f for more information on pll reconfiguration, see an 282: implementing pll reconfiguration in stratix & stratix gx devices. programmable bandwidth you have advanced control of the pll bandwidth using the programmable control of the pll loop characteristics, including loop filter and charge pump. the pll?s band width is a measure of its ability to track the input clock and jitter. a high-bandwidth pll can quickly lock onto a reference clock and react to any changes in th e clock. it also will allow a wide band of input jitter spectrum to pass to the output. a low- bandwidth pll will take longer to lock, but it will attenuate all high- frequency jitter components. the quartus ii software can adjust pll characteristics to achieve the de sired bandwidth. the programmable n t t m g t l t e t pfd vco char g e pump loop filter f ref scandata scanclk scanaclr c oun ters a n d c lo c k de l a y sett in gs are pr o grammab l e all o u tp u t c oun ters a n d c lo c k de l a y sett in gs ca n be pr o grammed d yn am i ca lly 2?92 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks bandwidth is tuned by varying the ch arge pump current, loop filter resistor value, high frequency capacitor value, and m counter value. you can manually adjust these values if desired. bandwidth is programmable from 200 khz to 1.5 mhz. external clock outputs enhanced plls 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). differential sstl and hstl outputs are implemented using 2 single-e nded output buffers which are programmed to have opposite polarity . in quartus ii software, simply assign the appropriate differential i/o standard and the software will implement the inversion. see figure 2?55 . altera corporation 2?93 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?55. external clock outputs for plls 5 & 6 notes to figure 2?55 : (1) the design can use each external clock output pin as a general-purpose output pin from the logic array. these pins are multiplexed with ioe outputs. (2) two single-ended outputs ar e possible per output counter ? either two outputs of the same frequency and phase or one shifted 180 . (3) ep1s10, ep1s20, and ep1s25 devices in 672-pin bga and 484- and 672-pin fineline bga packages only have two pairs of external clocks (i.e., pll_out0p , pll_out0n , pll_out1p , and pll_out1n ). (4) differential sstl and hstl outputs are implemente d using two single-ended ou tput buffers, which are programmed to have opposite polarity. e 0 counter pll_out0p (3) , (4 ) pll_out0n (3) , (4 ) pll_out1p (3) , (4 ) pll_out1n (3) , (4 ) pll_out2p (3) , (4 ) pll_out2n (3) , (4 ) pll_out3p (3) , (4 ) pll_out3n (3) , (4 ) e 1 counter e 2 counter e 3 counter from ioe (1) , ( 2 ) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) 4 (3) 2?94 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks any of the four external output coun ters can drive the single-ended or differential clock outputs for plls 5 and 6. this means one counter or frequency can drive all output pins available from pll 5 or pll 6. each pair of output pins (four pins total) has dedicated vcc and gnd pins to reduce the output clock?s overall ji tter by providing im proved isolation from switching i/o pins. for plls 5 and 6, each pi n of a single-ended output pair can either be in phase or 180 out of phase. the clock output pin pairs support the same i/o standards as standard output pins (in the top and bottom banks) as well as lvds, lvpecl, 3.3-v pcml, hypertransport technology, differential hstl, and differential sstl. table 2?20 shows which i/o standards the enhanced pll clock pins support. when in single-ended or differential mode, the two outputs operate off the same power supply. both outputs use the same standards in single-ended mode to maintain performance. you can also use the ex ternal clock output pins as user output pins if external enhanc ed pll clocking is not needed. table 2?20. i/o standards supported for enhanced pll pins (part 1 of 2) i/o standard input output inclk fbin pllenable extclk lv t t l vv v v lv c m o s vv v v 2.5 v vv v 1.8 v vv v 1.5 v vv v 3.3-v pci vv v 3.3-v pci-x 1.0 vv v lvpecl vv v 3.3-v pcml vv v lv d s vv v hypertransport technology vv v differential hstl vv differential sstl v 3.3-v gtl vv v 3.3-v gtl+ vv v 1.5-v hstl class i vv v altera corporation 2?95 july 2005 stratix device handbook, volume 1 stratix architecture enhanced plls 11 and 12 support one single-ended output each (see figure 2?56 ). these outputs do not have their own vcc and gnd signals. therefore, to minimize jitter, do not place switching i/o pins next to this output pin. figure 2?56. external clock outputs for enhanced plls 11 & 12 note to figure 2?56 : (1) for pll 11, this pin is clk13n ; for pll 12 this pin is clk7n . stratix devices can drive any enhanc ed pll driven through the global clock or regional clock network to an y general i/o pin as an external output clock. the jitter on the output clock is not guaranteed for these cases. 1.5-v hstl class ii vv v 1.8-v hstl class i vv v 1.8-v hstl class ii vv v sstl-18 class i vv v sstl-18 class ii vv v sstl-2 class i vv v sstl-2 class ii vv v sstl-3 class i vv v sstl-3 class ii vv v agp (1 and 2 ) vv v ctt vv v table 2?20. i/o standards supported for enhanced pll pins (part 2 of 2) i/o standard input output inclk fbin pllenable extclk clk13n, i/o, pll11_out or clk6n, i/o, pll12_out (1 ) from internal logic or ioe g 0 counter 2?96 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks clock feedback the following four feedback modes in stratix device enhanced plls allow multiplication and/or phase and delay shifting: zero delay buffer: the external cl ock output pin is phase-aligned with the clock input pin for zero de lay. altera recommends using the same i/o standard on the input clock and the output clocks for optimum performance. external feedback: the exte rnal feedback input pin, fbin , is phase- aligned with the clock input, clk , pin. aligning these clocks allows you to remove clock delay and skew between devices. this mode is only possible for plls 5 and 6. pl ls 5 and 6 each support feedback for one of the dedicated external ou tputs, either one single-ended or one differential pair. in this mode, one e counter feeds back to the pll fbin input, becoming part of the f eedback loop. altera recommends using the same i/o standard on the input clock, the fbin pin, and the output clocks fo r optimum performance. normal mode: if an internal clock is used in this mode, it is phase- aligned to the input cloc k pin. the external cl ock output pin will have a phase delay relative to the clock input pin if connected in this mode. you define which internal clock output from the pll should be phase-aligned to th e internal clock pin. no compensation: in this mode, th e pll will not compensate for any clock networks or external clock outputs. phase & delay shifting stratix device enhanced plls prov ide advanced prog rammable phase and clock delay shifting. these para meters are set in the quartus ii software. phase delay the quartus ii software automatically sets the phase taps and counter settings according to the phase shift en try. you enter a desired phase shift and the quartus ii software automa tically sets the closest setting achievable. this type of phase shift is not reconfigurable during system operation. for phase shifting, enter a phase shift (in degrees or time units) for each pll clock output port or for all outputs together in one shift. you can select phase-shifting values in time units with a resolution of 156.25 to 416.66 ps. this resolution is a fu nction of frequency input and the multiplication and division factors (tha t is, it is a function of the vco period), with the finest step being equal to an eighth (0.125) of the vco period. each clock output counter ca n choose a different phase of the altera corporation 2?97 july 2005 stratix device handbook, volume 1 stratix architecture vco period from up to eight taps for individual fine step selection. also, each clock output counter can use a unique initial count setting to achieve individual coarse shift selection in steps of one vco period. the combination of coarse and fine shifts allows phase shifting for the entire input clock period. the equation to determin e the precision of the ph ase shifting in degrees is: 45 post-scale counter value. therefore, the maximum step size is 45 , and smaller steps are possible depending on the multiplication and division ratio necessary on the output counter port. this type of phase shift provides the highest precision since it is the least sensitive to process, supply, and temperature variation. clock delay in addition to the phase shift featur e, the ability to fine tune the t clock delay provides advanced time delay sh ift control on each of the four pll outputs. there are time delays for each post-scale counter ( e , g , or l ) from the pll, the n counter, and m counter. each of these can shift in 250-ps increments for a range of 3.0 ns. the m delay shifts all outputs earlier in time, while n delay shifts all outputs later in time. individual delays on post-scale counters ( e , g , and l ) provide positive delay for each output. table 2?21 shows the combined delay for ea ch output for normal or zero delay buffer mode where t e , t g , or t l is unique for each pll output. the t output for a single output can range from ?3 ns to +6 ns. the total delay shift difference between any two pll outputs, however, must be less than 3 ns. for example, shifts on tw o outputs of ?1 and +2 ns is allowed, but not ?1 and +2.5 ns beca use these shifts would result in a difference of 3.5 ns. if the design uses external feedback, the t e delay will remove delay from outputs, repr esented by a negative sign (see table 2?21 ). this effect occurs because the t e delay is then part of the feedback loop. table 2?21. output clock delay for enhanced plls normal or zero delay buffer mode external feedback mode t e output = t n ? t m + t e t g output = t n ? t m + t g t l output = t n ? t m + t l t e output = t n ? t m ? t e (1) t g output = t n ? t m + t g t l output = t n ? t m + t l note to table 2?21 : (1) t e removes delay from outputs in external feedback mode. 2?98 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks the variation due to process, volt age, and temperature is about 15 % on the delay settings. pll reconfiguration can control the clock delay shift elements, but not the vco phase sh ift multiplexers, during system operation. spread-spectrum clocking stratix device enhanced plls use spread-spectrum technology to reduce electromagnetic interference generation from a syst em by distributing the energy over a broader frequency range. the enhanced pll typically provides 0.5% down spread modulation using a triangular profile. the modulation frequency is programmable. enabling spread-spectrum for a pll affects all of its outputs. lock detect the lock output indicates that there is a stable clock output signal in phase with the reference clock. withou t any additional ci rcuitry, the lock signal may toggle as the pll begins tr acking the reference clock. you may need to gate the lock signal for use as a system control. the lock signal from the locked port can drive the logic array or an output pin. whenever the pll loses lock (for example, inclk jitter, clock switchover, pll reconfiguration, power supply noise, and so on), the pll must be reset with the areset signal to guarantee correct phase relationship between the pll output clocks. if the phase relationship between the input clock versus output clock, and between different output clocks from the pll is not important in th e design, then the pll need not be reset. f see the stratix fpga errata sheet for more information on implementing the gated lock signal in a design. programmable duty cycle the programmable duty cycle allows enhanced plls to generate clock outputs with a variable duty cycle. this featur e is supported on each enhanced pll post-scale counter ( g 0.. g 3, l 0.. l 3, e 0.. e 3). the duty cycle setting is achieved by a low and high time count setting for the post-scale dividers. the quartus ii software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. advanced clear & enable control there are several control signals for cl earing and enabling plls and their outputs. you can use these signals to control pll resynchronization and gate pll output clocks for low-power applications. altera corporation 2?99 july 2005 stratix device handbook, volume 1 stratix architecture the pllenable pin is a dedicated pin that enables/disables plls. when the pllenable pin is low, the clock ou tput ports are driven by gnd and all the plls go out of lock. when the pllenable pin goes high again, the plls relock and resynchronize to th e input clocks. you can choose which plls are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. the areset signals are reset/re synchronization inputs for each pll. the areset signal should be asserted ev ery time the pll loses lock to guarantee correct phase relationship between the pll output clocks. users should include the areset signal in designs if any of the following conditions are true: pll reconfiguration or clock switchover enables in the design. phase relationships between output clocks need to be maintained after a loss of lock condition the device input pins or logic el ements (les) can drive these input signals. when driven high, the pll counters will reset, clearing the pll output and placing the pll out of lock. the vco will set back to its nominal setting (~700 mhz). when dr iven low again, the pll will resynchronize to its input as it relock s. if the target vco frequency is below this nominal frequency, then th e output frequency will start at a higher value than desired as the pll locks. if the system cannot tolerate this, the clkena signal can disable the output clocks until the pll locks. the pfdena signals control the phase frequency detector (pfd) output with a programmable gate. if you disa ble the pfd, the vco operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. the system continues running when the pll goes out of lock or the input clock is disabled. by maintaining the last locked frequency, the system has time to store its current settings before shutting down. you can either us e your own control signal or a clkloss status signal to trigger pfdena . the clkena signals control the enhanced pll regional and global outputs. each regional and global output port has its own clkena signal. the clkena signals synchronously disable or enable the clock at the pll output port by gating the outputs of the g and l counters. the clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. figure 2?57 shows the waveform example for a pll clock port enable. the pll can remain locked independent of the clkena signals since the loop-related counters are not affected. this feature is useful for applications that require a low power or sleep mode. upon re-enabling, the pll does not need a 2?100 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks resynchronization or relock period. the clkena signal can also disable clock outputs if the system is not to lerant to frequency overshoot during resynchronization. the extclkena signals work in the same way as the clkena signals, but they control the external clock output counters ( e 0, e 1, e 2, and e 3). upon re-enabling, the pll does not need a resynchronization or relock period unless the pll is using external feedback mode. in order to lock in external feedback mode, the external output must drive the board trace back to the fbin pin. figure 2?57. extclkena signals fast plls stratix devices contain up to eight fast plls with high-speed serial interfacing ability, along with general-purpose features. figure 2?58 shows a diagram of the fast pll. counter output clkena clkout altera corporation 2?101 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?58. stratix device fast pll notes to figure 2?58 : (1) the global or regional clock input can be driven by an output from another pll or any dedicated clk or fclk pin. it cannot be driven by intern ally-generated global signals. (2) in high-speed differential i/o support mode, this high-s peed pll clock feeds the serdes. stratix devices only support one rate of data transfer per fast p ll in high-speed differential i/o support mode. (3) this signal is a high-speed differential i/o support serdes control signal. clock multiplication & division stratix device fast plls provide clock synthesis for pll output ports using m /(post scaler) scaling factors. the input clock is multiplied by the m feedback factor. each output port has a unique post scale counter to divide down the high-frequency vco. there is one multiply divider, m , per fast pll with a range of 1 to 32. there are two post scale l dividers for regional and/or lvds interface clocks, and g 0 counter for global clock output port; all range from 1 to 32. in the case of a high-speed differential interface, set the output counter to 1 to allow the high-speed vco frequency to drive the serdes. when used for clocking the serdes, the m counter can range from 1 to 30. the vco frequency is equal to f in m, where vco frequency must be between 300 and 1000 mhz. char g e pump vco g 0 8 clock input pfd l 1 l 0 m loop filter p h ase f re qu e n c y detect o r v co p h ase se l ect ion se l ectab l e at eac h p ll o u tp u t p o rt p o st - sca l e c oun ters global or re g ional cloc k global or re g ional cloc k global or re g ional cloc k diffioclk2 ( 2 ) diffioclk1 ( 2 ) txload_en (3) rxload_en (3) global or re g ional clock (1) 2?102 altera corporation stratix device handbook, volume 1 july 2005 plls & clock networks external clock inputs each fast pll supports single-ended or differential inputs for source synchronous transmitters or fo r general-purpose use. source- synchronous receivers support differential clock inputs. the fast pll inputs are fed by clk[0..3] , clk[8..11] , and fpll[7..10]clk pins, as shown in figure 2?50 on page 2?85 . table 2?22 shows the i/o standards supported by fast pll input pins. table 2?22. fast pll port i/o standards (part 1 of 2) i/o standard input inclk pllenable lv t t l vv lv c m o s vv 2.5 v v 1.8 v v 1.5 v v 3.3-v pci 3.3-v pci-x 1.0 lvpecl v 3.3-v pcml v lv d s v hypertransport technology v differential hstl v differential sstl 3.3-v gtl 3.3-v gtl+ v 1.5-v hstl class i v 1.5-v hstl class ii 1.8-v hstl class i v 1.8-v hstl class ii sstl-18 class i v sstl-18 class ii sstl-2 class i v altera corporation 2?103 july 2005 stratix device handbook, volume 1 stratix architecture table 2?23 shows the performance on each of the fast pl l clock inputs when using lvds, lvpecl, 3.3-v pcml , or hypertransport technology. external clock outputs each fast pll supports differential or single-ended outputs for source- synchronous transmitters or for gene ral-purpose external clocks. there are no dedicated external clock outp ut pins. any i/o pi n can be driven by the fast pll global or regional outputs as an external output pin. the i/o standards supported by any pa rticular bank determines what standards are possible for an external clock output driven by the fast pll in that bank. phase shifting stratix device fast plls have advanced clock shift capability that enables programmable phase shifts. you can enter a phase shift (in degrees or time units) for each pll clock output port or for all outputs together in one shift. you can perform phase shifti ng in time units with a resolution range of 125 to 416.66 ps. this resolution is a function of the vco period, with the finest step being equal to an eighth (0.125) of the vco period. sstl-2 class ii v sstl-3 class i v sstl-3 class ii v agp (1 and 2 ) ctt v table 2?23. lvds performance on fast pll input fast pll clock input maxim um input frequency (mhz) clk0, clk2, clk9, clk11, fpll7clk, fpll8clk, fpll9clk, fpll10clk 717 (1) clk1, clk3, clk8, clk10 645 note to table 2?23 : (1) see the chapter dc & switching characteristics of the stratix device handbook, volume 1 for more information. table 2?22. fast pll port i/o standards (part 2 of 2) i/o standard input inclk pllenable 2?104 altera corporation stratix device handbook, volume 1 july 2005 i/o structure control signals the fast pll has the same lock output, pllenable input, and areset input control signals as the enhanced pll. if the input clock stops and causes the pll to lose lock, then the pll must be reset for correct phase shift operation. for more information on high-speed differential i/o support, see ?high- speed differential i/o support? on page 2?130 . i/o structure ioes provide many features, including: dedicated differential and single-ended i/o buffers 3.3-v, 64-bit, 66-mhz pci compliance 3.3-v, 64-bit, 133-mhz pci-x 1.0 compliance joint test action group (jtag) boundary-scan test (bst) support differential on-chip termination for lvds i/o standard programmable pull-up during configuration output drive strength control slew-rate control tri-state buffers bus-hold circuitry programmable pull-up resistors programmable input and output delays open-drain outputs dq and dqs i/o pins double-data rate (ddr) registers the ioe in stratix devices contains a bidirectional i/o buffer, six registers, and a latch for a complete embedded bidirectional single data rate or ddr transfer. figure 2?59 shows the stratix ioe structure. the ioe contains two input registers (plus a latch), two output registers, and two output enable registers. the desi gn can use both input registers and the latch to capture ddr input and both output registers to drive ddr outputs. additionally, the design can use the output enable (oe) register for fast clock-to-output enable timi ng. the negative edge-clocked oe register is used for ddr sdram interfacing. the quartus ii software automatically duplicates a single oe register that controls multiple output or bidirectional pins. altera corporation 2?105 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?59. stratix ioe structure the ioes are located in i/o blocks around the periphery of the stratix device. there are up to four ioes per row i/o block and six ioes per column i/o block. the row i/o blocks drive row, column, or direct link interconnects. the column i/o blocks drive column interconnects. figure 2?60 shows how a row i/o block connects to the logic array. figure 2?61 shows how a column i/o bloc k connects to th e logic array. dq output register output a dq output register output b input a input b dq oe register oe dq oe register dq input register dq input register dq input latch logic array clk ena 2?106 altera corporation stratix device handbook, volume 1 july 2005 i/o structure figure 2?60. row i/o block c onnection to the interconnect notes to figure 2?60 : (1) the 16 control signals are composed of four output enables io_boe[3..0] , four clock enables io_bce[3..0] , four clocks io_clk[3..0] , and four clear signals io_bclr[3..0] . (2) the 28 data and control signals consist of eight data out lines: four lines each for ddr applications io_dataouta[3..0] and io_dataoutb[3..0] , four output enables io_coe[3..0] , four input clock enables io_cce_in[3..0] , four output clock enables io_cce_out[3..0] , four clocks io_cclk[3..0] , and four clear signals io_cclr[3..0] . 16 28 r4, r8 & r24 interconnects c4, c8 & c16 interconnects i/o block local interconnect 16 control signals from i/o interconnect (1) i/o interconnect 28 data & control signals from logic array (2) io_dataouta[3..0] io_dataoutb[3..0] io_clk[7:0] horizontal i/o block contains up to four ioes direct link interconnect to adjacent lab direct link interconnect to adjacent lab lab local interconnect lab horizontal i/o block altera corporation 2?107 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?61. column i/o block connection to the interconnect notes to figure 2?61 : (1) the 16 control signals are composed of four output enables io_boe[3..0] , four clock enables io_bce[3..0] , four clocks io_bclk[3..0] , and four clear signals io_bclr[3..0] . (2) the 42 data and control signals consist of 12 data out lines; six lines each for ddr applications io_dataouta[5..0] and io_dataoutb[5..0] , six output enables io_coe[5..0] , six input clock enables io_cce_in[5..0] , six output clock enables io_cce_out[5..0] , six clocks io_cclk[5..0] , and six clear signals io_cclr[5..0] . 16 control signals from i/o interconnect (1) 42 data & control signals from logic array (2) vertical i/o block contains up to six ioes i/o block local interconnect i/o interconnec t io_datain[ 3 : 0 ] r4, r8 & r24 interconnects lab local interconnect c4, c8 & c16 interconnects 16 42 lab lab lab io_clk[7..0] vertical i/o block 2?108 altera corporation stratix device handbook, volume 1 july 2005 i/o structure stratix devices have an i/o interc onnect similar to the r4 and c4 interconnect to drive high-fanout si gnals to and from the i/o blocks. there are 16 signals that drive into the i/o bloc ks composed of four output enables io_boe[3..0] , four clock enables io_bce[3..0] , four clocks io_bclk[3..0] , and four clear signals io_bclr[3..0] . the pin?s datain signals can drive the io interconnect, which in turn drives the logic array or other i/o blocks. in addition, the control and data signals can be driven from the logic array, providing a slower but more flexible routing resource. the row or column ioe clocks, io_clk[7..0] , provide a dedicated routing resource for low-skew, high-speed clocks. i/o clocks are generated from regional, global, or fast regional clocks (see ?plls & clock networks? on page 2?73 ). figure 2?62 illustrates the signal paths through the i/o block. figure 2?62. signal path through the i/o block row or column io_clk[7..0] io_boe[3..0] io_bce[3..0] io_bclk[3..0] io_bclr[3..0] io_datain0 io_datain1 io_dataout0 io_dataout1 io_coe oe ce_in ce_out io_cce_in aclr/apreset io_cce_out sclr/spreset io_cclr clk_in io_cclk clk_out control signal selection ioe from i/o interconnect to logic array from logic array to other ioes altera corporation 2?109 july 2005 stratix device handbook, volume 1 stratix architecture each ioe contains its own control signal selection for the following control signals: oe , ce_in , ce_out , aclr/preset , sclr/preset , clk_in , and clk_out . figure 2?63 illustrates the control signal selection. figure 2?63. control signal selection per ioe in normal bidirectional operation, the input register can be used for input data requiring fast setup times. the input register can have its own clock input and clock enable separate from the oe and output registers. the output register can be used for da ta requiring fast clock-to-output performance. the oe register can be used for fast clock-to-output enable timing. the oe and output register share the same clock source and the same clock enable source from local interconnect in the associated lab, dedicated i/o clocks, and the column and row interconnects. figure 2?64 shows the ioe in bidirectional configuration. clk_out ce_in clk_in ce_out aclr/preset sclr/preset i/o interconnect [15..0] dedicated i/o clock [7..0] local interconnect local interconnect local interconnect local interconnect local interconnect oe io_coe io_cclr io_cce_out io_cce_in io_cclk io_bclk[3..0] io_bce[3..0] io_bclr[3..0] io_boe[3..0] 2?110 altera corporation stratix device handbook, volume 1 july 2005 i/o structure figure 2?64. stratix ioe in bidi rectional i/o configuration note (1) note to figure 2?64 : (1) all input signals to the io e can be inverted at the ioe. the stratix device ioe includes programmable delays that can be activated to ensure zero hold time s, input ioe register-to-logic array register transfers, or logic array-to-output ioe register transfers. a path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. programmable delays exist for decreasing input-pin-to-logic-array and ioe input register delays. the quartus ii comp iler can program these delays to automatically mini mize setup time while prov iding a zero hold time. programmable delays can increase the register-to-pin delays for output clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena output register v ccio v ccio optional pci clamp programmable pull-up resistor column or row interconnect i/o interconnect [15..0] ioe_clk[7..0] bus-hold circuit output enable clock enable delay output clock enable delay logic array to output register delay output t zx delay oe register t co delay clrn/prn dq ena input register input clock enable delay input pin to input register delay input pin to logic array delay drive strength control open-drain output slew control sclr/preset oe clkout ce_out aclr/prn clkin ce_in output pin delay altera corporation 2?111 july 2005 stratix device handbook, volume 1 stratix architecture and/or output enable registers. a programmable delay exists to increase the t zx delay to the output pin, which is required for zbt interfaces. table 2?24 shows the programmable delays for stratix devices. the ioe registers in stratix devices share the same source for clear or preset. you can program preset or clea r for each individual ioe. you can also program the registers to power up high or low after configuration is complete. if programmed to power up low, an asynchronous clear can control the registers. if programmed to power up high, an asynchronous preset can control the registers. this feature prevents the inadvertent activation of another device?s acti ve-low input upon power-up. if one register in an ioe uses a preset or clear signal then all registers in the ioe must use that same signal if they require preset or clear. additionally a synchronous reset signal is available for the ioe registers. double-data rate i/o pins stratix devices have six registers in the ioe, which support ddr interfacing by clocking data on both positive and negative clock edges. the ioes in stratix devices support ddr inputs, ddr outputs, and bidirectional ddr modes. when using the ioe for ddr inputs, th e two input registers clock double rate input data on alternating edges. an input latch is also used within the ioe for ddr input acquisition. the la tch holds the data that is present during the clock high times. this allows both bits of data to be synchronous with the same clock ed ge (either rising or falling). figure 2?65 shows an ioe configured for ddr input. figure 2?66 shows the ddr input ti ming diagram. table 2?24. stratix programmable delay chain programmable delays quartus ii logic option input pin to logic array delay decreas e input delay to internal cells input pin to input register delay de crease input delay to input register output pin delay increase delay to output pin output enable register t co delay increase delay to output enable pin output t zx delay increase t zx delay to output pin output clock enable delay increase output clock enable delay input clock enable delay increase input clock enable delay logic array to output register delay de crease input delay to output register output enable clock enable delay increase output enable clock enable delay 2?112 altera corporation stratix device handbook, volume 1 july 2005 i/o structure figure 2?65. stratix ioe in dd r input i/o configuration note (1) notes to figure 2?65 : (1) all input signals to the io e can be inverted at the ioe. (2) this signal connection is only al lowed on dedicated dq function pins. (3) this signal is for dedicated dqs function pins only. clrn/prn dq ena chip-wide reset input register clrn/prn dq ena input register vccio vccio optional pci clamp programmable pull-up resistor column or row interconnect i/o interconnect [15..0] dqs local bus (1), (2) to dqs local bus (3) ioe_clk[7..0] bus-hold circuit output clock enable delay clrn/prn dq ena latch input pin to input register delay sclr clkin aclr/prn (1) (1) altera corporation 2?113 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?66. input timing diagram in ddr mode when using the ioe for ddr output s, the two output registers are configured to clock two data paths from les on rising clock edges. these output registers are multiplexed by the clock to drive the output pin at a 2 rate. one output register clocks th e first bit out on th e clock high time, while the other output register clocks the second bit out on the clock low time. figure 2?67 shows the ioe configured for ddr output. figure 2?68 shows the ddr output timing diagram. data at input pin a' b' clk a0 b1 a1 a1 b2 a2 a3 a2 a3 b1 b2 b3 b3 b4 input to logic array 2?114 altera corporation stratix device handbook, volume 1 july 2005 i/o structure figure 2?67. stratix ioe in ddr output i/o configuration notes (1) , (2) notes to figure 2?67 : (1) all input signals to the io e can be inverted at the ioe. (2) the tristate is by default active high. it can, however, be designed to be active low. clrn/prn dq ena chip-wide reset oe register clrn/prn dq ena oe register clrn/prn dq ena output register v ccio v ccio optional pci clamp programmabl e pull-up resistor column or row interconnect i/o interconnect [15..0] ioe_clk[7..0] bus-hold circuit logic array to output register delay output t zx delay oe register t co delay clrn/prn dq ena output register logic array to output register delay drive strength control open-drain output slew control used for ddr sdram clk sclr aclr/prn clkout output pin delay output enable clock enable delay output clock enable delay altera corporation 2?115 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?68. output timing diagram in ddr mode the stratix ioe operates in bidire ctional ddr mode by combining the ddr input and ddr output configur ations. stratix device i/o pins transfer data on a ddr bidirectional bus to support ddr sdram. the negative-edge-clocked oe register hold s the oe signal inactive until the falling edge of the clock. this is done to meet ddr sdram timing requirements. external ram interfacing stratix devices support ddr sdram at up to 200 mhz (400-mbps data rate) through dedicated phase-shift circuitry, qdr and qdrii sram interfaces up to 167 mhz, and zbt sram interfaces up to 200 mhz. stratix devices also provide preliminary support for reduced latency dram ii (rldram ii) at rates up to 200 mhz through the dedicated phase-shift circuitry. 1 in addition to the required si gnals for external memory interfacing, stratix de vices offer the optional clock enable signal. by default the quartus ii software sets the clock enable signal high, which tells the output regi ster to update with new values. the output registers ho ld their own values if the design sets the clock enable signal low. see figure 2?64 . f to find out more about the ddr sd ram specification, see the jedec web site ( www.jedec.org ). for information on memory controller megafunctions for stratix device s, see the altera web site ( www.altera.com ). see an 342: interfacing ddr sdram with stratix & stratix gx devices for more information on ddr sdram interface in stratix. also see an 349: qdr sram controller reference design for stratix & stratix gx devices and an 329: zbt sram controller reference design for stratix & stratix gx devices . f r o m in ter n a l reg i sters ddr output clk a b b1 a1 b2 a2 b3 a3 a2 a1 a3 a4 b1 b2 b3 b4 2?116 altera corporation stratix device handbook, volume 1 july 2005 i/o structure tables 2?25 and 2?26 show the performance specification for ddr sdram, rldram ii, qdr sram, qdrii sram, and zbt sram interfaces in ep1s10 through ep1s 40 devices and in ep1s60 and ep1s80 devices. the ddr sdram and qdr sram numbers in table 2?25 have been verified with hardware char acterization with third-party ddr sdram and qdr sram devices over temperature and voltage extremes. table 2?25. external ram support in ep1s10 through ep1s40 devices ddr memory type i/o standard maximum clock rate (mhz) -5 speed grade -6 speed grade -7 speed grade -8 speed grade flip-chip flip-chip wire- bond flip- chip wire- bond flip- chip wire- bond ddr sdram (1) , (2) sstl-2 200 167 133 133 100 100 100 ddr sdram - side banks (2) , (3) , (4) sstl-2 150 133 110 133 100 100 100 rldram ii (4) 1.8-v hstl 200 (5) (5) (5) (5) (5) (5) qdr sram (6) 1.5-v hstl 167 167 133 133 100 100 100 qdrii sram (6) 1.5-v hstl 200 167 133 133 100 100 100 zbt sram (7) lvttl 200 200 200 167 167 133 133 notes to table 2?25 : (1) these maximum clock rates apply if the stratix device uses dqs phase-shift circuit ry to interface with ddr sdram. dqs phase-shift circuitry is only available in the top and bottom i/o banks (i/o banks 3, 4, 7, and 8). (2) for more informati on on ddr sdram, see an 342: interfacing ddr sdram wi th stratix & stratix gx devices. (3) ddr sdram is supported on the strati x device side i/o banks (i/o banks 1, 2, 5, and 6) without dedicated dqs phase-shift circuitry. the read dqs signal is ignored in this mode. (4) these performance specifications are preliminary. (5) this device does not support rldram ii. (6) for more information on qdr or qdrii sram, see an 349: q dr sram controller reference design for stratix & stratix gx devices . (7) for more informati on on zbt sram, see an 329: zbt sram controller reference design for stratix & stratix gx devices . altera corporation 2?117 july 2005 stratix device handbook, volume 1 stratix architecture in addition to six i/o registers and one input latch in the ioe for interfacing to these high-speed memory interfaces, stratix devices also have dedicated circuitry for interfacing with ddr sdram. in every stratix device, the i/o banks at the top (i/o banks 3 and 4) and bottom (i/o banks 7 and 8) of the device support ddr sdram up to 200 mhz. these pins support dqs signals with dq bus modes of 8, 16, or 32. table 2?27 shows the number of dq and dqs buses that are supported per device. table 2?26. external ram support in ep1s60 & ep1s80 devices ddr memory type i/o standard maximum clock rate (mhz) -5 speed grade -6 speed grade -7 speed grade ddr sdram (1) , (2) sstl-2 167 167 133 ddr sdram - side banks (2) , (3) sstl-2 150 133 133 qdr sram (4) 1.5-v hstl 133 133 133 qdrii sram (4) 1.5-v hstl 167 167 133 zbt sram (5) lvttl 200 200 167 notes to table 2?26 : (1) these maximum clock rates apply if the stratix device uses dqs phase-shift circuit ry to interface with ddr sdram. dqs phase-shift circuitry is only available in the top and bottom i/o banks (i/o banks 3, 4, 7, and 8). (2) for more informati on on ddr sdram, see an 342: interfacing ddr sdram wi th stratix & stratix gx devices. (3) ddr sdram is supported on the strati x device side i/o banks (i/o banks 1, 2, 5, and 6) without dedicated dqs phase-shift circuitry. the read dqs signal is ignored in this mode. numbers are preliminary. (4) for more information on qdr or qdrii sram, see an 349: q dr sram controller reference design for stratix & stratix gx devices . (5) for more informati on on zbt sram, see an 329: zbt sram controller reference design for stratix & stratix gx devices . table 2?27. dqs & dq bus mode support (part 1 of 2) note (1) device package number of 8 groups number of 16 groups number of 32 groups ep1s10 672-pin bga 672-pin fineline bga 12 (2) 00 484-pin fineline bga 780-pin fineline bga 16 (3) 04 ep1s20 484-pin fineline bga 18 (4) 7 (5) 4 672-pin bga 672-pin fineline bga 16 (3) 7 (5) 4 780-pin fineline bga 20 7 (5) 4 2?118 altera corporation stratix device handbook, volume 1 july 2005 i/o structure a compensated delay element on ea ch dqs pin automatically aligns input dqs synchronization signals with the data window of their corresponding dq data signals. the dqs signals drive a local dqs bus in the top and bottom i/o banks. this dq s bus is an additional resource to the i/o clocks and is used to cloc k dq input registers with the dqs signal. two separate single phase-shifting reference circuits are located on the top and bottom of the stratix device. each circuit is driven by a system reference clock through the clk pins that is the same frequency as the dqs signal. clock pins clk[15..12]p feed the phase-shift circuitry on the top of the device and clock pins clk[7..4]p feed the phase-shift circuitry on the bottom of the device . the phase-shifting reference circuit on the top of the device controls th e compensated delay elements for all 10 dqs pins located at the top of the device. the phase-shifting reference circuit on the bottom of the device controls the compensated delay elements for all 10 dqs pins locate d on the bottom of the device. all 10 delay elements (dqs signals) on ei ther the top or bottom of the device ep1s25 672-pin bga 672-pin fineline bga 16 (3) 84 780-pin fineline bga 1,020-pin fineline bga 20 8 4 ep1s30 956-pin bga 780-pin fineline bga 1,020-pin fineline bga 20 8 4 ep1s40 956-pin bga 1,020-pin fineline bga 1,508-pin fineline bga 20 8 4 ep1s60 956-pin bga 1,020-pin fineline bga 1,508-pin fineline bga 20 8 4 ep1s80 956-pin bga 1,508-pin fineline bga 1,923-pin fineline bga 20 8 4 notes to table 2?27 : (1) see the selectable i/o standards in stratix & stratix gx devices chapter in the stratix device handbook, volume 2 for v ref guidelines. (2) these packages have six groups in i/o banks 3 and 4 and six groups in i/o banks 7 and 8. (3) these packages have eight grou ps in i/o banks 3 and 4 and eigh t groups in i/o banks 7 and 8. (4) this package has nine groups in i/o banks 3 and 4 and nine groups in i/o banks 7 and 8. (5) these packages have three groups in i/o banks 3 and 4 and four groups in i/o banks 7 and 8. table 2?27. dqs & dq bus mode support (part 2 of 2) note (1) device package number of 8 groups number of 16 groups number of 32 groups altera corporation 2?119 july 2005 stratix device handbook, volume 1 stratix architecture shift by the same degree amount. for example, all 10 dqs pins on the top of the device can be shifted by 90 an d all 10 dqs pins on the bottom of the device can be shifted by 72. the reference circuits require a maximum of 256 system reference clock cycles to set the correct phase on the dqs delay elements. figure 2?69 illustrates the phase-shift reference circuit control of each dqs delay shift on the top of the device. this same circuit is duplicated on the bottom of the device. figure 2?69. simplified diagram of the dqs phase-shift circuitry see the external memory interfaces chapter in the stratix device handbook , volume 2 for more information on ex ternal memory interfaces. programmable drive strength the output buffer for each stratix device i/o pin has a programmable drive strength control for certain i/o standards. the lvttl and lvcmos standard has several levels of drive strength that the user can control. sstl-3 class i and ii, sstl-2 class i and ii, hstl class i and ii, and 3.3-v gtl+ support a minimum setting, the lowest drive strength that guarantees the i oh /i ol of the standard. using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. phase comparator up/down counter delay chains input reference clock control signals to dqs pins 6 2?120 altera corporation stratix device handbook, volume 1 july 2005 i/o structure table 2?28 shows the possible settings fo r the i/o standards with drive strength control. quartus ii software version 4.2 and la ter will report current strength as ?pci compliant? for 3.3-v pci, 3. 3-v pci-x 1.0, and compact pci i/o standards. stratix devices support series on-chip termination (oct) using programmable drive strength. for more information, contact your altera support representative. open-drain output stratix devices provide an optional open-drain (equivalent to an open- collector) output for each i/o pin. this open-drain output enables the device to provide system-level control signals (e.g., interrupt and write- enable signals) that can be asse rted by any of several devices. slew-rate control the output buffer for each stratix device i/o pin has a programmable output slew-rate control that can be configured for low-noise or high- speed performance. a faster slew rate provides high-speed transitions for high-performance systems. howeve r, these fast transitions may introduce noise transien ts into the system. a slow slew rate reduces system noise, but adds a nominal delay to rising and falling edges. each table 2?28. programmable drive strength i/o standard i oh / i ol current strength setting (ma) 3.3-v lvttl 24 (1) , 16, 12, 8, 4 3.3-v lvcmos 24 (2) , 12 (1) , 8, 4, 2 2.5-v lvttl/lvcmos 16 (1) , 12, 8, 2 1.8-v lvttl/lvcmos 12 (1) , 8, 2 1.5-v lvcmos 8 (1) , 4, 2 gtl/gtl+ 1.5-v hstl class i and ii 1.8-v hstl class i and ii sstl-3 class i and ii sstl-2 class i and ii sstl-18 class i and ii support max and min strength notes to ta b l e 2 ? 2 8 : (1) this is the quartus ii soft ware default current setting. (2) i/o banks 1, 2, 5, and 6 do not support this setting. altera corporation 2?121 july 2005 stratix device handbook, volume 1 stratix architecture i/o pin has an individual slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis. the slew-rate control affects both the rising and falling edges. bus hold each stratix device i/o pin provides an optional bus-hold feature. the bus-hold circuitry can weakly hold the signal on an i/o pin at its last- driven state. since the bus-hold feature holds the last-driven state of the pin until the next input si gnal is present, an exte rnal pull-up or pull-down resistor is not needed to hold a sign al level when the bus is tri-stated. table 2?29 shows bus hold support for different pin types. the bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. you can select this featur e individually for each i/o pin. the bus-hold output drives no higher than v ccio to prevent overdriving signals. if the bus-hold feature is enabled, the programmable pull-up option cannot be used. disable the bus-hold feature when using open- drain outputs with the gtl+ i/o standard or when the i/o pin has been configured for differential signals. the bus-hold circuitry uses a resistor with a nominal resistance (r bh ) of approximately 7 k to weakly pull the signal level to the last-driven state. see the dc & switching characteristics chapter of the stratix device handbook, volume 1 for the specific sustaining current driven through this resistor and overdrive current used to identify the next-driven input level. this information is provided for each v ccio voltage level. the bus-hold circuitry is active only after configuration. when going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. table 2?29. bus hold support pin type bus hold i/o pins v clk[15..0] clk[0,1,2,3,8,9,10,11] fclk v fpll[7..10]clk 2?122 altera corporation stratix device handbook, volume 1 july 2005 i/o structure programmable pull-up resistor each stratix device i/o pin provides an optional programmable pull-up resistor during user mode. if this feature is enabled for an i/o pin, the pull-up resistor (typically 25 k ) weakly holds the output to the v ccio level of the output pin?s bank. table 2?30 shows which pin types support the weak pull-up resistor feature. advanced i/o standard support stratix device ioes support the following i/o standards: lvttl lvcmos 1.5 v 1.8 v 2.5 v 3.3-v pci 3.3-v pci-x 1.0 3.3-v agp (1 and 2) lvds lvpecl 3.3-v pcml hypertransport differential hstl (on input/output clocks only) differential sstl (on output column clock pins only) gtl/gtl+ 1.5-v hstl class i and ii table 2?30. programmable weak pull-up resistor support pin type programmable w eak pull-up resistor i/o pins v clk[15..0] fclk v fpll[7..10]clk configuration pins jtag pins v (1) note to table 2?30 : (1) tdo pins do not support programmable weak pull-up resistors. altera corporation 2?123 july 2005 stratix device handbook, volume 1 stratix architecture 1.8-v hstl class i and ii sstl-3 class i and ii sstl-2 class i and ii sstl-18 class i and ii ctt table 2?31 describes the i/o standards supported by stratix devices. table 2?31. stratix supported i/o standards i/o standard type input reference voltage (v ref ) (v) output supply voltage (v ccio ) (v) board termination voltage (v tt ) (v) lvttl single-ended n/a 3.3 n/a lvcmos single-ended n/a 3.3 n/a 2.5 v single-ended n/a 2.5 n/a 1.8 v single-ended n/a 1.8 n/a 1.5 v single-ended n/a 1.5 n/a 3.3-v pci single-ended n/a 3.3 n/a 3.3-v pci-x 1.0 single-ended n/a 3.3 n/a lvds differential n/a 3.3 n/a lvpecl differential n/a 3.3 n/a 3.3-v pcml differential n/a 3.3 n/a hypertransport differential n/a 2.5 n/a differential hstl (1) differential 0.75 1.5 0.75 differential sstl (2) differential 1.25 2.5 1.25 gtl voltage-referenced 0.8 n/a 1.20 gtl+ voltage-referenced 1.0 n/a 1.5 1.5-v hstl class i and ii voltage-referenced 0.75 1.5 0.75 1.8-v hstl class i and ii voltage-referenced 0.9 1.8 0.9 sstl-18 class i and ii voltage-referenced 0.90 1.8 0.90 sstl-2 class i and ii voltage-referenced 1.25 2.5 1.25 sstl-3 class i and ii voltage-referenced 1.5 3.3 1.5 agp (1 and 2 ) voltage-referenced 1.32 3.3 n/a ctt voltage-referenced 1.5 3.3 1.5 notes to table 2?31 : (1) this i/o standard is only availa ble on input and output clock pins. (2) this i/o standard is only avai lable on output column clock pins. 2?124 altera corporation stratix device handbook, volume 1 july 2005 i/o structure f for more information on i/o standard s supported by stratix devices, see the selectable i/o standards in stratix & stratix gx devices chapter of the stratix device handbook, volume 2 . stratix devices contain eight i/o banks in addition to the four enhanced pll external clock out banks, as shown in figure 2?70 . the four i/o banks on the right and left of the de vice contain circui try to support high- speed differential i/o for lvds, lvpecl, 3.3-v pcml, and hypertransport inputs and output s. these banks support all i/o standards listed in table 2?31 except pci i/o pins or pci-x 1.0, gtl, sstl-18 class ii, and hstl class ii outputs. the top and bottom i/o banks support all single-ended i/o standards. additionally, stratix devices support four enhanced pll external clock output banks, allowing clock output capabilities su ch as differential support for sstl and hstl. table 2?32 shows i/o standard support for each i/o bank. altera corporation 2?125 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?70. strati x i/o banks notes (1) , (2) , (3) notes to figure 2?70 : (1) figure 2?70 is a top view of the silicon die. this will correspond to a top-down view for non-flip-chip packages, but will be a reverse view for flip-chip packages. (2) figure 2?70 is a graphic representation only. se e the device pin-outs on the web ( www.altera.com ) and the quartus ii software for exact locations. (3) banks 9 through 12 are enhanced pll external clock output banks. (4) if the high-speed differential i/o pins are not used for high-speed differential signaling, they can support all of the i/o standards except hs tl class i and ii, gtl, sstl-18 cl ass ii, pci, pci-x 1.0, and agp 1 /2 . (5) for guidelines for placing single-ended i/o pads next to differential i/o pads, see the selectable i/o standards in stratix and stratix gx devices chapter in the stratix device handbook, volume 2 . lv ds, lv p e c l , 3.3-v pcm l , a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) lv ds, lv p e c l , 3.3-v pcm l , a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) i/ o ba nk s 3 , 4 , 9 & 10 s u pp o rt all s in g l e -en ded i/ o sta n dards i/ o ba nk s 7 , 8, 11 & 1 2 s u pp o rt all s in g l e -en ded i/ o sta n dards i/ o ba nk s 1 , 2, 5, a n d 6 s u pp o rt all s in g l e -en ded i/ o sta n dards ex cept d i ffere n t i a l h s tl o u tp u t c lo c k s, d i ffere n t i a l ss tl- 2 o u tp u t c lo c k s, h s tl c l ass ii , g tl , ss tl-1 8 c l ass ii , pc i , pc i-x 1.0 , a n d a gp 1 / 2 dqs9t dqs8t dqs7t dqs6t dqs5t dqs4t dqs3t dqs2t dqs1t dqs0t pll5 vref1b3 vref2b3 vref3b3 vref4b3 vref5b3 vref1b4 vref2b4 vref3b4 vref4b4 vref5b4 vref5b8 vref4b8 vref3b8 vref2b8 vref1b8 vref5b7 vref4b7 vref3b7 vref2b7 vref1b7 pll6 dqs9b dqs8b dqs7b dqs6b dqs5b dqs4b dqs3b dqs2b dqs1b dqs0b 910 vref1b2 vref2b2 vref3b2 vref4b2 vref1b1 vref2b1 vref3b1 vref4b1 vref4b6 vref3b6 vref2b6 vref1b6 vref4b5 vref3b5 vref2b5 vref1b5 bank 5 bank 6 pll3 pll4 pll1 pll2 bank 1 bank 2 bank 3 bank 4 11 12 bank 8 bank 7 lv ds, lv p e c l , 3.3-v pcm l , a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) lv ds, lv p e c l , 3.3-v pcm l , a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) pll7 pll10 pll8 pll9 pll12 pll11 ( 5 ) ( 5 ) ( 5 ) ( 5 ) 2?126 altera corporation stratix device handbook, volume 1 july 2005 i/o structure table 2?32 shows i/o standard support for each i/o bank. table 2?32. i/o support by bank (part 1 of 2) i/o standard top & bottom banks (3, 4, 7 & 8) left & right banks (1, 2, 5 & 6) enhanced pll external clock output banks (9, 10, 11 & 12) lv t t l vvv lv c m o s vvv 2.5 v vvv 1.8 v vvv 1.5 v vvv 3.3-v pci vv 3.3-v pci-x 1.0 vv lvpecl vv 3.3-v pcml vv lv d s vv hypertransport technology vv differential hstl (clock inputs) vv differential hstl (clock outputs) v differential sstl (clock outputs) v 3.3-v gtl vv 3.3-v gtl+ vvv 1.5-v hstl class i vvv 1.5-v hstl class ii vv 1.8-v hstl class i vvv 1.8-v hstl class ii vv sstl-18 class i vvv sstl-18 class ii vv sstl-2 class i vvv sstl-2 class ii vvv sstl-3 class i vvv altera corporation 2?127 july 2005 stratix device handbook, volume 1 stratix architecture each i/o bank has its own vccio pins. a single device can support 1.5-, 1.8-, 2.5-, and 3.3-v interfaces; each bank can support a different standard independently. each ba nk also has dedicated vref pins to support any one of the voltage-referenced standa rds (such as sstl-3) independently. each i/o bank can support multiple standards with the same v ccio for input and output pins. each bank can support one voltage-referenced i/o standard. for example, when v ccio is 3.3 v, a bank can support lvttl, lvcmos, 3.3-v pci, and sstl-3 for inputs and outputs. differential on-chip termination stratix devices provide differenti al on-chip termination (lvds i/o standard) to reduce reflections and main tain signal integrity. differential on-chip termination simplifies board design by minimizing the number of external termination resistors re quired. termination can be placed inside the package, eliminating sm all stubs that can still lead to reflections. the internal termination is designed using transistors in the linear region of operation. stratix devices support internal diff erential termination with a nominal resistance value of 137.5 for lvds input receiver buffers. lvpecl signals require an external termination resistor. figure 2?71 shows the device with differential termination. sstl-3 class ii vvv agp (1 and 2 ) vv ctt vvv table 2?32. i/o support by bank (part 2 of 2) i/o standard top & bottom banks (3, 4, 7 & 8) left & right banks (1, 2, 5 & 6) enhanced pll external clock output banks (9, 10, 11 & 12) 2?128 altera corporation stratix device handbook, volume 1 july 2005 i/o structure figure 2?71. lvds input differ ential on-chip termination i/o banks on the left and right side of the device support lvds receiver (far-end) differential termination. table 2?33 shows the stratix device differential termination support. table 2?34 shows the termination support for different pin types. the differential on-chip resistance at the receiver input buffer is 118 20 %. r d + e + e transmittin g device receivin g device with differential termination z 0 z 0 table 2?33. differential terminat ion supported by i/o banks differential termination support i/o standard support top & bottom banks (3, 4, 7 & 8) left & right banks (1,2,5 & 6) differential termination (1) , (2) lv d s v notes to table 2?33 : (1) clock pin clk0 , clk2 , clk9 , clk11 , and pins fpll[7..10]clk do not support differential termination. (2) differential termination is only su pported for lvds because of a 3.3-v v ccio . table 2?34. differential termination support across pin types pin type r d top and bottom i/o banks (3, 4, 7, and 8) diffio_rx[] v clk[0,2,9,11],clk[4-7],clk[12-15] clk[1,3,8,10] v fclk fpll[7..10]clk altera corporation 2?129 july 2005 stratix device handbook, volume 1 stratix architecture however, there is additional resistan ce present between the device ball and the input of the receiver buffer, as shown in figure 2?72 . this resistance is because of package trace resistance (which can be calculated as the resistance from the package ball to the pad) and the parasitic layout metal routing resistance (which is shown between the pad and the intersection of the on-chip termination and input buffer). figure 2?72. differential resistance of lvds differential pin pair ( r d ) table 2?35 defines the specification for internal termination resistance for commercial devices. multivolt i/o interface the stratix architecture supports th e multivolt i/o interface feature, which allows stratix devices in all pa ckages to interface with systems of different supply voltages. the stratix vccint pins must always be co nnected to a 1.5-v power supply. with a 1.5-v v ccint level, input pins are 1.5-v, 1.8-v, 2.5-v, and 3.3-v tolerant. the vccio pins can be connected to either a 1.5-v, 1.8-v, 2.5-v, or 3.3-v power supply, depe nding on the output requirements. lvds input buffer differential on-chip termination resisto r 9.3 9.3 0.3 0.3 r d pad package ball table 2?35. differential on-chip termination symbol description conditions resistance unit min typ max r d (2) internal differential termination for lvds commercial (1) , (3) 110 135 165 w industrial (2) , (3) 100 135 170 w notes to table 2?35 : (1) data measured over minimum conditions (t j = 0 c, v ccio +5%) and maximum conditions (t j = 85 c, v ccio =?5%). (2) data measured over minimum conditions (t j = ?40 c, v ccio +5%) and maximum conditions (t j = 100 c, v ccio =?5%). (3) lvds data rate is supported for 840 mbps using internal differential termination. 2?130 altera corporation stratix device handbook, volume 1 july 2005 high-speed differential i/o support the output levels are compatible with systems of the same voltage as the power supply (i.e., when vccio pins are connected to a 1.5-v power supply, the output levels are comp atible with 1.5-v systems). when vccio pins are connected to a 3.3-v po wer supply, the output high is 3.3 v and is compatible with 3.3-v or 5.0-v systems. table 2?36 summarizes stratix multivolt i/o support. high-speed differential i/o support stratix devices contain dedicated circuitry for supporting differential standards at speeds up to 840 mbps. the following differential i/o standards are supported in the stratix device: lvds, lvpecl, hypertransport, and 3.3-v pcml. there are four dedicated high-spe ed plls in the ep1s10 to ep1s25 devices and eight dedicated high-speed plls in the ep1s30 to ep1s80 devices to multiply reference clocks and drive high-speed differential serdes channels. f see the stratix device pin-outs at www.altera.com for additional high speed diffio pin informat ion for stratix devices. table 2?36. stratix mu ltivolt i/o support note (1) v ccio (v) input signal (5) output signal (6) 1.5 v1.8 v2.5 v3.3 v5.0 v1.5 v1.8 v2.5 v3.3 v5.0 v 1.5 vv v (2) v (2) v 1.8 v (2) v v (2) v (2) v (3) v 2.5 vv v (3) v (3) v 3.3 v (2) v v (4) v (3) v (3) v (3) vv notes to table 2?36 : (1) to drive inputs higher than v ccio but less than 4.1 v, disable the pci clamping diode. however, to drive 5.0-v inputs to the device, enable the pci clamping diode to prevent v i from rising above 4.0 v. (2) the input pin current may be slightly higher than the typical value. (3) although v ccio specifies the voltage necessary for the stratix devi ce to drive out, a receiving device powered at a different level can still interface with the strati x device if it has inputs that tolerate the v ccio value. (4) stratix devices can be 5.0-v tolerant with the use of an external resistor and the internal pci clamp diode. (5) this is the external signal th at is driving the stratix device. (6) this represents the system voltage th at stratix supports when a vccio pin is connected to a specific voltage level. for example, when vccio is 3.3 v and if the i/o standa rd is lvttl/lvcmos, the ou tput high of the signal coming out from stratix is 3.3 v and is compatible with 3.3-v or 5.0-v systems. altera corporation 2?131 july 2005 stratix device handbook, volume 1 stratix architecture table 2?37 shows the number of channels that each fast pll can clock in ep1s10, ep1s20, and ep1s25 devices. tables 2?38 through table 2?41 show this information for ep1s30, ep1s40, ep1s60, an d ep1s80 devices. table 2?37. ep1s10, ep1s20 & ep1s25 device differential channels (part 1 of 2) note (1) device package transmitter/ receiver total channels maximum speed (mbps) center fast plls pll 1 pll 2 pll 3 pll 4 ep1s10 484-pin fineline bga transmitter (2) 20 840 (4) 5555 840 (3) 10 10 10 10 receiver 20 840 (4) 5555 840 (3) 10 10 10 10 672-pin fineline bga 672-pin bga transmitter (2) 36 624 (4) 9999 624 (3) 18 18 18 18 receiver 36 624 (4) 9999 624 (3) 18 18 18 18 780-pin fineline bga transmitter (2) 44 840 (4) 11 11 11 11 840 (3) 22 22 22 22 receiver 44 840 (4) 11 11 11 11 840 (3) 22 22 22 22 ep1s20 484-pin fineline bga transmitter (2) 24 840 (4) 6666 840 (3) 12 12 12 12 receiver 20 840 (4) 5555 840 (3) 10 10 10 10 672-pin fineline bga 672-pin bga transmitter (2) 48 624 (4) 12 12 12 12 624 (3) 24 24 24 24 receiver 50 624 (4) 13 12 12 13 624 (3) 25 25 25 25 780-pin fineline bga transmitter (2) 66 840 (4) 17 16 16 17 840 (3) 33 33 33 33 receiver 66 840 (4) 17 16 16 17 840 (3) 33 33 33 33 2?132 altera corporation stratix device handbook, volume 1 july 2005 high-speed differential i/o support when you span two i/o banks using cross-bank support, you can route only two load enable signals total between the plls. when you enable rx_data_align , you use both rxloadena and txloadena of a pll. that leaves no loadena for the second pll. ep1s25 672-pin fineline bga 672-pin bga transmitter (2) 56 624 (4) 14 14 14 14 624 (3) 28 28 28 28 receiver 58 624 (4) 14 15 15 14 624 (3) 29 29 29 29 780-pin fineline bga transmitter (2) 70 840 (4) 18 17 17 18 840 (3) 35 35 35 35 receiver 66 840 (4) 17 16 16 17 840 (3) 33 33 33 33 1,020-pin fineline bga transmitter (2) 78 840 (4) 19 20 20 19 840 (3) 39 39 39 39 receiver 78 840 (4) 19 20 20 19 840 (3) 39 39 39 39 notes to table 2?37 : (1) the first row for each transmitter or receiver reports the number of channels driven directly by the pll. the second row below it shows the maximum channels a pll can drive if cross bank channels are us ed from the adjacent center pll. for example, in the 484-pin fineline bga ep1s10 device, pll 1 can drive a maximum of five channels at 840 mbps or a maximum of 10 channels at 840 mbps. th e quartus ii software may also merge receiver and transmitter plls when a receiver is dri ving a transmitter. in this case, on e fast pll can drive both the maximum numbers of receiver and transmitter channels. (2) the number of channels listed in cludes the transmitter clock output ( tx_outclock ) channel. if the design requires a ddr clock, it can use an extra data channel. (3) these channels span across two i/o banks per side of the device. when a center pll clocks channels in the opposite bank on the same side of the device it is called cro ss-bank pll support. both center plls can clock cross-bank channels simultaneously if, for example, pll_1 is clocking all receiver channels and pll_2 is clocking all transmitter channels. you cannot have two adjacent plls simultaneously clocki ng cross-bank receiver channels or two adjacent plls simultaneously cloc king transmitter channels. cross-bank allows for all receiver channels on one side of the device to be clocked on one clock while all transmitter channe ls on the device are clocked on the other center pll. crossbank plls are supported at full-spee d, 840 mbps. for wire-bond devices, the full-speed is 624 mbps. (4) these values show the channels available for each pll without crossing another bank. table 2?37. ep1s10, ep1s20 & ep1s25 device differential channels (part 2 of 2) note (1) device package transmitter/ receiver total channels maximum speed (mbps) center fast plls pll 1 pll 2 pll 3 pll 4 altera corporation 2?133 july 2005 stratix device handbook, volume 1 stratix architecture the only way you can use the rx_data_align is if one of the following is true: the receiver pll is only clocking receive channels (no resources for the transmitter) if all channels can fit in one i/o bank table 2?38. ep1s30 differential channels note (1) package transmitter /receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 780-pin fineline bga transmitter (4) 70 840 18 17 17 18 (6) (6) (6) (6) 840 (5) 35 35 35 35 (6) (6) (6) (6) receiver 66 840 17 16 16 17 (6) (6) (6) (6) 840 (5) 33 33 33 33 (6) (6) (6) (6) 956-pin bga transmitter (4) 80 840 19 20 20 19 20 20 20 20 840 (5) 39 39 39 39 20 20 20 20 receiver 80 840 20 20 20 20 19 20 20 19 840 (5) 40 40 40 40 19 20 20 19 1,020-pin fineline bga transmitter (4) 80 (2) (7) 840 19 (1) 20 20 19 (1) 20 20 20 20 840 (5) , (8) 39 (1) 39 (1) 39 (1) 39 (1) 20 20 20 20 receiver 80 (2) (7) 840 20 20 20 20 19 (1) 20 20 19 (1) 840 (5) , (8) 40 40 40 40 19 (1) 20 20 19 (1) table 2?39. ep1s40 differential channels (part 1 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 780-pin fineline bga transmitter (4) 68 840 18 16 16 18 (6) (6) (6) (6) 840 (5) 34 34 34 34 (6) (6) (6) (6) receiver 66 840 17 16 16 17 (6) (6) (6) (6) 840 (5) 33 33 33 33 (6) (6) (6) (6) 2?134 altera corporation stratix device handbook, volume 1 july 2005 high-speed differential i/o support 956-pin bga transmitter (4) 80 840 18 17 17 18 20 20 20 20 840 (5) 35 35 35 35 20 20 20 20 receiver 80 840 20 20 20 20 18 17 17 18 840 (5) 40 40 40 40 18 17 17 18 1,020-pin fineline bga transmitter (4) 80 (10) (7) 840 18 (2) 17 (3) 17 (3) 18 (2) 20 20 20 20 840 (5) , (8) 35 (5) 35 (5) 35 (5) 35 (5) 20 20 20 20 receiver 80 (10) (7) 840 20 20 20 20 18 (2) 17 (3) 17 (3) 18 (2) 840 (5) , (8) 40 40 40 40 18 (2) 17 (3) 17 (3) 18 (2) 1,508-pin fineline bga transmitter (4) 80 (10) (7) 840 18 (2) 17 (3) 17 (3) 18 (2) 20 20 20 20 840 (5) , (8) 35 (5) 35 (5) 35 (5) 35 (5) 20 20 20 20 receiver 80 (10) (7) 840 20 20 20 20 18 (2) 17 (3) 17 (3) 18 (2) 840 (5) , (8) 40 40 40 40 18 (2) 17 (3) 17 (3) 18 (2) table 2?40. ep1s60 differential channels (part 1 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 956-pin bga transmitter (4) 80 840 12 10 10 12 20 20 20 20 840 (5) , (8) 22 22 22 22 20 20 20 20 receiver 80 840 20 20 20 20 12 10 10 12 840 (5) , (8) 40 40 40 40 12 10 10 12 table 2?39. ep1s40 differential channels (part 2 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 altera corporation 2?135 july 2005 stratix device handbook, volume 1 stratix architecture 1,020-pin fineline bga transmitter (4) 80 (12) (7) 840 12 (2) 10 (4) 10 (4) 12 (2) 20 20 20 20 840 (5) , (8) 22 (6) 22 (6) 22 (6) 22 (6) 20 20 20 20 receiver 80 (10) (7) 840 20 20 20 20 12 (8) 10 (10) 10 (10) 12 (8) 840 (5) , (8) 40 40 40 40 12 (8) 10 (10) 10 (10) 12 (8) 1,508-pin fineline bga transmitter (4) 80 (36) (7) 840 12 (8) 10 (10) 10 (10) 12 (8) 20 20 20 20 840 (5) , (8) 22 (18) 22 (18) 22 (18) 22 (18) 20 20 20 20 receiver 80 (36) (7) 840 20 20 20 20 12 (8) 10 (10) 10 (10) 12 (8) 840 (5) , (8) 40 40 40 40 12 (8) 10 (10) 10 (10) 12 (8) table 2?41. ep1s80 differential channels (part 1 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 956-pin bga transmitter (4) 80 (40) (7) 840 10 10 10 10 20 20 20 20 840 (5) , (8) 20 20 20 20 20 20 20 20 receiver 80 840 20 20 20 20 10 10 10 10 840 (5) , (8) 40 40 40 40 10 10 10 10 1,020-pin fineline bga transmitter (4) 92 (12) (7) 840 10 (2) 10 (4) 10 (4) 10 (2) 20 20 20 20 840 (5) , (8) 20 (6) 20 (6) 20 (6) 20 (6) 20 20 20 20 receiver 90 (10) (7) 840 20 20 20 20 10 (2) 10 (3) 10 (3) 10 (2) 840 (5) , (8) 40 40 40 40 10 (2) 10 (3) 10 (3) 10 (2) table 2?40. ep1s60 differential channels (part 2 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 2?136 altera corporation stratix device handbook, volume 1 july 2005 high-speed differential i/o support the high-speed differential i/o ci rcuitry supports the following high speed i/o interconnect standards and applications: utopia iv spi-4 phase 2 (pos-phy level 4) sfi-4 10g ethernet xsbi 1,508-pin fineline bga transmitter (4) 80 (72) (7) 840 10 (10) 10 (10) 10 (10) 10 (10) 20 (8) 20 (8) 20 (8) 20 (8) 840 (5) , (8) 20 (20) 20 (20) 20 (20) 20 (20) 20 (8) 20 (8) 20 (8) 20 (8) receiver 80 (56) (7) 840 20 20 20 20 10 (14) 10 (14) 10 (14) 10 (14) 840 (5) , (8) 40 40 40 40 10 (14) 10 (14) 10 (14) 10 (14) notes to tables 2?38 through 2?41 : (1) the first row for each transmitter or receiver reports the number of channels driven directly by the pll. the second row below it shows the maximum channels a pll can drive if cross bank channels are used from the adjacent center pll. for example, in the 780-pin fineline bga ep1s 30 device, pll 1 can drive a maximum of 18 transmitter channels at 840 mbps or a maximum of 35 transmitter channels at 840 mbps. the quartus ii software may also merge transmitter and receiver plls wh en a receiver is driving a transmitter. in this case, on e fast pll can drive both the maximum numbers of rece iver and trans mitter channels. (2) some of the channels accessible by the center fast pll an d the channels accessible by th e corner fast pll overlap. therefore, the total number of channels is not the addition of the n umber of channels accessible by plls 1, 2, 3, and 4 with the number of channels accessible by plls 7, 8, 9, and 10. for more information on which channels overlap, see the stratix device pin-outs at www.altera.com . (3) the corner fast plls in this device support a data rate of 840 mbps for channels labeled ?high? speed in the device pin-outs at www.altera.com . (4) the numbers of channels listed in clude the transmitter clock output ( tx_outclock ) channel. an extra data channel can be used if a ddr clock is needed. (5) these channels span across two i/o banks per side of the device. when a center pll clocks channels in the opposite bank on the same side of the device it is called cro ss-bank pll support. both center plls can clock cross-bank channels simultaneously if say pll_1 is clocking all receiver channels and pll_2 is clocking all transmitter channels. you cannot have two adjacent plls simultaneously clocking cross-bank receiver channels or two adjacent plls simultaneously clocking transmitte r channels. cross-bank allows for all re ceiver channels on one side of the device to be clocked on one clock while all transmitter chan nels on the device are clocked on the other center pll. crossbank plls are supported at full-speed, 840 mbps . for wire-bond devices, the full-speed is 624 mbps. (6) plls 7, 8, 9, and 10 are not available in this device. (7) the number in parentheses is the n umber of slow-speed channels, guaranteed to operate at up to 462 mbps. these channels are independent of the high-sp eed differential channels. for the location of these channels, see the device pin-outs at www.altera.com . (8) see the stratix device pin-outs at www.altera.com . channels marked ?high? spee d are 840 mbps and ?low? speed channels are 462 mbps. table 2?41. ep1s80 differential channels (part 2 of 2) note (1) package transmitter/ receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 altera corporation 2?137 july 2005 stratix device handbook, volume 1 stratix architecture rapidio hypertransport dedicated circuitry stratix devices support source-synchronous interfacing with lvds, lvpecl, 3.3-v pcml, or hypertrans port signaling at up to 840 mbps. stratix devices can transmit or receive serial channels along with a low-speed or high-speed clock. the receiving device pll multiplies the clock by a integer factor w (w = 1 through 32). for example, a hypertransport applicat ion where the data rate is 800 mbps and the clock rate is 400 mhz would require that w be set to 2. the serdes factor j determines the parallel data width to deserialize from receivers or to serialize for transmitters. the serdes fa ctor j can be set to 4, 7, 8, or 10 and does not have to equal the pll clock-multiplication w value. for a j factor of 1, the stratix device bypasses the serdes block. for a j factor of 2, the stratix device bypasses the serdes block, and the ddr input and output registers are used in the ioe. see figure 2?73 . figure 2?73. high-speed differential i/o rece iver / transmitter interface example an external pin or global or regional clock can drive the fast plls, which can output up to three clocks: two mu ltiplied high-speed differential i/o clocks to drive the serdes block and/or external pin, and a low-speed clock to drive the logic array. + ? 8 data data fast pll 105 mhz 8 840 mbps ded i cated rece iv er in terface ded i cated t ra n sm i tter in terface r 4 , r8, a n d r2 4 in terc onn ect lo ca l in terc onn ect 8 + ? 8 840 mbps tx_load_en rx_load_en re g ional or g lobal cloc k 8 2?138 altera corporation stratix device handbook, volume 1 july 2005 high-speed differential i/o support the quartus ii megawizard ? plug-in manager only allows the implementation of up to 20 receiver or 20 transmitter channels for each fast pll. these channels operate at up to 840 mbps. the receiver and transmitter channels are in terleaved such that each i/o bank on the left and right side of the device has one receiver channel and one transmitter channel per lab row. figure 2?74 shows the fast pll and channel layout in ep1s10, ep1s20, and ep1s25 devices. figure 2?75 shows the fast pll and channel layout in th e ep1s30 to ep1s80 devices. figure 2?74. fast pll & channel layout in the ep1s10, ep1s20 or ep1s25 devices note (1) notes to figure 2?74 : (1) wire-bond packages support up to 624 mbps. (2) see table 2?41 for the number of channels each device supports. (3) there is a multiplexer here to select the pll clock source. if a pll uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 mbps for ?high? speed channels and 462 mbps for ?low? speed channels, as labele d in the device pin-outs at www.altera.com . transmitter receiver transmitter receiver clkin clkin transmitter receiver transmitter receiver clkin clkin fast pll 1 fast pll 2 ( 3 ) fast pll 4 fast pll 3 ( 3 ) up to 2 0 receiver and transmitter channels (2) up to 2 0 receiver and transmitter channels (2) up to 2 0 receiver and transmitter channels (2) up to 2 0 receiver and transmitter channels (2) altera corporation 2?139 july 2005 stratix device handbook, volume 1 stratix architecture figure 2?75. fast pll & channel layout in the ep1s30 to ep1s80 devices note (1) notes to figure 2?75 : (1) wire-bond packages support up to 624 mbps. (2) see table 2?38 through 2?41 for the number of channe ls each device supports. (3) there is a multiplexer here to select the pll clock source. if a pll uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 mbps for ?high? speed channels and 462 mbps for ?low? speed channels as labeled in the device pin-outs at www.altera.com . transmitter receiver transmitter receiver clkin fpll7clk transmitter receiver transmitter receiver clkin fpll10clk transmitter receiver transmitter receiver fpll9clk clkin fast pll 7 fast pll 1 up to 20 receiver and 20 transmitter channels in 20 rows (2) transmitter receiver transmitter receiver fpll8clk clkin fast pll 2 fast pll 8 up to 20 receiver and 20 transmitter channels in 20 rows (2) up to 20 receiver and 20 transmitter channels in 20 rows (2) up to 20 receiver and 20 transmitter channels in 20 rows (2) (3) (3) fast pll 10 fast pll 4 fast pll 3 fast pll 9 2?140 altera corporation stratix device handbook, volume 1 july 2005 power sequencing & hot socketing the transmitter external clock output is transmitted on a data channel. the txclk pin for each bank is located in between data transmitter pins. for 1 clocks (e.g., 622 mbps, 622 mhz), the high-speed pll clock bypasses the serdes to drive the output pins. for half-rate clocks (e.g., 622 mbps, 311 mhz) or any other even-n umbered factor such as 1/4, 1/7, 1/8, or 1/10, the serdes automatic ally generates the clock in the quartus ii software. for systems that require more than fo ur or eight high-speed differential i/o clock domains, a serdes bypass implementation is possible using ioes. byte alignment for high-speed source synchronous interfaces such as pos-phy 4, xsbi, rapidio, and hypertransport technology, the source synchronous clock rate is not a byte- or serdes-rate multiple of the data rate. byte alignment is necessary for these protocols since the source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate, not one eighth. the stratix device?s high-speed differential i/o circuitry provides dedicated data realignment circuitry for user- controlled byte boundary shifting. this simplifies designs while saving le resources. an input signal to ea ch fast pll can stall deserializer parallel data outputs by one bit pe riod. you can use an le-based state machine to signal the shift of receiv er byte boundaries until a specified pattern is detected to in dicate byte alignment. power sequencing & hot socketing because stratix devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. therefore, the vccio and vccint power supplies may be powered in any order. although you can power up or down the vccio and vccint power supplies in any sequence, you shou ld not power down any i/o banks that contain configuration pins wh ile leaving other i/o banks powered on. for power up and power down, all supplies ( vccint and all vccio power planes) must be powered up and down within 100 ms of each other. this prevents i /o pins from driving out. signals can be driven into stratix devices before and during power up without damaging the device. in addi tion, stratix devices do not drive out during power up. once operating conditions are reached and the device is configured, stratix devices operate as specified by the user. for more information, see hot socketing in the selectable i/o standards in stratix & stratix gx devices chapter in the stratix device handbook, volume 2 . altera corporation 3?1 july 2005 3. configuration & testing ieee std. 1149.1 (jtag) boundary-scan support all stratix ? devices provide jtag bst circuitry that complies with the ieee std. 1149.1a-1990 spec ification. jtag boundary-scan testing can be performed either before or after, bu t not during configuration. stratix devices can also use the jtag port fo r configuration together with either the quartus ? ii software or hardware using either jam files ( .jam ) or jam byte-code files ( .jbc ). stratix devices support ioe i/o standard setting reconfiguration through the jtag bst chain. the jtag chain can update the i/o standard for all input and output pins any time before or during user mode through the config_io instruction. you can use this ability for jtag testing before configuration when some of the stratix pins drive or receive from other devices on the board using voltage-referenced standards. since the stratix device may not be configured before jtag testing, the i/o pins may not be configured for appropriate elec trical standards for chip-to-chip communication. programming those i/o standards via jtag allows you to fully test the i/o conn ection to other devices. the enhanced pll reconfig uration bits are part of the jtag chain before configuration and after power-up. after device configuration, the pll reconfiguration bits are not part of the jtag chain. the jtag pins support 1.5-v/1.8-v or 2.5-v/3.3-v i/o standards. the tdo pin voltage is determined by the v ccio of the bank where it resides. the vccsel pin selects whether the jtag inpu ts are 1.5-v, 1.8-v, 2.5-v, or 3.3-v compatible. stratix devices also use the jtag port to monitor the logic operation of the device with the signaltap ? ii embedded logic analyzer. stratix devices support the jtag instructions shown in table 3?1 . the quartus ii software has an auto usercode feature where you can choose to use the checksum value of a programming file as the jtag user code. if selected, the checksum is automatically loaded to the usercode register. in the settings dialog box in the assignments menu, click device & pin options , then general, and then turn on the auto usercode option. s51003-1.3 3?2 altera corporation stratix device handbook, volume 1 july 2005 ieee std. 1149.1 (jtag) boundary-scan support table 3?1. stratix jt ag instructions jtag instruction instr uction code description sample/preload 00 0000 0101 allows a snapshot of si gnals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. also used by the signaltap ii embedded logic analyzer. extest (1) 00 0000 0000 allows the external circui try and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass 11 1111 1111 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation. usercode 00 0000 0111 selects the 32-bit usercode register and places it between the tdi and tdo pins, allowing the usercode to be serially shifted out of tdo . idcode 00 0000 0110 selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . highz (1) 00 0000 1011 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the i/o pins. clamp (1) 00 0000 1010 places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through selected devices to adjacent devices duri ng normal device operation while holding i/o pins to a state defined by the data in the boundary-scan register. icr instructions used when configuring an st ratix device via the jtag port with a masterblaster tm , byteblastermv tm , or byteblaster tm ii download cable, or when using a jam file or jam byte-code file via an embedded processor or jrunner. pulse_nconfig 00 0000 0001 emulates pulsing the nconfig pin low to trigger reconfiguration even though the physical pin is unaffected. config_io 00 0000 1101 allows configuration of i/o standards through the jtag chain for jtag testing. can be executed before, after, or during configuration. stops configuration if executed during configuration. once issued, the config_io instruction will hold nstatus low to reset the configuration device. nstatus is held low until the device is reconfigured. signaltap ii instructions monitors internal device operation with the signaltap ii embedded logic analyzer. note to ta b l e 3 ? 1 : (1) bus hold and weak pull-up resistor feat ures override the high-impedance state of highz , clamp , and extest . altera corporation 3?3 july 2005 stratix device handbook, volume 1 configuration & testing the stratix device instruction register length is 10 bits and the usercode register length is 32 bits. tables 3?2 and 3?3 show the boundary-scan register length and device idcode information for stratix devices. table 3?2. stratix boundary-scan register length device boundary-scan register length ep1s10 1,317 ep1s20 1,797 ep1s25 2,157 ep1s30 2,253 ep1s40 2,529 ep1s60 3,129 ep1s80 3,777 table 3?3. 32-bit stratix device idcode device idcode (32 bits) (1) version (4 bits) part number (16 bits) manufacturer identity (11 bits) lsb (1 bit) (2) ep1s10 0000 0010 0000 0000 0001 000 0110 1110 1 ep1s20 0000 0010 0000 0000 0010 000 0110 1110 1 ep1s25 0000 0010 0000 0000 0011 000 0110 1110 1 ep1s30 0000 0010 0000 0000 0100 000 0110 1110 1 ep1s40 0000 0010 0000 0000 0101 000 0110 1110 1 ep1s60 0000 0010 0000 0000 0110 000 0110 1110 1 ep1s80 0000 0010 0000 0000 0111 000 0110 1110 1 notes to ta b l e s 3 ? 2 and 3?3 : (1) the most significant bit (msb) is on the left. (2) the idcode?s least significant bit (lsb) is always 1. 3?4 altera corporation stratix device handbook, volume 1 july 2005 ieee std. 1149.1 (jtag) boundary-scan support figure 3?1 shows the timing requirements for the jtag signals. figure 3?1. stratix jtag waveforms table 3?4 shows the jtag timing parameters and values for stratix devices. table 3?4. stratix jtag ti ming parameters & values symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 35 ns t jszx update register high impedance to valid output 35 ns t jsxz update register valid output to high impedance 35 ns tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms si g nal to be captured si g nal to be driven t jszx t jssu t jsh t jsco t jsxz altera corporation 3?5 july 2005 stratix device handbook, volume 1 configuration & testing 1 stratix, stratix ii, cyclone ? , and cyclone ii devices must be within the first 17 devices in a jt ag chain. all of these devices have the same jtag controller. if any of the stratix, stratix ii, cyclone, and cyclone ii devices ar e in the 18th or after they will fail configuration. this does not affect signaltap ii. f for more information on jtag, see the following documents: an 39: ieee std. 1149.1 (jtag) bounda ry-scan testing in altera devices jam programming & test language specification signaltap ii embedded logic analyzer stratix devices feature the signalta p ii embedded logic analyzer, which monitors design operation over a peri od of time throug h the ieee std. 1149.1 (jtag) circuitry. you can analyz e internal logic at speed without bringing internal signals to the i/o pins. this feature is particularly important for advanced packag es, such as fineline bga ? packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured. configuration the logic, circuitry, and interconne cts in the stratix architecture are configured with cmos sram elements. altera ? devices are reconfigurable. because every device is tested with a high-coverage production test program, you do not have to perform fault testing and can focus on simulation and design verification. stratix devices are configured at system power-up with data stored in an altera serial configuration device or provided by a system controller. altera offers in-system programmabi lity (isp)-capable configuration devices that configure stratix devices via a serial data stream. stratix devices can be configured in under 100 ms using 8-bit parallel data at 100 mhz. the stratix device?s optimized interface allows microprocessors to configure it serially or in parallel, and synchr onously or asynchronously. the interface also enables microprocessors to treat stratix devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. after a stratix device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. operating modes the stratix architecture uses sram configuration elements that require configuration data to be loaded each time the circuit powers up. the process of physically loading the sr am data into the device is called configuration. during initialization, which occurs immediately after 3?6 altera corporation stratix device handbook, volume 1 july 2005 configuration configuration, the device resets regist ers, enables i/o pins, and begins to operate as a logic device. the i/o pins are tri-stated during power-up, and before and during configuration. together, the configuration and initialization processes are called command mode. normal device operation is called user mode. sram configuration elements allow stratix devices to be reconfigured in- circuit by loading new configuration data into the device. with real-time reconfiguration, the device is forced into command mode with a device pin. the configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. you can perform in-field upgrades by distribu ting new configuration files either within the system or remotely. porsel is a dedicated input pin used to select por delay times of 2 ms or 100 ms during power-up. when the porsel pin is connected to ground, the por time is 100 ms; when the porsel pin is connected to v cc , the por time is 2 ms. the nio_pullup pin enables a built-in weak pull-up resistor to pull all user i/o pins to v ccio before and during device configuration. if nio_pullup is connected to v cc during configuration, the weak pull- ups on all user i/o pins are disabled . if connected to ground, the pull-ups are enabled during configuration. the nio_pullup pin can be pulled to 1.5, 1.8, 2.5, or 3.3 v for a logic level high. vccsel is a dedicated input that is used to choose whether all dedicated configuration and jtag input pins ca n accept 1.5 v/1.8 v or 2.5 v/3.3 v during configuration. a logic low sets 3.3 v/2.5 v, and a logic high sets 1.8 v/1.5 v. vccsel affects the following pins: tdi , tms , tck , trst , msel0 , msel1 , msel2 , nconfig , nce , dclk , pll_ena , conf_done , nstatus . the vccsel pin can be pulled to 1.5, 1.8, 2.5, or 3.3 v for a logic level high. the vccsel signal does not control the dual-purpose configuration pins such as the data[7..0] and ppa pins ( nws , nrs , cs , ncs , and rdynbsy ). during configuration, these dual-purpose pins will drive out voltage levels corresponding to the v ccio supply voltage that powers the i/o bank containing the pin. after co nfiguration, the dual-purpose pins use i/o standards specified in the user design. tdo and nceo drive out at the same voltages as the v ccio supply that powers the i/o bank containing th e pin. users must select the v ccio supply for bank containing tdo accordingly. for ex ample, when using the byteblaster ? mv cable, the v ccio for the bank containing tdo must be powered up at 3.3 v. altera corporation 3?7 july 2005 stratix device handbook, volume 1 configuration & testing configuring stratix fpgas with jrunner jrunner is a software driver that configures altera fpgas, including stratix fpgas, through th e byteblaster ii or by teblastermv cables in jtag mode. the programming input file supported is in raw binary file ( .rbf ) format. jrunner also requires a chain description file ( .cdf ) generated by the quartus ii software. jrunner is targeted for embedded jtag configuration. the source code is developed for the windows nt operating system (os), but can be cus tomized to run on other platforms. for more information on the jrunne r software driver, see the jrunner software driver: an embedded so lution to the jtag configuration white paper and the source files on the altera web site ( www.altera.com ). configuration schemes you can load the configuration data for a stratix device with one of five configuration schemes (see table 3?5 ), chosen on the basis of the target application. you can use a configuration device, intelligent controller, or the jtag port to configure a stratix device. a configuration device can automatically configure a strati x device at system power-up. multiple stratix devices can be configured in any of five configuration schemes by connecting th e configuration enable ( nce ) and configuration enable output ( nceo ) pins on each device. partial reconfiguration the enhanced plls within the stratix device family support partial reconfiguration of their multiply, di vide, and time delay settings without reconfiguring the entire device. you ca n use either serial data from the logic array or regular i/o pins to pr ogram the pll?s counter settings in a serial chain. this option provides considerable flexibility for frequency table 3?5. data sources for configuration configuration sc heme data source configuration device enhanced or epc2 configuration device passive serial (ps) masterblaster, byteblastermv, or byteblaster ii download cable or serial data source passive parallel asynchronous (ppa) parallel data source fast passive parallel parallel data source jtag masterblaster, byteblastermv, or byteblaster ii download cable, a microprocessor with a jam or jbc file, or jrunner 3?8 altera corporation stratix device handbook, volume 1 july 2005 configuration synthesis, allowing real-time variat ion of the pll frequency and delay. the rest of the device is functional while reconfiguring the pll. see the stratix architecture chapter of the stratix device handbook, volume 1 for more information on stratix plls. remote update co nfiguration modes stratix devices also support remote configuration using an altera enhanced configuration device (e.g., epc16, epc8, and epc4 devices) with page mode selection. factory configuration data is stored in the default page of the configuration device. this is the default configuration that contains the design required to control remote updates and handle or recover from errors. you write the factory configuration once into the flash memory or configuration device. remote update data can update any of the remaining pages of the config uration device. if there is an error or corruption in a remote update co nfiguration, the configuration device reverts back to the factory configuration information. there are two remote configuration modes: remote and local configuration. you can use the remote update configuration mode for all three configuration modes: serial, pa rallel synchronou s, and parallel asynchronous. configuration devices (for example, epc16 devices) only support serial and parallel synchron ous modes. asynchronous parallel mode allows remote updates when an intelligent host is used to configure the stratix device. this host must suppo rt page mode settings similar to an epc16 device. remote update mode when the stratix device is firs t powered up in remote update programming mode, it loads the configuration located at page address ? 000 .? the factory configuration should always be located at page address ? 000 ,? and should never be remotely updated. the factory configuration contains the requir ed logic to perform the following operations: determine the page address/load lo cation for the next application?s configuration data recover from a previous configuration error receive new configuration data and write it into the configuration device the factory configuration is the defa ult and takes control if an error occurs while loading the application configuration. altera corporation 3?9 july 2005 stratix device handbook, volume 1 configuration & testing while in the factory configuration, the factory-configuration logic performs the following operations: loads a remote update-control register to determine the page address of the new application configuration determines whether to enable a user watchdog timer for the application configuration determines what the watchdog time r setting should be if it is enabled the user watchdog timer is a coun ter that must be continually reset within a specific amount of time in the user mode of an application configuration to ensure that valid co nfiguration occurred during a remote update. only valid application configurations designed for remote update can reset the user watchdog timer in user mode. if a valid application configuration does not re set the user watchdog timer in a specific amount of time, the timer up dates a status register and loads the factory configuration. the user watchd og timer is automatically disabled for factory configurations. if an error occurs in loading th e application configuration, the configuration logic writes a status register to specify the cause of the error. once this occurs, the stratix devi ce automatically loads the factory configuration, which read s the status register and determines the reason for reconfiguration. based on the re ason, the factory co nfiguration will take appropriate steps and will write the remote update control register to specify the next application configuration page to be loaded. when the stratix device successfully loads the application configuration, it enters into user mode. the strati x device then executes the main application of the user. intellectua l property (ip), such as a nios ? (16-bit isa) and nios ? ii (32-bit isa) embedded processors, can help the stratix device determine when remote upda te is coming. the nios embedded processor or user logic receives incoming data, writes it to the configuration device, and loads the factory configuration. the factory configuration will read the remote update status register and determine the valid application configuration to load. figure 3?2 shows the stratix remote update. figure 3?3 shows the transition diagram for remote update mode. 3?10 altera corporation stratix device handbook, volume 1 july 2005 configuration figure 3?2. stratix devi ce remote update note to figure 3?2 : (1) when the stratix device is configured with the factory co nfiguration, it can handle upda te data from epc16, epc8, or epc4 configuration device pages and point to the next page in the configuration device. watchdo g timer stratix device new remote confi g uration data confi g uration device application confi g uration application confi g uration factory confi g uration (1) c on f i g u rat ion de vi ce updates strat ix de vi ce wi t h f act o r y c on f i g u rat ion ( t o h a n d l e update ) o r n e w a pp li cat ion c on f i g u rat ion page 7 page 6 page 0 altera corporation 3?11 july 2005 stratix device handbook, volume 1 configuration & testing figure 3?3. remote update transition diagram notes (1) , (2) notes to figure 3?3 : (1) remote update of application config uration is controlled by a nios embedded processor or user logic programmed in the factory or application configurations. (2) up to seven pages can be specified allowing up to seven different configuration applications. confi g uration error confi g uration error application 1 confi g uration confi g uration error factory confi g uration reload an application reload an application application n confi g uration power-up 3?12 altera corporation stratix device handbook, volume 1 july 2005 stratix automated single event upset (seu) detection local update mode local update mode is a simplified version of the remote update. this feature is intended for simple systems that need to load a single application configuration immediately upon power up without loading the factory configuration first. local update designs have only one application configuratio n to load, so it does not require a factory configuration to determine which application configuration to use. figure 3?4 shows the transition diagram for local update mode. figure 3?4. local update transition diagram stratix automated single event upset (seu) detection stratix devices offer on-chip circuitr y for automated checking of single event upset (seu) detection. fpga devi ces that operate at high elevations or in close proximity to earth?s north or south pole require periodic checks to ensure continued data integrity. the error detection cyclic redundancy check (crc) feature controlled by the device & pin options dialog box in the quartus ii software uses a 32-bit crc circuit to ensure data reliability and is one of the best options for mitigating seu. nconfig nconfig confi g uration error application confi g uration confi g uration error factory confi g uration power-up or nconfig altera corporation 3?13 july 2005 stratix device handbook, volume 1 configuration & testing for stratix, the crc is computed by the quartus ii software and downloaded into the device as a part of the configuration bit stream. the crc_error pin reports a soft error when configuration sram data is corrupted, triggering device reconfiguration. custom-built circuitry dedicated circuitry is built in th e stratix devices to perform error detection automatically. you can use th e built-in dedicated circuitry for error detection using crc feature in stratix devices, eliminating the need for external logic. this circui try will perform error detection automatically when enabled. this error detection circuitry in stratix devices constantly checks for errors in the configuration sram cells while the device is in user mode. yo u can monitor one external pin for the error and use it to trigger a re-configu ration cycle. select the desired time between checks by adjusting a built-in clock divider. software interface in the quartus ii software version 4.1 and later, you can turn on the automated error detection crc feature in the device & pin options dialog box. this dialog box allows you to enable the feature and set the internal frequency of the crc between 400 khz to 100 mhz. this controls the rate that the crc circuitry verifi es the internal configuration sram bits in the fpga device. for more information on crc, see an 357: error detection using crc in altera fpga devices . temperature sensing diode stratix devices include a diode-connected transistor for use as a temperature sensor in power manageme nt. this diode is used with an external digital thermometer devi ce such as a max1617a or max1619 from maxim integrated products. these devices steer bias current through the stratix diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus sign). the external device?s output re presents the junction temperature of the stratix device and can be used for intelligent power management. the diode requires two pins ( tempdiodep and tempdioden ) on the stratix device to connect to the exte rnal temperature-sensing device, as shown in figure 3?5 . the temperature sensing diode is a passive element and therefore can be used before the stratix device is powered. 3?14 altera corporation stratix device handbook, volume 1 july 2005 temperature sensing diode figure 3?5. external temperature-sensing diode table 3?6 shows the specifications for bias voltage and current of the stratix temperature sensing diode. table 3?6. temperature-sensing di ode electrical characteristics parameter minimum typical maximum unit i bias high 80 100 120 a i bias low 8 10 12 a v bp ? v bn 0.3 0.9 v v bn 0.7 v series resistance 3 w stratix device temperature-sensin g device tempdiodep tempdioden altera corporation 3?15 july 2005 stratix device handbook, volume 1 configuration & testing the temperature-sensing diode works for the entire operating range shown in figure 3?6 . figure 3?6. temperature vs. temperature-sensing diode voltage 0.90 0.85 0.95 0.75 0.65 voltage (across diode) temperature ( c) 0.55 0.45 0.60 0.50 0.40 0.70 0.80 ? 55 ? 30 ? 520457095120 10 a bias current 100 a bias current 3?16 altera corporation stratix device handbook, volume 1 july 2005 temperature sensing diode altera corporation 4?1 january 2006 4. dc & switching characteristics operating conditions stratix ? devices are offered in both co mmercial and indu strial grades. industrial devices are offered in -6 and -7 speed grades and commercial devices are offered in -5 (fastest), -6 , -7, and -8 speed grades. this section specifies the operation conditions fo r operating junction temperature, v ccint and v ccio voltage levels, and input voltage requirements. the voltage specifications in this section are specified at the pins of the device (and not the power supply). if the de vice operates outside these ranges, then all dc and ac specifications are not guaranteed. furthermore, the reliability of the device may be affected. the timing parameters in this chapter apply to both commercial an d industrial temperature ranges unless otherwise stated. tables 4?1 through 4?8 provide information on absolute maximum ratings. table 4?1. stratix device absolute maximum ratings notes (1) , (2) symbol parameter conditions minimum maximum unit v ccint supply voltage with respect to ground ?0.5 2.4 v v ccio ?0.5 4.6 v v i dc input voltage (3) ?0.5 4.6 v i out dc output current, per pin ?25 40 ma t stg storage temperature no bias ?65 150 c t j junction temperature bga packages under bias 135 c table 4?2. stratix device recommend ed operating conditions (part 1 of 2) symbol parameter conditions minimum maximum unit v ccint supply voltage for internal logic and input buffers (4) 1.425 1.575 v s51004-3.4 4?2 altera corporation stratix device handbook, volume 1 january 2006 operating conditions v ccio supply voltage for output buffers, 3.3-v operation (4) , (5) 3.00 (3.135) 3.60 (3.465) v supply voltage for output buffers, 2.5-v operation (4) 2.375 2.625 v supply voltage for output buffers, 1.8-v operation (4) 1.71 1.89 v supply voltage for output buffers, 1.5-v operation (4) 1.4 1.6 v v i input voltage (3) , (6) ?0.5 4.0 v v o output voltage 0 v ccio v t j operating junction temperature for commercial use 0 85 c for industrial use ?40 100 c table 4?3. stratix device dc operating conditions note (7) (part 1 of 2) symbol parameter conditions minimum typical maximum unit i i input pin leakage current v i = v cciomax to 0 v (8) ?10 10 a i oz tri-stated i/o pin leakage current v o = v cciomax to 0 v (8) ?10 10 a i cc0 v cc supply current (standby) (all memory blocks in power-down mode) v i = ground, no load, no toggling inputs ma ep1s10. v i = ground, no load, no toggling inputs 37 ma ep1s20. v i = ground, no load, no toggling inputs 65 ma ep1s25. v i = ground, no load, no toggling inputs 90 ma ep1s30. v i = ground, no load, no toggling inputs 114 ma ep1s40. v i = ground, no load, no toggling inputs 145 ma ep1s60. v i = ground, no load, no toggling inputs 200 ma ep1s80. v i = ground, no load, no toggling inputs 277 ma table 4?2. stratix device recommend ed operating conditions (part 2 of 2) symbol parameter conditions minimum maximum unit altera corporation 4?3 january 2006 stratix device handbook, volume 1 dc & switching characteristics r conf value of i/o pin pull- up resistor before and during configuration v ccio = 3.0 v (9) 20 50 k v ccio = 2.375 v (9) 30 80 k v ccio = 1.71 v (9) 60 150 k table 4?4. lvttl specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage i oh = ?4 to ?24 ma (10) 2.4 v v ol low-level output voltage i ol = 4 to 24 ma (10) 0.45 v table 4?5. lvcmos specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage v ccio = 3.0, i oh = ?0.1 ma v ccio ? 0.2 v v ol low-level output voltage v ccio = 3.0, i ol = 0.1 ma 0.2 v table 4?6. 2.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 2.375 2.625 v v ih high-level input voltage 1.7 4.1 v v il low-level input voltage ?0.5 0.7 v v oh high-level output voltage i oh = ?1 ma (10) 2.0 v v ol low-level output voltage i ol = 1 ma (10) 0.4 v table 4?3. stratix device dc operating conditions note (7) (part 2 of 2) symbol parameter conditions minimum typical maximum unit 4?4 altera corporation stratix device handbook, volume 1 january 2006 operating conditions table 4?7. 1.8-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 1.65 1.95 v v ih high-level input voltage 0.65 v ccio 2.25 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 to ?8 ma (10) v ccio ? 0.45 v v ol low-level output voltage i ol = 2 to 8 ma (10) 0.45 v table 4?8. 1.5-v i/o specifications symbol parameter conditions minimum maximum unit v ccio output supply voltage 1.4 1.6 v v ih high-level input voltage 0.65 v ccio v ccio + 0.3 v v il low-level input voltage ?0.3 0.35 v ccio v v oh high-level output voltage i oh = ?2 ma (10) 0.75 v ccio v v ol low-level output voltage i ol = 2 ma (10) 0.25 v ccio v notes to ta b l e s 4 ? 1 through 4?8 : (1) see the operating requirements for altera devices data sheet . (2) conditions beyond those listed in table 4?1 may cause permanent damage to a device. additionally, device operation at the absolute maximum ratings for extended pe riods of time may have adve rse affects on the device. (3) minimum dc input is ?0.5 v. during transitions, the in puts may undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns, or overshoot to the voltage shown in table 4?9 , based on input duty cycle for input currents less than 100 ma. the overshoot is depe ndent upon duty cycle of th e signal. the dc case is equivalent to 100% duty cycle. (4) maximum v cc rise time is 100 ms, and v cc must rise monotonically. (5) v ccio maximum and minimum conditions for lvpecl, lvds, and 3.3-v pcml are shown in parentheses. (6) all pins, including dedicated inputs, clock, i/o, and jtag pins, may be driven before v ccint and v ccio are powered. (7) typical values are for t a = 25c, v ccint = 1.5 v, and v ccio = 1.5 v, 1.8 v, 2.5 v, and 3.3 v. (8) this value is specified for normal device operation. the value may vary during power-up. this applies for all v ccio settings (3.3, 2.5, 1.8, and 1.5 v). (9) pin pull-up resistance values will lower if an external source drives the pin higher than v ccio . (10) drive strength is programmable according to the values shown in the stratix architecture chapter of the stratix device handbook, volume 1 . table 4?9. overshoot input voltage with respect to duty cycle (part 1 of 2) vin (v) maximum duty cycle (%) 4.0 100 4.1 90 4.2 50 altera corporation 4?5 january 2006 stratix device handbook, volume 1 dc & switching characteristics figures 4?1 and 4?2 show receiver input and transmitter output waveforms, respectively, for all diffe rential i/o standards (lvds, 3.3-v pcml, lvpecl, and hypert ransport technology). figure 4?1. receiver input waveform s for differential i/o standards 4.3 30 4.4 17 4.5 10 table 4?9. overshoot input voltage with respect to duty cycle (part 2 of 2) vin (v) maximum duty cycle (%) single-ended waveform differential waveform positive channel (p) = v ih ne g ative channel (n) = v il ground v id v id v id v cm p ? n = 0 v 4?6 altera corporation stratix device handbook, volume 1 january 2006 operating conditions figure 4?2. transmitter output wavefo rms for differential i/o standards tables 4?10 through 4?33 recommend operating conditions, dc operating conditions, and ca pacitance for 1.5-v stratix devices. single-ended waveform differential waveform positive channel (p) = v oh ne g ative channel (n) = v ol ground v od v od v od p ? n = 0 v v cm table 4?10. 3.3-v lvds i/o specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 3.135 3.3 3.465 v v id (6) input differential voltage swing (single-ended) 0.1 v v cm < 1.1 v w = 1 through 10 300 1,000 mv 1.1 v v cm 1.6 v w = 1 200 1,000 mv 1.1 v v cm 1.6 v w = 2 through10 100 1,000 mv 1.6 v < v cm 1.8 v w = 1 through 10 300 1,000 mv altera corporation 4?7 january 2006 stratix device handbook, volume 1 dc & switching characteristics v icm input common mode voltage (6) lv d s 0.3 v v id 1.0 v w = 1 through 10 100 1,100 mv lv d s 0.3 v v id 1.0 v w = 1 through 10 1,600 1,800 mv lv d s 0.2 v v id 1.0 v w = 1 1,100 1,600 mv lv d s 0.1 v v id 1.0 v w = 2 through 10 1,100 1,600 mv v od (1) output differential voltage (single-ended) r l = 100 250 375 550 mv v od change in v od between high and low r l = 100 50 mv v ocm output common mode voltage r l = 100 1,125 1,200 1,375 mv v ocm change in v ocm between high and low r l = 100 50 mv r l receiver differential input discrete resistor (external to stratix devices) 90 100 110 table 4?10. 3.3-v lvds i/o specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit 4?8 altera corporation stratix device handbook, volume 1 january 2006 operating conditions table 4?11. 3.3-v pcml specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 3.135 3.3 3.465 v v id (peak- to-peak) input differential voltage swing (single-ended) 300 600 mv v icm input common mode voltage 1.5 3.465 v v od output differential voltage (single-ended) 300 370 500 mv v od change in v od between high and low 50 mv v ocm output common mode voltage 2.5 2.85 3.3 v v ocm change in v ocm between high and low 50 mv v t output termination voltage v ccio v r 1 output external pull-up resistors 45 50 55 r 2 output external pull-up resistors 45 50 55 table 4?12. lvpecl specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 3.135 3.3 3.465 v v id (peak- to-peak) input differential voltage swing (single-ended) 300 1,000 mv v icm input common mode voltage 12v v od output differential voltage (single-ended) r l = 100 525 700 970 mv v ocm output common mode voltage r l = 100 1.5 1.7 1.9 v r l receiver differential input resistor 90 100 110 altera corporation 4?9 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?13. hypertransport te chnology spec ifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 2.375 2.5 2.625 v v id (peak- to-peak) input differential voltage swing (single-ended) 300 900 mv v icm input common mode voltage 300 900 mv v od output differential voltage (single-ended) r l = 100 380 485 820 mv v od change in v od between high and low r l = 100 50 mv v ocm output common mode voltage r l = 100 440 650 780 mv v ocm change in v ocm between high and low r l = 100 50 mv r l receiver differential input resistor 90 100 110 table 4?14. 3.3-v pci specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.5 0.3 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v 4?10 altera corporation stratix device handbook, volume 1 january 2006 operating conditions table 4?15. pci-x 1.0 specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.6 v v ih high-level input voltage 0.5 v ccio v ccio + 0.5 v v il low-level input voltage ?0.5 0.35 v ccio v v ipu input pull-up voltage 0.7 v ccio v v oh high-level output voltage i out = ?500 a0.9 v ccio v v ol low-level output voltage i out = 1,500 a0.1 v ccio v table 4?16. gtl+ i/o specifications symbol parameter conditions minimum typical maximum unit v tt termination voltage 1.35 1.5 1.65 v v ref reference voltage 0.88 1.0 1.12 v v ih high-level input voltage v ref + 0.1 v v il low-level input voltage v ref ? 0.1 v v ol low-level output voltage i ol = 34 ma (3) 0.65 v table 4?17. gtl i/o specifications symbol parameter conditions minimum typical maximum unit v tt termination voltage 1.14 1.2 1.26 v v ref reference voltage 0.74 0.8 0.86 v v ih high-level input voltage v ref + 0.05 v v il low-level input voltage v ref ? 0.05 v v ol low-level output voltage i ol = 40 ma (3) 0.4 v altera corporation 4?11 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?18. sstl-18 clas s i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.8 1.95 v v ref reference voltage 0.8 0.9 1.0 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih(dc) high-level dc input voltage v ref + 0.125 v v il(dc) low-level dc input voltage v ref ? 0.125 v v ih(ac) high-level ac input voltage v ref + 0.275 v v il(ac) low-level ac input voltage v ref ? 0.275 v v oh high-level output voltage i oh = ?6.7 ma (3) v tt + 0.475 v v ol low-level output voltage i ol = 6.7 ma (3) v tt ? 0.475 v table 4?19. sstl-18 clas s ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.8 1.95 v v ref reference voltage 0.8 0.9 1.0 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ih(dc) high-level dc input voltage v ref + 0.125 v v il(dc) low-level dc input voltage v ref ? 0.125 v v ih(ac) high-level ac input voltage v ref + 0.275 v v il(ac) low-level ac input voltage v ref ? 0.275 v v oh high-level output voltage i oh = ?13.4 ma (3) v tt + 0.630 v v ol low-level output voltage i ol = 13.4 ma (3) v tt ? 0.630 v 4?12 altera corporation stratix device handbook, volume 1 january 2006 operating conditions table 4?20. sstl-2 class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.15 1.25 1.35 v v ih(dc) high-level dc input voltage v ref + 0.18 3.0 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.18 v v ih(ac) high-level ac input voltage v ref + 0.35 v v il(ac) low-level ac input voltage v ref ? 0.35 v v oh high-level output voltage i oh = ?8.1 ma (3) v tt + 0.57 v v ol low-level output voltage i ol = 8.1 ma (3) v tt ? 0.57 v table 4?21. sstl-2 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.375 2.5 2.625 v v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v v ref reference voltage 1.15 1.25 1.35 v v ih(dc) high-level dc input voltage v ref + 0.18 v ccio + 0.3 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.18 v v ih(ac) high-level ac input voltage v ref + 0.35 v v il(ac) low-level ac input voltage v ref ? 0.35 v v oh high-level output voltage i oh = ?16.4 ma (3) v tt + 0.76 v v ol low-level output voltage i ol = 16.4 ma (3) v tt ? 0.76 v table 4?22. sstl-3 class i specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v v ih(dc) high-level dc input voltage v ref + 0.2 v ccio + 0.3 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.2 v v ih(ac) high-level ac input voltage v ref + 0.4 v altera corporation 4?13 january 2006 stratix device handbook, volume 1 dc & switching characteristics v il(ac) low-level ac input voltage v ref ? 0.4 v v oh high-level output voltage i oh = ?8 ma (3) v tt + 0.6 v v ol low-level output voltage i ol = 8 ma (3) v tt ? 0.6 v table 4?23. sstl-3 class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.0 3.3 3.6 v v tt termination voltage v ref ? 0.05 v ref v ref + 0.05 v v ref reference voltage 1.3 1.5 1.7 v v ih(dc) high-level dc input voltage v ref + 0.2 v ccio + 0.3 v v il(dc) low-level dc input voltage ?0.3 v ref ? 0.2 v v ih(ac) high-level ac input voltage v ref + 0.4 v v il(ac) low-level ac input voltage v ref ? 0.4 v v oh high-level output voltage i oh = ?16 ma (3) v tt + 0.8 v v ol low-level output voltage i ol = 16 ma (3) v tt ? 0.8 v table 4?24. 3.3-v agp 2 specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.15 3.3 3.45 v v ref reference voltage 0.39 v ccio 0.41 v ccio v v ih high-level input voltage (4) 0.5 v ccio v ccio + 0.5 v v il low-level input voltage (4) 0.3 v ccio v v oh high-level output voltage i out = ?0.5 ma 0.9 v ccio 3.6 v v ol low-level output voltage i out = 1.5 ma 0.1 v ccio v table 4?25. 3.3-v agp 1 specifications (part 1 of 2) symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 3.15 3.3 3.45 v v ih high-level input voltage (4) 0.5 v ccio v ccio + 0.5 v v il low-level input voltage (4) 0.3 v ccio v table 4?22. sstl-3 class i specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit 4?14 altera corporation stratix device handbook, volume 1 january 2006 operating conditions v oh high-level output voltage i out = ?0.5 ma 0.9 v ccio 3.6 v v ol low-level output voltage i out = 1.5 ma 0.1 v ccio v table 4?26. 1.5-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.4 1.5 1.6 v v ref input reference voltage 0.68 0.75 0.9 v v tt termination voltage 0.7 0.75 0.8 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = ?8 ma (3) v ccio ? 0.4 v v ol low-level output voltage i ol = 8 ma (3) 0.4 v table 4?27. 1.5-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.4 1.5 1.6 v v ref input reference voltage 0.68 0.75 0.9 v v tt termination voltage 0.7 0.75 0.8 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = ?16 ma (3) v ccio ? 0.4 v v ol low-level output voltage i ol = 16 ma (3) 0.4 v table 4?25. 3.3-v agp 1 specifications (part 2 of 2) symbol parameter conditions minimum typical maximum unit altera corporation 4?15 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?28. 1.8-v hstl class i specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.80 1.95 v v ref input reference voltage 0.70 0.90 0.95 v v tt termination voltage v ccio 0.5 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.5 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = ?8 ma (3) v ccio ? 0.4 v v ol low-level output voltage i ol = 8 ma (3) 0.4 v table 4?29. 1.8-v hstl class ii specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 1.65 1.80 1.95 v v ref input reference voltage 0.70 0.90 0.95 v v tt termination voltage v ccio 0.5 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.5 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = ?16 ma (3) v ccio ? 0.4 v v ol low-level output voltage i ol = 16 ma (3) 0.4 v table 4?30. 1.5-v differential hstl cl ass i & class ii specifications symbol parameter conditions minimum typical maximum unit v ccio i/o supply voltage 1.4 1.5 1.6 v v dif (dc) dc input differential voltage 0.2 v v cm (dc) dc common mode input voltage 0.68 0.9 v v dif (ac) ac differential input voltage 0.4 v 4?16 altera corporation stratix device handbook, volume 1 january 2006 operating conditions table 4?31. ctt i/o specifications symbol parameter conditions minimum typical maximum unit v ccio output supply voltage 2.05 3.3 3.6 v v tt /v ref termination and input reference voltage 1.35 1.5 1.65 v v ih high-level input voltage v ref + 0.2 v v il low-level input voltage v ref ? 0.2 v v oh high-level output voltage i oh = ?8 ma v ref + 0.4 v v ol low-level output voltage i ol = 8 ma v ref ? 0.4 v i o output leakage current (when output is high z ) gnd v out v ccio ?10 10 a table 4?32. bus hold parameters parameter conditions v ccio level unit 1.5 v1.8 v2.5 v3.3 v min max min max min max min max low sustaining current v in > v il (maximum) 25 30 50 70 a high sustaining current v in < v ih (minimum) -25 ?30 ?50 ?70 a low overdrive current 0 v < v in < v ccio 160 200 300 500 a high overdrive current 0 v < v in < v ccio -160 ?200 ?300 ?500 a bus-hold trip point 0.5 1.0 0.68 1.07 0.7 1.7 0.8 2.0 v altera corporation 4?17 january 2006 stratix device handbook, volume 1 dc & switching characteristics power consumption altera ? offers two ways to calculate power for a design: the altera web power calculator and the powergauge tm feature in the quartus ? ii software. the interactive power calculator on th e altera web site is typically used prior to designing the fpga in order to get a magnitude estimate of the device power. the quartus ii software powergauge feature allows you to apply test vectors against your design for more accurate power consumption modeling. in both cases, these calculations should only be used as an estimation of power, not as a specification. stratix devices require a certain amount of power-up current to successfully power up because of th e small process ge ometry on which they are fabricated. table 4?34 shows the maximum power-up current (i ccint ) required to power a stratix device. this specification is for commercial operating conditions. measurements were perf ormed with an isolated stratix device on the board to characterize the power-up current of an isolated table 4?33. stratix device capacitance note (5) symbol parameter minimum typical maximum unit c iotb input capacitance on i/o pins in i/o banks 3, 4, 7, and 8. 11.5 pf c iolr input capacitance on i/o pins in i/o banks 1, 2, 5, and 6, including high-speed differential receiver and transmitter pins. 8.2 pf c clktb input capacitance on top/bottom clock input pins: clk[4:7] and clk[12:15] . 11.5 pf c clklr input capacitance on left/right clock inputs: clk1 , clk3 , clk8 , clk10 . 7.8 pf c clklr+ input capacitance on left/right clock inputs: clk0 , clk2 , clk9 , and clk11 . 4.4 pf notes to tables 4?10 through 4?33 : (1) when tx_outclock port of altlvds_tx megafunction is 717 mhz, v od(min) = 235 mv on the output clock pin. (2) pin pull-up resistance values will lower if an external source drives the pin higher than v ccio . (3) drive strength is programmable ac cording to the values shown in the stratix architecture chapter of the stratix device handbook, volume 1 . (4) v ref specifies the center point of the switching range. (5) capacitance is sample-tested only. capacitance is me asured using time-domain reflections (tdr). measurement accuracy is within 0.5 pf. (6) v io and v cm have multiple ranges and values for j=1 through 10. 4?18 altera corporation stratix device handbook, volume 1 january 2006 power consumption device. decoupling capacitors were not used in this measurement. to factor in the current for decoupling capacitors, sum up the current for each capacitor using the following equation: i = c (dv/dt) if the regulator or power supply mini mum output current is more than the stratix device requires, then the device may consume more current than the maximum current listed in table 4?34 . however, the device does not require any more current to successf ully power up than what is listed in table 4?34 . the exact amount of current consumed varies according to the process, temperature, and power ramp rate. st ratix devices typically require less current during power up than shown in table 4?34 . the user-mode current during device operation is generally higher than the power-up current. the duration of the i ccint power-up requirement depends on the v ccint voltage supply rise time. the power-up current consumption drops when the v ccint supply reaches approximately 0.75 v. table 4?34. stratix power-up current (i ccint ) requirements note (1) device power-up current requirement unit typical maximum ep1s10 250 700 ma ep1s20 400 1,200 ma ep1s25 500 1,500 ma ep1s30 550 1,900 ma ep1s40 650 2,300 ma ep1s60 800 2,600 ma ep1s80 1,000 3,000 ma note to table 4?34 : (1) the maximum test conditions are for 0 c and typical test conditions are for 40 c. altera corporation 4?19 january 2006 stratix device handbook, volume 1 dc & switching characteristics timing model the directdrive ? technology and multitrack ? interconnect ensure predictable performance, accurate simulation, and ac curate timing analysis across all stratix device densities and speed grades. this section describes and specifies the performance, internal, external, and pll timing specifications. all specifications are representative of worst-case supply voltage and junction temperature conditions. preliminary & final timing timing models can have either preliminary or final status. the quartus ii software issues an informational me ssage during the design compilation if the timing models are preliminary. table 4?35 shows the status of the stratix device timing models. preliminary status means the timing model is subject to change. initially, timing numbers are created using simulation results, process data, and other known parameters. these tests are used to make the preliminary numbers as close to the actual timing parameters as possible. final timing numbers are based on ac tual device operation and testing. these numbers reflect the actual perf ormance of the device under worst- case voltage and junction temperature conditions. table 4?35. stratix device timing model status device preliminary final ep1s10 v ep1s20 v ep1s25 v ep1s30 v ep1s40 v ep1s60 v ep1s80 v 4?20 altera corporation stratix device handbook, volume 1 january 2006 timing model performance table 4?36 shows stratix performance fo r some common designs. all performance values were obtained with quartus ii software compilation of lpm, or megacore ? functions for the fir and fft designs. table 4?36. stratix performance (part 1 of 2) notes (1) , (2) applications resources used performance les trimatrix memory blocks dsp blocks -5 speed grade -6 speed grade -7 speed grade -8 speed grade units le 16-to-1 multiplexer (1) 22 0 0 407.83 324.56 288.68 228.67 mhz 32-to-1 multiplexer (3) 46 0 0 318.26 255.29 242.89 185.18 mhz 16-bit counter 16 0 0 422.11 422.11 390.01 348.67 mhz 64-bit counter 64 0 0 321.85 290.52 261.23 220.5 mhz tr i m a t r i x memory m512 block simple dual-port ram 32 18 bit 0 1 0 317.76 277.62 241.48 205.21 mhz fifo 32 18 bit 30 1 0 319.18 278.86 242.54 206.14 mhz tr i m a t r i x memory m4k block simple dual-port ram 128 36 bit 0 1 0 290.86 255.55 222.27 188.89 mhz true dual-port ram 128 18 bit 0 1 0 290.86 255.55 222.27 188.89 mhz fifo 128 36 bit 34 1 0 290.86 255.55 222.27 188.89 mhz tr i m a t r i x memory m-ram block single port ram 4k 144 bit 1 1 0 255.95 223.06 194.06 164.93 mhz simple dual-port ram 4k 144 bit 0 1 0 255.95 233.06 194.06 164.93 mhz true dual-port ram 4k 144 bit 0 1 0 255.95 233.06 194.06 164.93 mhz single port ram 8k 72 bit 0 1 0 278.94 243.19 211.59 179.82 mhz simple dual-port ram 8k 72 bit 0 1 0 255.95 223.06 194.06 164.93 mhz true dual-port ram 8k 72 bit 0 1 0 255.95 223.06 194.06 164.93 mhz single port ram 16k 36 bit 0 1 0 280.66 254.32 221.28 188.00 mhz simple dual-port ram 16k 36 bit 0 1 0 269.83 237.69 206.82 175.74 mhz altera corporation 4?21 january 2006 stratix device handbook, volume 1 dc & switching characteristics tr i m a t r i x memory m-ram block true dual-port ram 16k 36 bit 0 1 0 269.83 237.69 206.82 175.74 mhz single port ram 32k 18 bit 0 1 0 275.86 244.55 212.76 180.83 mhz simple dual-port ram 32k 18 bit 0 1 0 275.86 244.55 212.76 180.83 mhz true dual-port ram 32k 18 bit 0 1 0 275.86 244.55 212.76 180.83 mhz single port ram 64k 9 bit 0 1 0 287.85 253.29 220.36 187.26 mhz simple dual-port ram 64k 9 bit 0 1 0 287.85 253.29 220.36 187.26 mhz true dual-port ram 64k 9 bit 0 1 0 287.85 253.29 220.36 187.26 mhz dsp block 9 9-bit multiplier (3) 0 0 1 335.0 293.94 255.68 217.24 mhz 18 18-bit multiplier (4) 0 0 1 278.78 237.41 206.52 175.50 mhz 36 36-bit multiplier (4) 0 0 1 148.25 134.71 117.16 99.59 mhz 36 36-bit multiplier (5) 0 0 1 278.78 237.41 206.52 175.5 mhz 18-bit, 4-tap fir filter 0 0 1 278.78 237.41 206.52 175.50 mhz larger designs 8-bit, 16-tap parallel fir filter 58 0 4 141.26 133.49 114.88 100.28 mhz 8-bit, 1,024-point fft function 870 5 1 261.09 235.51 205.21 175.22 mhz notes to table 4?36 : (1) these design performance numbers were obtained using the quartus ii software. (2) numbers not listed will be included in a future version of the data sheet. (3) this application uses regi stered inputs and outputs. (4) this application uses registered multiplier input and output stages within the dsp block. (5) this application uses registered multiplier input, pipeline, and output stages within the dsp block. table 4?36. stratix performance (part 2 of 2) notes (1) , (2) applications resources used performance les trimatrix memory blocks dsp blocks -5 speed grade -6 speed grade -7 speed grade -8 speed grade units 4?22 altera corporation stratix device handbook, volume 1 january 2006 timing model internal timing parameters internal timing parame ters are specified on a speed grade basis independent of device density. tables 4?37 through 4?42 describe the stratix device internal timing microparameters for les, ioes, trimatrix ? memory structures, dsp blocks, and multitrack interconnects. table 4?37. le internal timing microparameter descriptions symbol parameter t su le register setup time before clock t h le register hold time after clock t co le register clock-to-output delay t lut le combinatorial lut delay for data-in to data-out t clr minimum clear pulse width t pre minimum preset pulse width t clkhl register minimum clock high or low time. the maximum core clock frequency can be calculated by 1/(2 t clkhl ). table 4?38. ioe internal timing microparameter descriptions symbol parameter t su_r row ioe input register setup time t su_c column ioe input register setup time t h ioe input and output register hold time after clock t co_r row ioe input and output register clock-to-output delay t co_c column ioe input and output register clock-to-output delay t pin2combout_r row input pin to ioe combinatorial output t pin2combout_c column input pin to ioe combinatorial output t combin2pin_r row ioe data input to combinatorial output pin t combin2pin_c column ioe data input to combinatorial output pin t clr minimum clear pulse width t pre minimum preset pulse width t clkhl register minimum clock high or low time. the maximum i/o clock frequency can be calculated by 1/(2 t clkhl ). performance may also be affected by i/o timing, use of pll, and i/o programmable settings. altera corporation 4?23 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?39. dsp block internal timing microparameter descriptions symbol parameter t su input, pipeline, and output regist er setup time before clock t h input, pipeline, and output regi ster hold time after clock t co input, pipeline, and output regi ster clock-to-output delay t inreg2pipe9 input register to dsp bloc k pipeline register in 9 9-bit mode t inreg2pipe18 input register to dsp bloc k pipeline register in 18 18-bit mode t pipe2outreg2add dsp block pipeline register to output register delay in two- multipliers adder mode t pipe2outreg4add dsp block pipeline register to output register delay in four- multipliers adder mode t pd9 combinatorial input to output delay for 9 9 t pd18 combinatorial input to output delay for 18 18 t pd36 combinatorial input to output delay for 36 36 t clr minimum clear pulse width t clkhl register minimum clock high or low time. this is a limit on the min time for the clock on the registers in these blocks. the actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in table 4?36 on page 4?20 and as reported by the timing analyzer in the quartus ii software. 4?24 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?40. m512 block internal t iming microparameter descriptions symbol parameter t m512rc synchronous read cycle time t m512wc synchronous write cycle time t m512weresu write or read enable setup time before clock t m512wereh write or read enable hold time after clock t m512clkensu clock enable setup time before clock t m512clkenh clock enable hold time after clock t m512datasu data setup time before clock t m512datah data hold time after clock t m512waddrsu write address setup time before clock t m512waddrh write address hold time after clock t m512raddrsu read address setup time before clock t m512raddrh read address hold time after clock t m512dataco1 clock-to-output delay when using output registers t m512dataco2 clock-to-output delay without output registers t m512clkhl register minimum clock high or low time. this is a limit on the min time for the clock on the registers in these blocks. the actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in table 4?36 on page 4?20 and as reported by the timing analyzer in the quartus ii software. t m512clr minimum clear pulse width table 4?41. m4k block internal timing microparameter descriptions (part 1 of 2) symbol parameter t m4krc synchronous read cycle time t m4kwc synchronous write cycle time t m4kweresu write or read enable setup time before clock t m4kwereh write or read enable hold time after clock t m4kclkensu clock enable setup time before clock t m4kclkenh clock enable hold time after clock t m4kbesu byte enable setup time before clock t m4kbeh byte enable hold time after clock t m4kdataasu a port data setup time before clock altera corporation 4?25 january 2006 stratix device handbook, volume 1 dc & switching characteristics t m4kdataah a port data hold time after clock t m4kaddrasu a port address setup time before clock t m4kaddrah a port address hold time after clock t m4kdatabsu b port data setup time before clock t m4kdatabh b port data hold time after clock t m4kaddrbsu b port address setup time before clock t m4kaddrbh b port address hold time after clock t m4kdataco1 clock-to-output delay when using output registers t m4kdataco2 clock-to-output delay without output registers t m4kclkhl register minimum clock high or low time. this is a limit on the min time for the clock on the registers in these blocks. the actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in table 4?36 on page 4?20 and as reported by the timing analyzer in the quartus ii software. t m4kclr minimum clear pulse width table 4?42. m-ram block internal timing microparameter descriptions (part 1 of 2) symbol parameter t mramrc synchronous read cycle time t mramwc synchronous write cycle time t mramweresu write or read enable setup time before clock t mramwereh write or read enable hold time after clock t mramclkensu clock enable setup time before clock t mramclkenh clock enable hold time after clock t mrambesu byte enable setup time before clock t mrambeh byte enable hold time after clock t mramdataasu a port data setup time before clock t mramdataah a port data hold time after clock t mramaddrasu a port address setup time before clock t mramaddrah a port address hold time after clock t mramdatabsu b port setup time before clock table 4?41. m4k block internal timing microparameter descriptions (part 2 of 2) symbol parameter 4?26 altera corporation stratix device handbook, volume 1 january 2006 timing model t mramdatabh b port hold time after clock t mramaddrbsu b port address setup time before clock t mramaddrbh b port address hold time after clock t mramdataco1 clock-to-output delay when using output registers t mramdataco2 clock-to-output delay without output registers t mramclkhl register minimum clock high or low time. this is a limit on the min time for the clock on the registers in these blocks. the actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in table 4?36 on page 4?20 and as reported by the timing analyzer in the quartus ii software. t mramclr minimum clear pulse width. table 4?42. m-ram block internal timing microparameter descriptions (part 2 of 2) symbol parameter altera corporation 4?27 january 2006 stratix device handbook, volume 1 dc & switching characteristics figure 4?3 shows the trimatrix memory waveforms for the m512, m4k, and m-ram timing parameters shown in tables 4?40 through 4?42 . figure 4?3. dual-port ram timi ng microparameter waveform internal timing parame ters are specified on a speed grade basis independent of device density. tables 4?44 through 4?50 show the internal timing microparameters for les, ioes, trimatrix memory structures, dsp blocks, and multitrack interconnects. wrclock wren wraddress data-in reg_data-out an-1 an a0 a1 a2 a3 a4 a5 din-1 din din4 din5 rdclock a6 din6 unreg_data-out rden rdaddress bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 t weresu t wereh t datac o 1 t datac o 2 t datasu t data h t wereh t weresu t waddrsu t waddrh dout0 t rc table 4?43. routing delay internal timing microparameter descriptions (part 1 of 2) symbol parameter t r4 delay for an r4 line with average loading; covers a distance of four lab columns. t r8 delay for an r8 line with average lo ading; covers a distance of eight lab columns. t r24 delay for an r24 line with average loading; covers a distance of 24 lab columns. 4?28 altera corporation stratix device handbook, volume 1 january 2006 timing model t c4 delay for a c4 line with average loading; covers a distance of four lab rows. t c8 delay for a c8 line with average l oading; covers a distance of eight lab rows. t c16 delay for a c16 line with average loading; covers a distance of 16 lab rows. t local local interconnect delay, for connections within a lab, and for the final routing hop of connections to labs, dsp blocks, ram blocks and i/os. table 4?43. routing delay internal timing microparameter descriptions (part 2 of 2) symbol parameter table 4?44. le internal timing microparameters parameter -5 -6 -7 -8 unit min max min max min max min max t su 10 10 11 13 ps t h 100 100 114 135 ps t co 156 176 202 238 ps t lut 366 459 527 621 ps t clr 100 100 114 135 ps t pre 100 100 114 135 ps t clkhl 1000 1111 1190 1400 ps table 4?45. ioe internal tsu microparameter by device density (part 1 of 2) device symbol -5 -6 -7 -8 unit min max min max min max min max ep1s10 t su_r 76 80 80 80 ps t su_c 176 80 80 80 ps ep1s20 t su_r 76 80 80 80 ps t su_c 76 80 80 80 ps ep1s25 t su_r 276 280 280 280 ps t su_c 276 280 280 280 ps ep1s30 t su_r 76 80 80 80 ps t su_c 176 180 180 180 ps altera corporation 4?29 january 2006 stratix device handbook, volume 1 dc & switching characteristics ep1s40 t su_r 76 80 80 80 ps t su_c 376 380 380 380 ps ep1s60 t su_r 276 280 280 280 ps t su_c 276 280 280 280 ps ep1s80 t su_r 426 430 430 430 ps t su_c 76 80 80 80 ps table 4?46. ioe internal timing microparameters symbol -5 -6 -7 -8 unit min max min max min max min max t h 68 71 82 96 ps t co_r 171 179 206 242 ps t co_c 171 179 206 242 ps t pin2combout_r 1,234 1,295 1,490 1,753 ps t pin2combout_c 1,087 1,141 1,312 1,544 ps t combin2pin_r 3,894 4,089 4,089 4,089 ps t combin2pin_c 4,299 4,494 4,494 4,494 ps t clr 276 289 333 392 ps t pre 260 273 313 369 ps t clkhl 1,000 1,111 1,190 1,400 ps table 4?47. dsp block internal timing microparameters (part 1 of 2) symbol -5 -6 -7 -8 unit min max min max min max min max t su 0000ps t h 67 75 86 101 ps t co 142 158 181 214 ps t inreg2pipe9 2,613 2,982 3,429 4,035 ps t inreg2pipe18 3,390 3,993 4,591 5,402 ps table 4?45. ioe internal tsu microparameter by device density (part 2 of 2) device symbol -5 -6 -7 -8 unit min max min max min max min max 4?30 altera corporation stratix device handbook, volume 1 january 2006 timing model t pipe2outreg2add 2,002 2,203 2,533 2,980 ps t pipe2outreg4add 2,899 3,189 3,667 4,314 ps t pd9 3,709 4,081 4,692 5,520 ps t pd18 4,795 5,275 6,065 7,135 ps t pd36 7,495 8,245 9,481 11,154 ps t clr 450 500 575 676 ps t clkhl 1,350 1,500 1,724 2,029 ps table 4?48. m512 block internal timing microparameters symbol -5 -6 -7 -8 unit min max min max min max min max t m512rc 3,340 3,816 4,387 5,162 ps t m512wc 3,138 3,590 4,128 4,860 ps t m512weresu 110 123 141 166 ps t m512wereh 34 38 43 51 ps t m512clkensu 215 215 247 290 ps t m512clkenh ?70 ?70 ?81 ?95 ps t m512datasu 110 123 141 166 ps t m512datah 34 38 43 51 ps t m512waddrsu 110 123 141 166 ps t m512waddrh 34 38 43 51 ps t m512raddrsu 110 123 141 166 ps t m512raddrh 34 38 43 51 ps t m512dataco1 424 472 541 637 ps t m512dataco2 3,366 3,846 4,421 5,203 ps t m512clkhl 1,000 1,111 1,190 1,400 ps t m512clr 170 189 217 255 ps table 4?47. dsp block internal timing microparameters (part 2 of 2) symbol -5 -6 -7 -8 unit min max min max min max min max altera corporation 4?31 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?49. m4k block internal timing microparameters symbol -5 -6 -7 -8 unit min max min max min max min max t m4krc 3,807 4,320 4,967 5,844 ps t m4kwc 2,556 2,840 3,265 3,842 ps t m4kweresu 131 149 171 202 ps t m4kwereh 34 38 43 51 ps t m4kclkensu 193 215 247 290 ps t m4kclkenh ?63 ?70 ?81 ?95 ps t m4kbesu 131 149 171 202 ps t m4kbeh 34 38 43 51 ps t m4kdataasu 131 149 171 202 ps t m4kdataah 34 38 43 51 ps t m4kaddrasu 131 149 171 202 ps t m4kaddrah 34 38 43 51 ps t m4kdatabsu 131 149 171 202 ps t m4kdatabh 34 38 43 51 ps t m4kaddrbsu 131 149 171 202 ps t m4kaddrbh 34 38 43 51 ps t m4kdataco1 571 635 729 858 ps t m4kdataco2 3,984 4,507 5,182 6,097 ps t m4kclkhl 1,000 1,111 1,190 1,400 ps t m4kclr 170 189 217 255 ps table 4?50. m-ram block internal ti ming microparameters (part 1 of 2) symbol -5 -6 -7 -8 unit min max min max min max min max t mramrc 4,364 4,838 5,562 6,544 ps t mramwc 3,654 4,127 4,746 5,583 ps t mramweresu 25 25 28 33 ps t mramwereh 18 20 23 27 ps t mramclkensu 99 111 127 150 ps t mramclkenh ?48 ?53 ?61 ?72 ps 4?32 altera corporation stratix device handbook, volume 1 january 2006 timing model routing delays vary depending on the load on that specific routing line. the quartus ii software reports th e routing delay information when running the timing analysis for a design. t mrambesu 25 25 28 33 ps t mrambeh 18 20 23 27 ps t mramdataasu 25 25 28 33 ps t mramdataah 18 20 23 27 ps t mramaddrasu 25 25 28 33 ps t mramaddrah 18 20 23 27 ps t mramdatabsu 25 25 28 33 ps t mramdatabh 18 20 23 27 ps t mramaddrbsu 25 25 28 33 ps t mramaddrbh 18 20 23 27 ps t mramdataco1 1,038 1,053 1,210 1,424 ps t mramdataco2 4,362 4,939 5,678 6,681 ps t mramclkhl 1,000 1,111 1,190 1,400 ps t mramclr 135 150 172 202 ps table 4?51. routing delay internal timing parameters symbol -5 -6 -7 -8 unit min max min max min max min max t r4 268 295 339 390 ps t r8 371 349 401 461 ps t r24 465 512 588 676 ps t c4 440 484 557 641 ps t c8 577 634 730 840 ps t c16 445 489 563 647 ps t local 313 345 396 455 ps table 4?50. m-ram block internal ti ming microparameters (part 2 of 2) symbol -5 -6 -7 -8 unit min max min max min max min max altera corporation 4?33 january 2006 stratix device handbook, volume 1 dc & switching characteristics external timing parameters external timing parameters are specified by device density and speed grade. figure 4?4 shows the pin-to-pin timing model for bidirectional ioe pin timing. all registers are within the ioe. figure 4?4. external timing in stratix devices all external timing parameters report ed in this section are defined with respect to the dedicated clock pin as th e starting point. all external i/o timing parameters shown are for 3. 3-v lvttl i/o standard with the 24-ma current strength and fast slew rate. for external i/o timing using standards other than lvttl or for diff erent current strengths, use the i/o standard input and output delay adders in tables 4?103 through 4?108 . prn clrn dq oe re g ister prn clrn dq input re g ister prn clrn dq output re g ister bidirectional pin dedicated clock t in su t inh t ou t co t xz t zx 4?34 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?52 shows the external i/o timing parameters when using fast regional clock networks. table 4?53 shows the external i/o timing parameters when using regional clock networks. table 4?52. stratix fast regional clock external i/o timing parameters notes (1) , (2) symbol parameter t insu setup time for input or bidirectiona l pin using ioe input register with fast regional clock fed by fclk pin t inh hold time for input or bidirectional pin using ioe input register with fast regional clock fed by fclk pin t outco clock-to-output delay output or bi directional pin using ioe output register with fast regional clock fed by fclk pin t xz synchronous ioe output enab le register to output pin disable delay using fast regional clock fed by fclk pin t zx synchronous ioe output enab le register to output pin enable delay using fast regional clock fed by fclk pin notes to ta b l e 4 ? 5 2 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for column and row ioe pins. you should use the quartus ii software to verify the external timing for any pin. table 4?53. stratix regional clock exte rnal i/o timing parameters (part 1 of 2) notes (1) , (2) symbol parameter t insu setup time for input or bidirectional pin using ioe input register with regional clock fed by clk pin t inh hold time for input or bidirectional pin using ioe input register with regional clock fed by clk pin t outco clock-to-output delay output or bi directional pin using ioe output register with regional clock fed by clk pin t insupll setup time for input or bidirectional pin using ioe input register with regional clock fed by enhanced pll with default phase setting t inhpll hold time for input or bidirectional pin using ioe input register with regional clock fed by enhanced pll with default phase setting t outcopll clock-to-output delay output or bi directional pin using ioe output register with regional clock e nhanced pll with default phase setting altera corporation 4?35 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?54 shows the external i/o timing parameters when using global clock networks. t xzpll synchronous ioe output enable regist er to output pin disable delay using regional clock fed by enhanc ed pll with default phase setting t zxpll synchronous ioe output enable regi ster to output pin enable delay using regional clock fed by enhanc ed pll with default phase setting notes to ta b l e 4 ? 5 3 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for column and row ioe pins. you should use the quartus ii software to verify the external timing for any pin. table 4?54. stratix global clock ex ternal i/o timing parameters notes (1) , (2) symbol parameter t insu setup time for input or bidirectional pin using ioe input register with global clock fed by clk pin t inh hold time for input or bidirectional pin using ioe input register with global clock fed by clk pin t outco clock-to-output delay output or bi directional pin using ioe output register with global clock fed by clk pin t insupll setup time for input or bidirectional pin using ioe input register with global clock fed by enhanced pll with default phase setting t inhpll hold time for input or bidirectional pin using ioe input register with global clock fed by enhanced pll with default phase setting t outcopll clock-to-output delay output or bi directional pin using ioe output register with global clock enhanced pll with default phase setting t xzpll synchronous ioe output enab le register to output pin disable delay using global clock fed by enhanced pll with default phase setting t zxpll synchronous ioe output enab le register to output pin enable delay using global clock fed by enhanced pll with default phase setting notes to ta b l e 4 ? 5 4 : (1) these timing parameters are sample-tested only. (2) these timing parameters are for column and row ioe pins. you should use the quartus ii software to verify the external timing for any pin. table 4?53. stratix regional clock exte rnal i/o timing parameters (part 2 of 2) notes (1) , (2) symbol parameter 4?36 altera corporation stratix device handbook, volume 1 january 2006 timing model stratix external i/o timing these timing parameters are for both column ioe and row ioe pins. in ep1s30 devices and above, you can decrease the t su time by using the fpllclk , but may get positive hold time in ep1s60 and ep1s80 devices. you should use the quartus ii software to verify the external devices for any pin. tables 4?55 through 4?60 show the external timing parameters on column and row pins for ep1s10 devices. table 4?55. ep1s10 external i/o timing on column pins using fast regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmax min max t insu 2.238 2.325 2.668 na ns t inh 0.000 0.000 0.000 na ns t outco 2.240 4.549 2.240 4.836 2.240 5.218 na na ns t xz 2.180 4.423 2.180 4.704 2.180 5.094 na na ns t zx 2.180 4.423 2.180 4.704 2.180 5.094 na na ns table 4?56. ep1s10 external i/o timing on colu mn pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max t insu 1.992 2.054 2.359 na ns t inh 0.000 0.000 0.000 na ns t outco 2.395 4.795 2.395 5.107 2.395 5.527 na na ns t xz 2.335 4.669 2.335 4.975 2.335 5.403 na na ns t zx 2.335 4.669 2.335 4.975 2.335 5.403 na na ns t insupll 0.975 0.985 1.097 na ns t inhpll 0.000 0.000 0.000 na na ns t outcopll 1.262 2.636 1.262 2.680 1.262 2.769 na na ns t xzpll 1.202 2.510 1.202 2.548 1.202 2.645 na na ns t zxpll 1.202 2.510 1.202 2.548 1.202 2.645 na na ns altera corporation 4?37 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?57. ep1s10 external i/o timing on co lumn pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.647 1.692 1.940 na ns t inh 0.000 0.000 0.000 na ns t outco 2.619 5.184 2.619 5.515 2.619 5.999 na na ns t xz 2.559 5.058 2.559 5.383 2.559 5.875 na na ns t zx 2.559 5.058 2.559 5.383 2.559 5.875 na na ns t insupll 1.239 1.229 1.374 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.109 2.372 1.109 2.436 1.109 2.492 na na ns t xzpll 1.049 2.246 1.049 2.304 1.049 2.368 na na ns t zxpll 1.049 2.246 1.049 2.304 1.049 2.368 na na ns table 4?58. ep1s10 external i/o timing on ro w pin using fast regional clock network note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.212 2.403 2.759 na ns t inh 0.000 0.000 0.000 na ns t outco 2.391 4.838 2.391 5.159 2.391 5.569 na na ns t xz 2.418 4.892 2.418 5.215 2.418 5.637 na na ns t zx 2.418 4.892 2.418 5.215 2.418 5.637 na na ns 4?38 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?59. ep1s10 external i/o timing on ro w pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.161 2.336 2.685 na ns t inh 0.000 0.000 0.000 na ns t outco 2.434 4.889 2.434 5.226 2.434 5.643 na na ns t xz 2.461 4.493 2.461 5.282 2.461 5.711 na na ns t zx 2.461 4.493 2.461 5.282 2.461 5.711 na na ns t insupll 1.057 1.172 1.315 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.327 2.773 1.327 2.848 1.327 2.940 na na ns t xzpll 1.354 2.827 1.354 2.904 1.354 3.008 na na ns t zxpll 1.354 2.827 1.354 2.904 1.354 3.008 na na ns table 4?60. ep1s10 external i/o timing on row pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.787 1.944 2.232 na ns t inh 0.000 0.000 0.000 na ns t outco 2.647 5.263 2.647 5.618 2.647 6.069 na na ns t xz 2.674 5.317 2.674 5.674 2.674 6.164 na na ns t zx 2.674 5.317 2.674 5.674 2.674 6.164 na na ns t insupll 1.371 1.1472 1.654 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.144 2.459 1.144 2.548 1.144 2.601 na na ns t xzpll 1.171 2.513 1.171 2.604 1.171 2.669 na na ns t zxpll 1.171 2.513 1.171 2.604 1.171 2.669 na na ns note to tables 4?55 to 4?60 : (1) only ep1s25, ep1s30, and ep1s40 have speed grade of -8. altera corporation 4?39 january 2006 stratix device handbook, volume 1 dc & switching characteristics tables 4?61 through 4?66 show the external timing parameters on column and row pins for ep1s20 devices. table 4?61. ep1s20 external i/o timing on column pins using fast regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.065 2.245 2.576 na ns t inh 0.000 0.000 0.000 na ns t outco 2.283 4.622 2.283 4.916 2.283 5.310 na na ns t xz 2.223 4.496 2.223 4.784 2.223 5.186 na na ns t zx 2.223 4.496 2.223 4.784 2.223 5.186 na na ns table 4?62. ep1s20 external i/o timing on colu mn pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.541 1.680 1.931 na ns t inh 0.000 0.000 0.000 na ns t outco 2.597 5.146 2.597 5.481 2.597 5.955 na na ns t xz 2.537 5.020 2.537 5.349 2.537 5.831 na na ns t zx 2.537 5.020 2.537 5.349 2.537 5.831 na na ns t insupll 0.777 0.818 0.937 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.296 2.690 1.296 2.801 1.296 2.876 na na ns t xzpll 1.236 2.564 1.236 2.669 1.236 2.752 na na ns t zxpll 1.236 2.564 1.236 2.669 1.236 2.752 na na ns 4?40 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?63. ep1s20 external i/o timing on co lumn pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 1.351 1.479 1.699 na ns t inh 0.000 0.000 0.000 na ns t outco 2.732 5.380 2.732 5.728 2.732 6.240 na na ns t xz 2.672 5.254 2.672 5.596 2.672 6.116 na na ns t zx 2.672 5.254 2.672 5.596 2.672 6.116 na na ns t insupll 0.923 0.971 1.098 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.210 2.544 1.210 2.648 1.210 2.715 na na ns t xzpll 1.150 2.418 1.150 2.516 1.150 2.591 na na ns t zxpll 1.150 2.418 1.150 2.516 1.150 2.591 na na ns table 4?64. ep1s20 external i/o timing on row pins using fast regi onal clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.032 2.207 2.535 na ns t inh 0.000 0.000 0.000 na ns t outco 2.492 5.018 2.492 5.355 2.492 5.793 na na ns t xz 2.519 5.072 2.519 5.411 2.519 5.861 na na ns t zx 2.519 5.072 2.519 5.411 2.519 5.861 na na ns altera corporation 4?41 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?65. ep1s20 external i/o timing on ro w pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.815 1.967 2.258 na ns t inh 0.000 0.000 0.000 na ns t outco 2.633 5.235 2.663 5.595 2.663 6.070 na na ns t xz 2.660 5.289 2.660 5.651 2.660 6.138 na na ns t zx 2.660 5.289 2.660 5.651 2.660 6.138 na na ns t insupll 1.060 1.112 1.277 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.325 2.770 1.325 2.908 1.325 2.978 na na ns t xzpll 1.352 2.824 1.352 2.964 1.352 3.046 na na ns t zxpll 1.352 2.824 1.352 2.964 1.352 3.046 na na ns table 4?66. ep1s20 external i/o timing on row pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.742 1.887 2.170 na ns t inh 0.000 0.000 0.000 na ns t outco 2.674 5.308 2.674 5.675 2.674 6.158 na na ns t xz 2.701 5.362 2.701 5.731 2.701 6.226 na na ns t zx 2.701 5.362 2.701 5.731 2.701 6.226 na na ns t insupll 1.353 1.418 1.613 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.158 2.447 1.158 2.602 1.158 2.642 na na ns t xzpll 1.185 2.531 1.158 2.602 1.185 2.710 na na ns t zxpll 1.185 2.531 1.158 2.602 1.185 2.710 na na ns note to tables 4?61 to 4?66 : (1) only ep1s25, ep1s30, and ep1s40 have a speed grade of -8. 4?42 altera corporation stratix device handbook, volume 1 january 2006 timing model tables 4?67 through 4?72 show the external timing parameters on column and row pins for ep1s25 devices. table 4?67. ep1s25 external i/o timing on colu mn pins using fast regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.412 2.613 2.968 3.468 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.196 4.475 2.196 4.748 2.196 5.118 2.196 5.603 ns t xz 2.136 4.349 2.136 4.616 2.136 4.994 2.136 5.488 ns t zx 2.136 4.349 2.136 4.616 2.136 4.994 2.136 5.488 ns table 4?68. ep1s25 external i/o timing on co lumn pins using regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.535 1.661 1.877 2.125 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.739 5.396 2.739 5.746 2.739 6.262 2.739 6.946 ns t xz 2.679 5.270 2.679 5.614 2.679 6.138 2.679 6.831 ns t zx 2.679 5.270 2.679 5.614 2.679 6.138 2.679 6.831 ns t insupll 0.934 0.980 1.092 1.231 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.316 2.733 1.316 2.839 1.316 2.921 1.316 3.110 ns t xzpll 1.256 2.607 1.256 2.707 1.256 2.797 1.256 2.995 ns t zxpll 1.256 2.607 1.256 2.707 1.256 2.797 1.256 2.995 ns altera corporation 4?43 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?69. ep1s25 external i/o timing on co lumn pins using global clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 1.371 1.471 1.657 1.916 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.809 5.516 2.809 5.890 2.809 6.429 2.809 7.155 ns t xz 2.749 5.390 2.749 5.758 2.749 6.305 2.749 7.040 ns t zx 2.749 5.390 2.749 5.758 2.749 6.305 2.749 7.040 ns t insupll 1.271 1.327 1.491 1.677 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.124 2.396 1.124 2.492 1.124 2.522 1.124 2.602 ns t xzpll 1.064 2.270 1.064 2.360 1.064 2.398 1.064 2.487 ns t zxpll 1.064 2.270 1.064 2.360 1.064 2.398 1.064 2.487 ns table 4?70. ep1s25 external i/o timing on ro w pins using fast r egional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.429 2.631 2.990 3.503 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.376 4.821 2.376 5.131 2.376 5.538 2.376 6.063 ns t xz 2.403 4.875 2.403 5.187 2.403 5.606 2.403 6.145 ns t zx 2.403 4.875 2.403 5.187 2.403 5.606 2.403 6.145 ns 4?44 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?71. ep1s25 external i/o timing on row pins using regi onal clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.793 1.927 2.182 2.542 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.759 5.457 2.759 5.835 2.759 6.346 2.759 7.024 ns t xz 2.786 5.511 2.786 5.891 2.786 6.414 2.786 7.106 ns t zx 2.786 5.511 2.786 5.891 2.786 6.414 2.786 7.106 ns t insupll 1.169 1.221 1.373 1.600 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.375 2.861 1.375 2.999 1.375 3.082 1.375 3.174 ns t xzpll 1.402 2.915 1.402 3.055 1.402 3.150 1.402 3.256 ns t zxpll 1.402 2.915 1.402 3.055 1.402 3.150 1.402 3.256 ns table 4?72. ep1s25 external i/o timing on row pins using global clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.665 1.779 2.012 2.372 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.834 5.585 2.834 5.983 2.834 6.516 2.834 7.194 ns t xz 2.861 5.639 2.861 6.039 2.861 6.584 2.861 7.276 ns t zx 2.861 5.639 2.861 6.039 2.861 6.584 2.861 7.276 ns t insupll 1.538 1.606 1.816 2.121 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.164 2.492 1.164 2.614 1.164 2.639 1.164 2.653 ns t xzpll 1.191 2.546 1.191 2.670 1.191 2.707 1.191 2.735 ns t zxpll 1.191 2.546 1.191 2.670 1.191 2.707 1.191 2.735 ns altera corporation 4?45 january 2006 stratix device handbook, volume 1 dc & switching characteristics tables 4?73 through 4?78 show the external timing parameters on column and row pins for ep1s30 devices. table 4?73. ep1s30 external i/o timing on colu mn pins using fast regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.502 2.680 3.062 3.591 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.473 4.965 2.473 5.329 2.473 5.784 2.473 6.392 ns t xz 2.413 4.839 2.413 5.197 2.413 5.660 2.413 6.277 ns t zx 2.413 4.839 2.413 5.197 2.413 5.660 2.413 6.277 ns table 4?74. ep1s30 external i/o timing on colu mn pins using regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.286 2.426 2.769 3.249 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.641 5.225 2.641 5.629 2.641 6.130 2.641 6.796 ns t xz 2.581 5.099 2.581 5.497 2.581 6.006 2.581 6.681 ns t zx 2.581 5.099 2.581 5.497 2.581 6.006 2.581 6.681 ns t insupll 1.200 1.185 1.344 1.662 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.108 2.367 1.108 2.534 1.108 2.569 1.108 2.517 ns t xzpll 1.048 2.241 1.048 2.402 1.048 2.445 1.048 2.402 ns t zxpll 1.048 2.241 1.048 2.402 1.048 2.445 1.048 2.402 ns table 4?75. ep1s30 external i/o timing on column pins using global clock networks (part 1 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.935 2.029 2.310 2.709 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.814 5.532 2.814 5.980 2.814 6.536 2.814 7.274 ns 4?46 altera corporation stratix device handbook, volume 1 january 2006 timing model t xz 2.754 5.406 2.754 5.848 2.754 6.412 2.754 7.159 ns t zx 2.754 5.406 2.754 5.848 2.754 6.412 2.754 7.159 ns t insupll 1.265 1.236 1.403 1.756 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.068 2.302 1.068 2.483 1.068 2.510 1.068 2.423 ns t xzpll 1.008 2.176 1.008 2.351 1.008 2.386 1.008 2.308 ns t zxpll 1.008 2.176 1.008 2.351 1.008 2.386 1.008 2.308 ns table 4?76. ep1s30 external i/o timing on ro w pins using fast r egional clock networks parameters -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.616 2.808 3.223 3.797 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.542 5.114 2.542 5.502 2.542 5.965 2.542 6.581 ns t xz 2.569 5.168 2.569 5.558 2.569 6.033 2.569 6.663 ns t zx 2.569 5.168 2.569 5.558 2.569 6.033 2.569 6.663 ns table 4?75. ep1s30 external i/o timing on column pins using global clock networks (part 2 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax altera corporation 4?47 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?77. ep1s30 external i/o timing on row pins using regi onal clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.322 2.467 2.828 3.342 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.731 5.408 2.731 5.843 2.731 6.360 2.731 7.036 ns t xz 2.758 5.462 2.758 5.899 2.758 6.428 2.758 7.118 ns t zx 2.758 5.462 2.758 5.899 2.758 6.428 2.758 7.118 ns t insupll 1.291 1.283 1.469 1.832 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.192 2.539 1.192 2.737 1.192 2.786 1.192 2.742 ns t xzpll 1.219 2.539 1.219 2.793 1.219 2.854 1.219 2.824 ns t zxpll 1.219 2.539 1.219 2.793 1.219 2.854 1.219 2.824 ns table 4?78. ep1s30 external i/o timing on row pins using global clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 1.995 2.089 2.398 2.830 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.917 5.735 2.917 6.221 2.917 6.790 2.917 7.548 ns t xz 2.944 5.789 2.944 6.277 2.944 6.858 2.944 7.630 ns t zx 2.944 5.789 2.944 6.277 2.944 6.858 2.944 7.630 ns t insupll 1.337 1.312 1.508 1.902 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.164 2.493 1.164 2.708 1.164 2.747 1.164 2.672 ns t xzpll 1.191 2.547 1.191 2.764 1.191 2.815 1.191 2.754 ns t zxpll 1.191 2.547 1.191 2.764 1.191 2.815 1.191 2.754 ns 4?48 altera corporation stratix device handbook, volume 1 january 2006 timing model tables 4?79 through 4?84 show the external timing parameters on column and row pins for ep1s40 devices. table 4?79. ep1s40 external i/o timing on colu mn pins using fast regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.696 2.907 3.290 2.899 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.506 5.015 2.506 5.348 2.506 5.809 2.698 7.286 ns t xz 2.446 4.889 2.446 5.216 2.446 5.685 2.638 7.171 ns t zx 2.446 4.889 2.446 5.216 2.446 5.685 2.638 7.171 ns table 4?80. ep1s40 external i/o timing on co lumn pins using regional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.413 2.581 2.914 2.938 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.668 5.254 2.668 5.628 2.668 6.132 2.869 7.307 ns t xz 2.608 5.128 2.608 5.496 2.608 6.008 2.809 7.192 ns t zx 2.608 5.128 2.608 5.496 2.608 6.008 2.809 7.192 ns t insupll 1.385 1.376 1.609 1.837 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.117 2.382 1.117 2.552 1.117 2.504 1.117 2.542 ns t xzpll 1.057 2.256 1,057 2.420 1.057 2.380 1.057 2.427 ns t zxpll 1.057 2.256 1,057 2.420 1.057 2.380 1.057 2.427 ns altera corporation 4?49 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?81. ep1s40 external i/o timing on co lumn pins using global clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.126 2.268 2.558 2.930 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.856 5.585 2.856 5.987 2.856 6.541 2.847 7.253 ns t xz 2.796 5.459 2.796 5.855 2.796 6.417 2.787 7.138 ns t zx 2.796 5.459 2.796 5.855 2.796 6.417 2.787 7.138 ns t insupll 1.466 1.455 1.711 1.906 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.092 2.345 1.092 2.510 1.092 2.455 1.089 2.473 ns t xzpll 1.032 2.219 1.032 2.378 1.032 2.331 1.029 2.358 ns t zxpll 1.032 2.219 1.032 2.378 1.032 2.331 1.029 2.358 ns table 4?82. ep1s40 external i/o timing on ro w pins using fast r egional clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.472 2.685 3.083 3.056 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.631 5.258 2.631 5.625 2.631 6.105 2.745 7.324 ns t xz 2.658 5.312 2.658 5.681 2.658 6.173 2.772 7.406 ns t zx 2.658 5.312 2.658 5.681 2.658 6.173 2.772 7.406 ns 4?50 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?83. ep1s40 external i/o timing on row pins using regi onal clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.349 2.526 2.898 2.952 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.725 5.381 2.725 5.784 2.725 6.290 2.725 7.426 ns t xz 2.752 5.435 2.752 5.840 2.752 6.358 2.936 7.508 ns t zx 2.752 5.435 2.752 5.840 2.752 6.358 2.936 7.508 ns t insupll 1.328 1.322 1.605 1.883 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.169 2.502 1.169 2.698 1.169 2.650 1.169 2.691 ns t xzpll 1.196 2.556 1.196 2.754 1.196 2.718 1.196 2.773 ns t zxpll 1.196 2.556 1.196 2.754 1.196 2.718 1.196 2.773 ns table 4?84. ep1s40 external i/o timing on row pins using global clock networks parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.020 2.171 2.491 2.898 ns t inh 0.000 0.000 0.000 0.000 ns t outco 2.912 5.710 2.912 6.139 2.912 6.697 2.931 7.480 ns t xz 2.939 5.764 2.939 6.195 2.939 6.765 2.958 7.562 ns t zx 2.939 5.764 2.939 6.195 2.939 6.765 2.958 7.562 ns t insupll 1.370 1.368 1.654 1.881 ns t inhpll 0.000 0.000 0.000 0.000 ns t outcopll 1.144 2.460 1.144 2.652 1.144 2.601 1.170 2.693 ns t xzpll 1.171 2.514 1.171 2.708 1.171 2.669 1.197 2.775 ns t zxpll 1.171 2.514 1.171 2.708 1.171 2.669 1.197 2.775 ns altera corporation 4?51 january 2006 stratix device handbook, volume 1 dc & switching characteristics tables 4?85 through 4?90 show the external timing parameters on column and row pins for ep1s60 devices. table 4?85. ep1s60 external i/o timing on column pins using fast regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 3.029 3.277 3.733 na ns t inh 0.000 0.000 0.000 na ns t outco 2.446 4.871 2.446 5.215 2.446 5.685 na na ns t xz 2.386 4.745 2.386 5.083 2.386 5.561 na na ns t zx 2.386 4.745 2.386 5.083 2.386 5.561 na na ns table 4?86. ep1s60 external i/o timing on colu mn pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.491 2.691 3.060 na ns t inh 0.000 0.000 0.000 na ns t outco 2.767 5.409 2.767 5.801 2.767 6.358 na na ns t xz 2.707 5.283 2.707 5.669 2.707 6.234 na na ns t zx 2.707 5.283 2.707 5.669 2.707 6.234 na na ns t insupll 1.233 1.270 1.438 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.078 2.278 1.078 2.395 1.078 2.428 na na ns t xzpll 1.018 2.152 1.018 2.263 1.018 2.304 na na ns t zxpll 1.018 2.152 1.018 2.263 1.018 2.304 na na ns 4?52 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?87. ep1s60 external i/o timing on co lumn pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 2.000 2.152 2.441 na ns t inh 0.000 0.000 0.000 na ns t outco 3.051 5.900 3.051 6.340 3.051 6.977 na na ns t xz 2.991 5.774 2.991 6.208 2.991 6.853 na na ns t zx 2.991 5.774 2.991 6.208 2.991 6.853 na na ns t insupll 1.315 1.362 1.543 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.029 2.196 1.029 2.303 1.029 2.323 na na ns t xzpll 0.969 2.070 0.969 2.171 0.969 2.199 na na ns t zxpll 0.969 2.070 0.969 2.171 0.969 2.199 na na ns table 4?88. ep1s60 external i/o timing on row pins using fast regi onal clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max t insu 3.144 3.393 3.867 na ns t inh 0.000 0.000 0.000 na ns t outco 2.643 5.275 2.643 5.654 2.643 6.140 na na ns t xz 2.670 5.329 2.670 5.710 2.670 6.208 na na ns t zx 2.670 5.329 2.670 5.710 2.670 6.208 na na ns altera corporation 4?53 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?89. ep1s60 external i/o timing on ro w pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.775 2.990 3.407 na ns t inh 0.000 0.000 0.000 na ns t outco 2.867 5.644 2.867 6.057 2.867 6.600 na na ns t xz 2.894 5.698 2.894 6.113 2.894 6.668 na na ns t zx 2.894 5.698 2.894 6.113 2.894 6.668 na na ns t insupll 1.523 1.577 1.791 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.174 2.507 1.174 2.643 1.174 2.664 na na ns t xzpll 1.201 2.561 1.201 2.699 1.201 2.732 na na ns t zxpll 1.201 2.561 1.201 2.699 1.201 2.732 na na ns table 4?90. ep1s60 external i/o timing on row pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.232 2.393 2.721 na ns t inh 0.000 0.000 0.000 na ns t outco 3.182 6.187 3.182 6.654 3.182 7.286 na na ns t xz 3.209 6.241 3.209 6.710 3.209 7.354 na na ns t zx 3.209 6.241 3.209 6.710 3.209 7.354 na na ns t insupll 1.651 1.612 1.833 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.154 2.469 1.154 2.608 1.154 2.622 na na ns t xzpll 1.181 2.523 1.181 2.664 1.181 2.690 na na ns t zxpll 1.181 2.523 1.181 2.664 1.181 2.690 na na ns note to tables 4?85 to 4?90 : (1) only ep1s25, ep1s30, and ep1s40 devices have the -8 speed grade. 4?54 altera corporation stratix device handbook, volume 1 january 2006 timing model tables 4?91 through 4?96 show the external timing parameters on column and row pins for ep1s80 devices. table 4?91. ep1s80 external i/o timing on column pins using fast regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.328 2.528 2.900 na ns t inh 0.000 0.000 0.000 na ns t outco 2.422 4.830 2.422 5.169 2.422 5.633 na na ns t xz 2.362 4.704 2.362 5.037 2.362 5.509 na na ns t zx 2.362 4.704 2.362 5.037 2.362 5.509 na na ns table 4?92. ep1s80 external i/o timing on colu mn pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.760 1.912 2.194 na ns t inh 0.000 0.000 0.000 na ns t outco 2.761 5.398 2.761 5.785 2.761 6.339 na na ns t xz 2.701 5.272 2.701 5.653 2.701 6.215 na na ns t zx 2.701 5.272 2.701 5.653 2.701 6.215 na na ns t insupll 0.462 0.606 0.785 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.661 2.849 1.661 2.859 1.661 2.881 na na ns t xzpll 1.601 2.723 1.601 2.727 1.601 2.757 na na ns t zxpll 1.601 2.723 1.601 2.727 1.601 2.757 na na ns altera corporation 4?55 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?93. ep1s80 external i/o timing on co lumn pins using global clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 0.884 0.976 1.118 na ns t inh 0.000 0.000 0.000 na ns t outco 3.267 6.274 3.267 6.721 3.267 7.415 na na ns t xz 3.207 6.148 3.207 6.589 3.207 7.291 na na ns t zx 3.207 6.148 3.207 6.589 3.207 7.291 na na ns t insupll 0.506 0.656 0.838 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.635 2.805 1.635 2.809 1.635 2.828 na na ns t xzpll 1.575 2.679 1.575 2.677 1.575 2.704 na na ns t zxpll 1.575 2.679 1.575 2.677 1.575 2.704 na na ns table 4?94. ep1s80 external i/o timing on row pins using fast regi onal clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.792 2.993 3.386 na ns t inh 0.000 0.000 0.000 na ns t outco 2.619 5.235 2.619 5.609 2.619 6.086 na na ns t xz 2.646 5.289 2.646 5.665 2.646 6.154 na na ns t zx 2.646 5.289 2.646 5.665 2.646 6.154 na na ns 4?56 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?95. ep1s80 external i/o timing on ro w pins using regional clock networks note (1) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 2.295 2.454 2.767 na ns t inh 0.000 0.000 0.000 na ns t outco 2.917 5.732 2.917 6.148 2.917 6.705 na na ns t xz 2.944 5.786 2.944 6.204 2.944 6.773 na na ns t zx 2.944 5.786 2.944 6.204 2.944 6.773 na na ns t insupll 1.011 1.161 1.372 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.808 3.169 1.808 3.209 1.808 3.233 na na ns t xzpll 1.835 3.223 1.835 3.265 1.835 3.301 na na ns t zxpll 1.835 3.223 1.835 3.265 1.835 3.301 na na ns table 4?96. ep1s80 external i/o timing on rows using pin global clock networks note (1) symbol -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit minmaxminmaxminmaxminmax t insu 1.362 1.451 1.613 na ns t inh 0.000 0.000 0.000 na ns t outco 3.457 6.665 3.457 7.151 3.457 7.859 na na ns t xz 3.484 6.719 3.484 7.207 3.484 7.927 na na ns t zx 3.484 6.719 3.484 7.207 3.484 7.927 na na ns t insupll o.994 1.143 1.351 na ns t inhpll 0.000 0.000 0.000 na ns t outcopll 1.821 3.186 1.821 3.227 1.821 3.254 na na ns t xzpll 1.848 3.240 1.848 3.283 1.848 3.322 na na ns t zxpll 1.848 3.240 1.848 3.283 1.848 3.322 na na ns note to tables 4?91 to 4?96 : (1) only ep1s25, ep1s30, and ep1s40 devices have the -8 speed grade. altera corporation 4?57 january 2006 stratix device handbook, volume 1 dc & switching characteristics definition of i/o skew i/o skew is defined as the absolute va lue of the worst-case difference in clock-to-out times (t co ) between any two output registers fed by a common clock source. i/o bank skew is made up of the following components: clock network skews: this is the difference between the arrival times of the clock at the clock input port of the two ioe registers. package skews: this is the packag e trace length differences between (i/o pad a to i/o pin a) and (i/o pad b to i/o pin b). figure 4?5 shows an example of two ioe registers located in the same bank, being fed by a common clock source. the clock can come from an input pin or from a pll output. figure 4?5. i/o skew within an i/o bank common source of gclk fast edge slow edge i/o skew i/o bank i/o skew i/o pin a i/o pin b i/o pin a i/o pin b 4?58 altera corporation stratix device handbook, volume 1 january 2006 timing model figure 4?6 shows the case where four ioe registers are located in two different i/o banks. figure 4?6. i/o skew ac ross two i/o banks table 4?97 defines the timing parameters used to define the timing for horizontal i/o pins (side banks 1, 2, 5, 6) and vertical i/o pins (top and bottom banks 3, 4, 7, 8). the timing pa rameters define the skew within an i/o bank, across two neighboring i /o banks on the same side of the device, across all horizont al i/o banks, ac ross all vertical i/o banks, and the skew for the overall device. table 4?97. output pin timing skew definitions (part 1 of 2) symbol definition t sb_hio row i/o (hio) within one i/o bank (1) t sb_vio column i/o (vio) within one i/o bank (1) t ss_hio row i/o (hio) same side of the device, across two banks (2) t ss_vio column i/o (vio) same side of the device, across two banks (2) common source of gclk i/o bank i/o bank i/o pin a i/o pin b i/o pin c i/o pin d i/o pin a i/o pin b i/o pin c i/o pin d i/o pin skew across two banks altera corporation 4?59 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?98 shows the i/o skews when using the same global or regional clock to feed ioe registers in i/o banks around each device. these values can be used for calculating the timing budget on the output (write) side of a memory interface. these values already factor in the package skew. t lr_hio across all hio banks (1, 2, 5, 6); across four similar type i/o banks t tb_vio across all vio banks (3, 4, 7, 8); across four similar type i/o banks t overall output timing skew for all i/o pins on the device. notes to ta b l e 4 ? 9 7 : (1) see figure 4?5 on page 4?57 . (2) see figure 4?6 on page 4?58 . table 4?98. output skew for stratix by device density symbol skew (ps) (1) ep1s10 to ep1s30 ep1s40 ep1s60 & ep1s80 t sb_hio 90 290 500 t sb_vio 160 290 500 t ss_hio 90 460 600 t ss_vio 180 520 630 t lr_hio 150 490 600 t tb_vio 190 580 670 t overall 430 630 880 note to table 4?98 : (1) the skew numbers in table 4?98 account for worst case package skews. table 4?97. output pin timing skew definitions (part 2 of 2) symbol definition 4?60 altera corporation stratix device handbook, volume 1 january 2006 timing model skew on input pins table 4?99 shows the package skews that were considered to get the worst case i/o skew value. you can use these values, for example, when calculating the timing budget on the input (read) side of a memory interface. pll counter & clock network skews table 4?100 shows the clock skews between different clock outputs from the stratix device pll. i/o timing measurement methodology different i/o standards require different baseline loading techniques for reporting timing delays. altera char acterizes timing delays with the required termination and loading fo r each i/o standard. the timing information is specified from the inpu t clock pin up to the output pin of table 4?99. package skew on input pins package parameter worst-case skew (ps) pins in the same i/o bank 50 pins in top/bottom (vertical i/o) banks 50 pins in left/right side (horizontal i/o) banks 50 pins across the entire device 100 table 4?100. pll counter & clock network skews parameter worst-case skew (ps) clock skew between two external clock outputs driven by the same counter 100 clock skew between two external clock outputs driven by the different counters with the same settings 150 dual-purpose pll dedicated clock output used as i/o pin vs. regular i/o pin 270 (1) clock skew between any two outputs of the pll that drive global clock networks 150 note to table 4?100 : (1) the quartus ii software models 270 p s of delay on the pll dedicated clock output ( pll6_out[3..0]p/n and pll5_out[3..0]p/n ) pins both when used as clocks and when used as i/o pins. altera corporation 4?61 january 2006 stratix device handbook, volume 1 dc & switching characteristics the fpga device. the quartus ii softwa re calculates the i/o timing for each i/o standard with a default baseline loading as specified by the i/o standard. altera measures clock-to-output delays (t co ) at worst-case process, minimum voltage, and maximum temperature (pvt) for the 3.3-v lvttl i/o standard with 24 ma (default case ) current drive strength setting and fast slew rate setting. i/o adder de lays are measured to calculate the t co change at worst-case pvt across all i/o standards and current drive strength settings with the default loading shown in table 4?101 on page 4?62 . timing derating data for addi tional loading is taken for t co across worst-case pvt for all i/o standards and drive strength settings. these three pieces of data are used to predict the timing at the output pin. t co at pin = t outco max for 3.3-v 24 ma lvttl + i/o adder + output delay adder for loading simulation using ibis models is required to determine the delays on the pcb traces in addition to the output pin delay timing reported by the quartus ii software and the timing model in the device handbook. 1. simulate the output driver of choice into the generalized test setup using values from table 4?101 on page 4?62 . 2. record the time to vmeas. 3. simulate the output driver of ch oice into the actual pcb trace and load, using the appropriate ibis input buffer model or an equivalent capacitance value to represent the load. 4. record the time to vmeas. 5. compare the results of steps 2 and 4. the increase or decrease in delay should be added to or subt racted from the i/o standard output adder delays to yield the actual worst-case propagation delay (clock-to-input) of the pcb trace. the quartus ii software reports maxi mum timing with the conditions shown in table 4?101 on page 4?62 using the proceeding equation. figure 4?7 on page 4?62 shows the model of the ci rcuit that is represented by the quartus ii output timing. 4?62 altera corporation stratix device handbook, volume 1 january 2006 timing model figure 4?7. output delay timing reporting setup modeled by quartus ii notes to figure 4?7 : (1) output pin timing is reported at the ou tput pin of the fpga device. additional delays for loading and board trace delay need to be accounted for with ibis model simulations. (2) v ccint is 1.42-v unless otherwise specified. vccio gnd output gnd r t v tt r s c l output buffer single-ended outputs v meas gnd r up vccio r dn table 4?101. reporting methodology for maximum timi ng for single-ended output pins (part 1 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r up r dn r s r t v ccio (v) vtt (v) c l (pf) v meas 3.3-v lvttl ? ? 0 ? 2.950 2.95 10 1.500 2.5-v lvttl ? ? 0 ? 2.370 2.37 10 1.200 1.8-v lvttl ? ? 0 ? 1.650 1.65 10 0.880 1.5-v lvttl ? ? 0 ? 1.400 1.40 10 0.750 3.3-v lvcmos ? ? 0 ? 2.950 2.95 10 1.500 2.5-v lvcmos ? ? 0 ? 2.370 2.37 10 1.200 1.8-v lvcmos ? ? 0 ? 1.650 1.65 10 0.880 1.5-v lvcmos ? ? 0 ? 1.400 1.40 10 0.750 3.3-v gtl ? ? 0 25 2.950 1.14 30 0.740 2.5-v gtl ? ? 0 25 2.370 1.14 30 0.740 3.3-v gtl+ ? ? 0 25 2.950 1.35 30 0.880 2.5-v gtl+ ? ? 0 25 2.370 1.35 30 0.880 3.3-v sstl-3 class ii ? ? 25 25 2.950 1.25 30 1.250 altera corporation 4?63 january 2006 stratix device handbook, volume 1 dc & switching characteristics 3.3-v sstl-3 class i ? ? 25 50 2.950 1.250 30 1.250 2.5-v sstl-2 class ii ? ? 25 25 2.370 1.110 30 1.110 2.5-v sstl-2 class i ? ? 25 50 2.370 1.110 30 1.110 1.8-v sstl-18 class ii ? ? 25 25 1.650 0.760 30 0.760 1.8-v sstl-18 class i ? ? 25 50 1.650 0.760 30 0.760 1.5-v hstl class ii ? ? 0 25 1.400 0.700 20 0.680 1.5-v hstl class i ? ? 0 50 1.400 0.700 20 0.680 1.8-v hstl class ii ? ? 0 25 1.650 0.700 20 0.880 1.8-v hstl class i ? ? 0 50 1.650 0.700 20 0.880 3.3-v pci (4) ?/25 25/? 0 ? 2.950 2.950 10 0.841/1.814 3.3-v pci-x 1.0 (4) ?/25 25/? 0 ? 2.950 2.950 10 0.841/1.814 3.3-v compact pci (4) ?/25 25/? 0 ? 2.950 2.950 10 0.841/1.814 3.3-v agp 1x (4) ?/25 25/? 0 ? 2.950 2.950 10 0.841/1.814 3.3-v ctt ? ? 25 50 2.050 1.350 30 1.350 notes to table 4?101 : (1) input measurement point at internal node is 0.5 v ccint . (2) output measuring point for data is v meas . (3) input stimulus edge rate is 0 to v ccint in 0.5 ns (internal signal) from the driver preceding the io buffer. (4) the first value is for output rising edge and the second value is for output falling edge. the hyphen (-) indicates infinite resistance or disconnection. table 4?101. reporting methodology for maximum timi ng for single-ended output pins (part 2 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r up r dn r s r t v ccio (v) vtt (v) c l (pf) v meas 4?64 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?102 shows the reporting methodol ogy used by the quartus ii software for minimum timing information for output pins. table 4?102. reporting methodology for minimum timi ng for single-ended output pins (part 1 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r up r dn r s r t v ccio (v) vtt (v) c l (pf) v meas 3.3-v lvttl ? ? 0 ? 3.600 3.600 10 1.800 2.5-v lvttl ? ? 0 ? 2.630 2.630 10 1.200 1.8-v lvttl ? ? 0 ? 1.950 1.950 10 0.880 1.5-v lvttl ? ? 0 ? 1.600 1.600 10 0.750 3.3-v lvcmos ? ? 0 ? 3.600 3.600 10 1.800 2.5-v lvcmos ? ? 0 ? 2.630 2.630 10 1.200 1.8-v lvcmos ? ? 0 ? 1.950 1.950 10 0.880 1.5-v lvcmos ? ? 0 ? 1.600 1.600 10 0.750 3.3-v gtl ? ? 0 25 3.600 1.260 30 0.860 2.5-v gtl ? ? 0 25 2.630 1.260 30 0.860 3.3-v gtl+ ? ? 0 25 3.600 1.650 30 1.120 2.5-v gtl+ ? ? 0 25 2.630 1.650 30 1.120 3.3-v sstl-3 class ii ? ? 25 25 3.600 1.750 30 1.750 3.3-v sstl-3 class i ? ? 25 50 3.600 1.750 30 1.750 2.5-v sstl-2 class ii ? ? 25 25 2.630 1.390 30 1.390 2.5-v sstl-2 class i ? ? 25 50 2.630 1.390 30 1.390 1.8-v sstl-18 class ii ? ? 25 25 1.950 1.040 30 1.040 1.8-v sstl-18 class i ? ? 25 50 1.950 1.040 30 1.040 1.5-v hstl class ii ? ? 0 25 1.600 0.800 20 0.900 1.5-v hstl class i ? ? 0 50 1.600 0.800 20 0.900 1.8-v hstl class ii ? ? 0 25 1.950 0.900 20 1.000 1.8-v hstl class i ? ? 0 50 1.950 0.900 20 1.000 3.3-v pci (4) ?/25 25/? 0 ? 3.600 1.950 10 1.026/2.214 3.3-v pci-x 1.0 (4) ?/25 25/? 0 ? 3.600 1.950 10 1.026/2.214 3.3-v compact pci (4) ?/25 25/? 0 ? 3.600 3.600 10 1.026/2.214 3.3-v agp 1 (4) ?/25 25/? 0 ? 3.600 3.600 10 1.026/2.214 altera corporation 4?65 january 2006 stratix device handbook, volume 1 dc & switching characteristics figure 4?8 shows the measurement setup fo r output disable and output enable timing. the t chz stands for clock to high z time delay and is the same as t xz . the t clz stands for clock to low z (driving) time delay and is the same as t zx . figure 4?8. measurement setup for t xz and t zx 3.3-v ctt ? ? 25 50 3.600 1.650 30 1.650 notes to table 4?102 : (1) input measurement point at internal node is 0.5 v ccint . (2) output measuring point for data is v meas . when two values are given, the first is the measurement point on the rising edge and the other is for the falling edge. (3) input stimulus edge rate is 0 to v ccint in 0.5 ns (internal signal) from th e driver preceding the i/o buffer. (4) the first value is for the output rising edge and the se cond value is for the output falling edge. the hyphen (-) indicates infinite resistance or disconnection. table 4?102. reporting methodology for minimum timi ng for single-ended output pins (part 2 of 2) notes (1) , (2) , (3) i/o standard loading and termination measurement point r up r dn r s r t v ccio (v) vtt (v) c l (pf) v meas 200mv 200mv 200mv 200mv clk out out t chz t clz v t =1.5v c total =10pf r =50 4?66 altera corporation stratix device handbook, volume 1 january 2006 timing model external i/o delay parameters external i/o delay timing parameters for i/o standard input and output adders and programmable input and output delays are specified by speed grade independent of device dens ity. all of the timing parameters in this section apply to both flip-chip and wire-bond packages. tables 4?103 and 4?104 show the input adder delays associated with column and row i/o pins. if an i/o standard is selected other than 3.3-v lvttl or lvcmos, add the select ed delay to the external t insu and t insupll i/o parameters shown in tables 4?54 through 4?96 . table 4?103. stratix i/o standard colu mn pin input delay adders parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 0 0 0 0 ps 3.3-v lvttl 0 0 0 0 ps 2.5-v lvttl 19 19 22 26 ps 1.8-v lvttl 221 232 266 313 ps 1.5-v lvttl 352 369 425 500 ps gtl ?45 ?48 ?55 ?64 ps gtl+ ?75 ?79 ?91 ?107 ps 3.3-v pci 0 0 0 0 ps 3.3-v pci-x 1.0 0 0 0 0 ps compact pci 0 0 0 0 ps agp 1 0 0 0 0 ps agp 2 0 0 0 0 ps ctt 120 126 144 170 ps sstl-3 class i ?162 ?171 ?196 ?231 ps sstl-3 class ii ?162 ?171 ?196 ?231 ps sstl-2 class i ?202 ?213 ?244 ?287 ps sstl-2 class ii ?202 ?213 ?244 ?287 ps sstl-18 class i 78 81 94 110 ps sstl-18 class ii 78 81 94 110 ps 1.5-v hstl class i ?76 ?80 ?92 ?108 ps 1.5-v hstl class ii ?76 ?80 ?92 ?108 ps 1.8-v hstl class i ?52 ?55 ?63 ?74 ps 1.8-v hstl class ii ?52 ?55 ?63 ?74 ps altera corporation 4?67 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?104. stratix i/o standard row pin input delay adders parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 0 0 0 0 ps 3.3-v lvttl 0 0 0 0 ps 2.5-v lvttl 21 22 25 29 ps 1.8-v lvttl 181 190 218 257 ps 1.5-v lvttl 300 315 362 426 ps gtl+ ?152 ?160 ?184 ?216 ps ctt ?168 ?177 ?203 ?239 ps sstl-3 class i ?193 ?203 ?234 ?275 ps sstl-3 class ii ?193 ?203 ?234 ?275 ps sstl-2 class i ?262 ?276 ?317 ?373 ps sstl-2 class ii ?262 ?276 ?317 ?373 ps sstl-18 class i ?105 ?111 ?127 ?150 ps sstl-18 class ii 0 0 0 0 ps 1.5-v hstl class i ?151 ?159 ?183 ?215 ps 1.8-v hstl class i ?126 ?133 ?153 ?179 ps lvds ?149 ?157 ?180 ?212 ps lvpecl ?149 ?157 ?180 ?212 ps 3.3-v pcml ?65 ?69 ?79 ?93 ps hypertransport 77 ?81 ?93 ?110 ps 4?68 altera corporation stratix device handbook, volume 1 january 2006 timing model tables 4?105 through 4?108 show the output adder delays associated with column and row i/o pins for both fast and slow slew rates. if an i/o standard is selected other than 3. 3-v lvttl 4ma or lvcmos 2 ma with a fast slew rate, add the selected delay to the external t outco , t outcopll , t xz , t zx , t xzpll , and t zxpll i/o parameters shown in table 4?55 on page 4?36 through table 4?96 on page 4?56 . table 4?105. stratix i/o standar d output delay adders for fast slew rate on column pins (part 1 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 2 ma 1,895 1,990 1,990 1,990 ps 4 ma 956 1,004 1,004 1,004 ps 8 ma 189 198 198 198 ps 12 ma 0 0 0 0ps 24 ma ?157 ?165 ?165 ?165 ps 3.3-v lvttl 4 ma 1,895 1,990 1,990 1,990 ps 8 ma 1,347 1,414 1,414 1,414 ps 12 ma 636 668 668 668 ps 16 ma 561 589 589 589 ps 24 ma 0 0 0 0ps 2.5-v lvttl 2 ma 2,517 2,643 2,643 2,643 ps 8 ma 834 875 875 875 ps 12 ma 504 529 529 529 ps 16 ma 194 203 203 203 ps 1.8-v lvttl 2 ma 1,304 1,369 1,369 1,369 ps 8 ma 960 1,008 1,008 1,008 ps 12 ma 960 1,008 1,008 1,008 ps 1.5-v lvttl 2 ma 6,680 7,014 7,014 7,014 ps 4 ma 3,275 3,439 3,439 3,439 ps 8 ma 1,589 1,668 1,668 1,668 ps gtl 16 17 17 17 ps gtl+ 9 9 9 9ps 3.3-v pci 50 52 52 52 ps 3.3-v pci-x 1.0 50 52 52 52 ps compact pci 50 52 52 52 ps agp 1 50 52 52 52 ps agp 2 1,895 1,990 1,990 1,990 ps altera corporation 4?69 january 2006 stratix device handbook, volume 1 dc & switching characteristics ctt 973 1,021 1,021 1,021 ps sstl-3 class i 719 755 755 755 ps sstl-3 class ii 146 153 153 153 ps sstl-2 class i 678 712 712 712 ps sstl-2 class ii 223 234 234 234 ps sstl-18 class i 1,032 1,083 1,083 1,083 ps sstl-18 class ii 447 469 469 469 ps 1.5-v hstl class i 660 693 693 693 ps 1.5-v hstl class ii 537 564 564 564 ps 1.8-v hstl class i 304 319 319 319 ps 1.8-v hstl class ii 231 242 242 242 ps table 4?106. stratix i/o standar d output delay adders for fast slew rate on row pins (part 1 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 2 ma 1,518 1,594 1,594 1,594 ps 4 ma 746 783 783 783 ps 8 ma 96 100 100 100 ps 12 ma 0 0 0 0ps 3.3-v lvttl 4 ma 1,518 1,594 1,594 1,594 ps 8 ma 1,038 1,090 1,090 1,090 ps 12 ma 521 547 547 547 ps 16 ma 414 434 434 434 ps 24 ma 0 0 0 0ps 2.5-v lvttl 2 ma 2,032 2,133 2,133 2,133 ps 8 ma 699 734 734 734 ps 12 ma 374 392 392 392 ps 16 ma 165 173 173 173 ps 1.8-v lvttl 2 ma 3,714 3,899 3,899 3,899 ps 8 ma 1,055 1,107 1,107 1,107 ps 12 ma 830 871 871 871 ps table 4?105. stratix i/o standar d output delay adders for fast slew rate on column pins (part 2 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max 4?70 altera corporation stratix device handbook, volume 1 january 2006 timing model 1.5-v lvttl 2 ma 5,460 5,733 5,733 5,733 ps 4 ma 2,690 2,824 2,824 2,824 ps 8 ma 1,398 1,468 1,468 1,468 ps gtl+ 6 6 6 6ps ctt 845 887 887 887 ps sstl-3 class i 638 670 670 670 ps sstl-3 class ii 144 151 151 151 ps sstl-2 class i 604 634 634 634 ps sstl-2 class ii 211 221 221 221 ps sstl-18 class i 955 1,002 1,002 1,002 ps 1.5-v hstl class i 733 769 769 769 ps 1.8-v hstl class i 372 390 390 390 ps lvds ?196 ?206 ?206 ?206 ps lvpecl ?148 ?156 ?156 ?156 ps pcml ?147 ?155 ?155 ?155 ps hypertransport technology ?93 ?98 ?98 ?98 ps note to table 4?103 through 4?106 : (1) these parameters are only available on row i/o pins. table 4?107. stratix i/o standard output delay adders fo r slow slew rate on column pins (part 1 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 2 ma 1,822 1,913 1,913 1,913 ps 4 ma 684 718 718 718 ps 8 ma 233 245 245 245 ps 12 ma1111ps 24 ma ?608 ?638 ?638 ?638 ps table 4?106. stratix i/o standar d output delay adders for fast slew rate on row pins (part 2 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max altera corporation 4?71 january 2006 stratix device handbook, volume 1 dc & switching characteristics 3.3-v lvttl 4 ma 1,822 1,913 1,913 1,913 ps 8 ma 1,586 1,665 1,665 1,665 ps 12 ma 686 720 720 720 ps 16 ma 630 662 662 662 ps 24 ma0000ps 2.5-v lvttl 2 ma 2,925 3,071 3,071 3,071 ps 8 ma 1,496 1,571 1,571 1,571 ps 12 ma 937 984 984 984 ps 16 ma 1,003 1,053 1,053 1,053 ps 1.8-v lvttl 2 ma 7,101 7,456 7,456 7,456 ps 8 ma 3,620 3,801 3,801 3,801 ps 12 ma 3,109 3,265 3,265 3,265 ps 1.5-v lvttl 2 ma 10,941 11,488 11,488 11,488 ps 4 ma 7,431 7,803 7,803 7,803 ps 8 ma 5,990 6,290 6,290 6,290 ps gtl ?959 ?1,007 ?1,007 ?1,007 ps gtl+ ?438 ?460 ?460 ?460 ps 3.3-v pci 660 693 693 693 ps 3.3-v pci-x 1.0 660 693 693 693 ps compact pci 660 693 693 693 ps agp 1 660 693 693 693 ps agp 2 288 303 303 303 ps ctt 631 663 663 663 ps sstl-3 class i 301 316 316 316 ps sstl-3 class ii ?359 ?377 ?377 ?377 ps sstl-2 class i 523 549 549 549 ps sstl-2 class ii ?49 ?51 ?51 ?51 ps sstl-18 class i 2,315 2,431 2,431 2,431 ps sstl-18 class ii 723 759 759 759 ps 1.5-v hstl class i 1,687 1,771 1,771 1,771 ps 1.5-v hstl class ii 1,095 1,150 1,150 1,150 ps 1.8-v hstl class i 599 629 678 744 ps 1.8-v hstl class ii 87 102 102 102 ps table 4?107. stratix i/o standard output delay adders fo r slow slew rate on column pins (part 2 of 2) parameter -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max 4?72 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?108. stratix i/o standard output delay adders for slow slew rate on row pins i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max lvcmos 2 ma 1,571 1,650 1,650 1,650 ps 4 ma 594 624 624 624 ps 8 ma 208 218 218 218 ps 12 ma 0 0 0 0ps 3.3-v lvttl 4 ma 1,571 1,650 1,650 1,650 ps 8 ma 1,393 1,463 1,463 1,463 ps 12 ma 596 626 626 626 ps 16 ma 562 590 590 590 ps 2.5-v lvttl 2 ma 2,562 2,690 2,690 2,690 ps 8 ma 1,343 1,410 1,410 1,410 ps 12 ma 864 907 907 907 ps 16 ma 945 992 992 992 ps 1.8-v lvttl 2 ma 6,306 6,621 6,621 6,621 ps 8 ma 3,369 3,538 3,538 3,538 ps 12 ma 2,932 3,079 3,079 3,079 ps 1.5-v lvttl 2 ma 9,759 10,247 10,247 10,247 ps 4 ma 6,830 7,172 7,172 7,172 ps 8 ma 5,699 5,984 5,984 5,984 ps gtl+ ?333 ?350 ?350 ?350 ps ctt 591 621 621 621 ps sstl-3 class i 267 280 280 280 ps sstl-3 class ii ?346 ?363 ?363 ?363 ps sstl-2 class i 481 505 505 505 ps sstl-2 class ii ?58 ?61 ?61 ?61 ps sstl-18 class i 2,207 2,317 2,317 2,317 ps 1.5-v hstl class i 1,966 2,064 2,064? 2,064 ps 1.8-v hstl class i 1,208 1,268 1,460 1,720 ps altera corporation 4?73 january 2006 stratix device handbook, volume 1 dc & switching characteristics tables 4?109 and 4?110 show the adder delays for the column and row ioe programmable delays. these delays are controlled with the quartus ii software logic options listed in the parameter column. table 4?109. stratix ioe programmable delays on column pins note (1) parameter setting -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max decrease input delay to internal cells off 3,970 4,367 5,022 5,908 ps small 3,390 3,729 4,288 5,045 ps medium 2,810 3,091 3,554 4,181 ps large 224 235 270 318 ps on 224 235 270 318 ps decrease input delay to input register off 3,900 4,290 4,933 5,804 ps on 0000ps decrease input delay to output register off 1,240 1,364 1,568 1,845 ps on 0000ps increase delay to output pin off 0000ps on 397 417 417 417 ps increase delay to output enable pin off 0000ps on 338 372 427 503 ps increase output clock enable delay off 0000ps small 540 594 683 804 ps large 1,016 1,118 1,285 1,512 ps on 1,016 1,118 1,285 1,512 ps increase input clock enable delay off 0000ps small 540 594 683 804 ps large 1,016 1,118 1,285 1,512 ps on 1,016 1,118 1,285 1,512 ps increase output enable clock enable delay off 0000ps small 540 594 683 804 ps large 1,016 1,118 1,285 1,512 ps on 1,016 1,118 1,285 1,512 ps increase t zx delay to output pin off 0000ps on 2,199 2,309 2,309 2,309 ps 4?74 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?110. stratix ioe programmable delays on row pins note (1) parameter setting -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min max min max min max min max decrease input delay to internal cells off 3,970 4,367 5,022 5,908 ps small 3,390 3,729 4,288 5,045 ps medium 2,810 3,091 3,554 4,181 ps large 173 181 208 245 ps on 173 181 208 245 ps decrease input delay to input register off 3,900 4,290 4,933 5,804 ps on 0000ps decrease input delay to output register off 1,240 1,364 1,568 1,845 ps on 0000ps increase delay to output pin off 0000ps on 397 417 417 417 ps increase delay to output enable pin off 0000ps on 348 383 441 518 ps increase output clock enable delay off 0000ps small 180 198 227 267 ps large 260 286 328 386 ps on 260 286 328 386 ps increase input clock enable delay off 0000ps small 180 198 227 267 ps large 260 286 328 386 ps on 260 286 328 386 ps increase output enable clock enable delay off 0000ps small 540 594 683 804 ps large 1,016 1,118 1,285 1,512 ps on 1,016 1,118 1,285 1,512 ps increase t zx delay to output pin off 0000ps on 1,993 2,092 2,092 2,092 ps note to table 4?109 and ta b l e 4 ? 11 0 : (1) the delay chain delays vary for different device densitie s. these timing values only apply to ep1s30 and ep1s40 devices. reference the timing information report ed by the quartus ii software for other devices. altera corporation 4?75 january 2006 stratix device handbook, volume 1 dc & switching characteristics the scaling factors for col umn output pin timing in tables 4?111 to 4?113 are shown in units of time per pf un it of capacitance (ps/pf). add this delay to the t co or combinatorial timing path for output or bidirectional pins in addition to the i /o adder delays shown in tables 4?103 through 4?108 and the ioe programmable delays in tables 4?109 and 4?110 . table 4?111. output delay adder for loadi ng on lvttl/lvcmos output buffers note (1) conditions output pin adder delay (ps/pf) parameter value 3.3-v lvttl 2.5-v lvttl 1.8-v lvttl 1.5-v lvttl lvcmos drive strength 24ma 15 ? ? - 8 16ma 25 18 ? ? ? 12ma 30 25 25 ? 15 8ma 50 35 40 35 20 4ma 60 ? ? 80 30 2ma ? 75 120 160 60 note to ta b l e 4 ? 111 : (1) the timing information in this table is preliminary. table 4?112. output delay adder for loading on sstl/hstl output buffers note (1) conditions output pin adder delay (ps/pf) sstl-3 sstl-2 sstl-1.8 1.5-v hstl class i class ii 25 25 25 25 25 20 25 20 note to table 4?112 : (1) the timing information in this table is preliminary. table 4?113. output delay adder for loading on gtl+/gtl/ctt/pci output buffers note (1) conditions output pin adder delay (ps/pf) parameter value gtl+ gtl ctt pci agp vccio voltage level 3.3v 18 18 25 20 20 2.5v 15 18 - - - note to table 4?113 : (1) the timing information in this table is preliminary. 4?76 altera corporation stratix device handbook, volume 1 january 2006 timing model maximum input & output clock rates tables 4?114 through 4?119 show the maximum input clock rate for column and row pins in stratix devices. table 4?114. stratix maximum input clock rate for clk[7..4] & clk[15..12] pins in flip-chip packages (part 1 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 422 390 390 mhz 2.5 v 422 422 390 390 mhz 1.8 v 422 422 390 390 mhz 1.5 v 422 422 390 390 mhz lvcmos 422 422 390 390 mhz gtl 300 250 200 200 mhz gtl+ 300 250 200 200 mhz sstl-3 class i 400 350 300 300 mhz sstl-3 class ii 400 350 300 300 mhz sstl-2 class i 400 350 300 300 mhz sstl-2 class ii 400 350 300 300 mhz sstl-18 class i 400 350 300 300 mhz sstl-18 class ii 400 350 300 300 mhz 1.5-v hstl class i 400 350 300 300 mhz 1.5-v hstl class ii 400 350 300 300 mhz 1.8-v hstl class i 400 350 300 300 mhz 1.8-v hstl class ii 400 350 300 300 mhz 3.3-v pci 422 422 390 390 mhz 3.3-v pci-x 1.0 422 422 390 390 mhz compact pci 422 422 390 390 mhz agp 1 422 422 390 390 mhz agp 2 422 422 390 390 mhz ctt 300 250 200 200 mhz differential 1.5-v hstl c1 400 350 300 300 mhz lvpecl (1) 645 645 622 622 mhz pcml (1) 300 275 275 275 mhz altera corporation 4?77 january 2006 stratix device handbook, volume 1 dc & switching characteristics lv d s (1) 645 645 622 622 mhz hypertransport technology (1) 500 500 450 450 mhz table 4?115. stratix maximum input clock ra te for clk[0, 2, 9, 11] pins & fpll[10..7]clk pins in flip-chip packages i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 422 390 390 mhz 2.5 v 422 422 390 390 mhz 1.8 v 422 422 390 390 mhz 1.5 v 422 422 390 390 mhz lvcmos 422 422 390 390 mhz gtl+ 300 250 200 200 mhz sstl-3 class i 400 350 300 300 mhz sstl-3 class ii 400 350 300 300 mhz sstl-2 class i 400 350 300 300 mhz sstl-2 class ii 400 350 300 300 mhz sstl-18 class i 400 350 300 300 mhz sstl-18 class ii 400 350 300 300 mhz 1.5-v hstl class i 400 350 300 300 mhz 1.8-v hstl class i 400 350 300 300 mhz ctt 300 250 200 200 mhz differential 1.5-v hstl c1 400 350 300 300 mhz lvpecl (1) 717 717 640 640 mhz pcml (1) 400 375 350 350 mhz lv d s (1) 717 717 640 640 mhz hypertransport technology (1) 717 717 640 640 mhz table 4?114. stratix maximum input clock rate for clk[7..4] & clk[15..12] pins in flip-chip packages (part 2 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit 4?78 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?116. stratix maximum input clock rate for clk[1, 3, 8, 10] pins in flip-chip packages i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 422 390 390 mhz 2.5 v 422 422 390 390 mhz 1.8 v 422 422 390 390 mhz 1.5 v 422 422 390 390 mhz lvcmos 422 422 390 390 mhz gtl+ 300 250 200 200 mhz sstl-3 class i 400 350 300 300 mhz sstl-3 class ii 400 350 300 300 mhz sstl-2 class i 400 350 300 300 mhz sstl-2 class ii 400 350 300 300 mhz sstl-18 class i 400 350 300 300 mhz sstl-18 class ii 400 350 300 300 mhz 1.5-v hstl class i 400 350 300 300 mhz 1.8-v hstl class i 400 350 300 300 mhz ctt 300 250 200 200 mhz differential 1.5-v hstl c1 400 350 300 300 mhz lvpecl (1) 645 645 640 640 mhz pcml (1) 300 275 275 275 mhz lv d s (1) 645 645 640 640 mhz hypertransport technology (1) 500 500 450 450 mhz table 4?117. stratix maximum input clock rate for clk[7..4] & clk[15..12] pins in wire-bond packages (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 390 390 mhz 2.5 v 422 390 390 mhz 1.8 v 422 390 390 mhz 1.5 v 422 390 390 mhz lvcmos 422 390 390 mhz gtl 250 200 200 mhz altera corporation 4?79 january 2006 stratix device handbook, volume 1 dc & switching characteristics gtl+ 250 200 200 mhz sstl-3 class i 300 250 250 mhz sstl-3 class ii 300 250 250 mhz sstl-2 class i 300 250 250 mhz sstl-2 class ii 300 250 250 mhz sstl-18 class i 300 250 250 mhz sstl-18 class ii 300 250 250 mhz 1.5-v hstl class i 300 180 180 mhz 1.5-v hstl class ii 300 180 180 mhz 1.8-v hstl class i 300 180 180 mhz 1.8-v hstl class ii 300 180 180 mhz 3.3-v pci 422 390 390 mhz 3.3-v pci-x 1.0 422 390 390 mhz compact pci 422 390 390 mhz agp 1 422 390 390 mhz agp 2 422 390 390 mhz ctt 250 180 180 mhz differential 1.5-v hstl c1 300 180 180 mhz lvpecl (1) 422 400 400 mhz pcml (1) 215 200 200 mhz lv d s (1) 422 400 400 mhz hypertransport technology (1) 422 400 400 mhz table 4?118. stratix maximum input clock ra te for clk[0, 2, 9, 11] pins & fpll[10..7]clk pins in wire-bond packages (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 390 390 mhz 2.5 v 422 390 390 mhz 1.8 v 422 390 390 mhz 1.5 v 422 390 390 mhz table 4?117. stratix maximum input clock rate for clk[7..4] & clk[15..12] pins in wire-bond packages (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit 4?80 altera corporation stratix device handbook, volume 1 january 2006 timing model lvcmos 422 390 390 mhz gtl+ 250 200 200 mhz sstl-3 class i 350 300 300 mhz sstl-3 class ii 350 300 300 mhz sstl-2 class i 350 300 300 mhz sstl-2 class ii 350 300 300 mhz sstl-18 class i 350 300 300 mhz sstl-18 class ii 350 300 300 mhz 1.5-v hstl class i 350 300 300 mhz 1.8-v hstl class i 350 300 300 mhz ctt 250 200 200 mhz differential 1.5-v hstl c1 350 300 300 mhz lvpecl (1) 717 640 640 mhz pcml (1) 375 350 350 mhz lv d s (1) 717 640 640 mhz hypertransport technology (1) 717 640 640 mhz table 4?119. stratix maximum input clock ra te for clk[1, 3, 8, 10] pins in wire-bond packages (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 422 390 390 mhz 2.5 v 422 390 390 mhz 1.8 v 422 390 390 mhz 1.5 v 422 390 390 mhz lvcmos 422 390 390 mhz gtl+ 250 200 200 mhz sstl-3 class i 350 300 300 mhz sstl-3 class ii 350 300 300 mhz sstl-2 class i 350 300 300 mhz sstl-2 class ii 350 300 300 mhz table 4?118. stratix maximum input clock ra te for clk[0, 2, 9, 11] pins & fpll[10..7]clk pins in wire-bond packages (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit altera corporation 4?81 january 2006 stratix device handbook, volume 1 dc & switching characteristics tables 4?120 through 4?123 show the maximum output clock rate for column and row pins in stratix devices. sstl-18 class i 350 300 300 mhz sstl-18 class ii 350 300 300 mhz 1.5-v hstl class i 350 300 300 mhz 1.8-v hstl class i 350 300 300 mhz ctt 250 200 200 mhz differential 1.5-v hstl c1 350 300 300 mhz lvpecl (1) 645 622 622 mhz pcml (1) 275 275 275 mhz lv d s (1) 645 622 622 mhz hypertransport technology (1) 500 450 450 mhz note to ta b l e s 4 ? 11 4 through 4?119 : (1) these parameters are only available on row i/o pins. table 4?120. stratix maximum output clock rate for pll[5, 6, 11, 12] pins in flip-chip packages (part 1 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit lvttl 350 300 250 250 mhz 2.5 v 350 300 300 300 mhz 1.8 v 250 250 250 250 mhz 1.5 v 225 200 200 200 mhz lvcmos 350 300 250 250 mhz gtl 200 167 125 125 mhz gtl+ 200 167 125 125 mhz sstl-3 class i 200 167 167 133 mhz sstl-3 class ii 200 167 167 133 mhz sstl-2 class i (3) 200 200 167 167 mhz sstl-2 class i (4) 200 200 167 167 mhz sstl-2 class i (5) 150 134 134 134 mhz table 4?119. stratix maximum input clock ra te for clk[1, 3, 8, 10] pins in wire-bond packages (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit 4?82 altera corporation stratix device handbook, volume 1 january 2006 timing model sstl-2 class ii (3) 200 200 167 167 mhz sstl-2 class ii (4) 200 200 167 167 mhz sstl-2 class ii (5) 150 134 134 134 mhz sstl-18 class i 150 133 133 133 mhz sstl-18 class ii 150 133 133 133 mhz 1.5-v hstl class i 250 225 200 200 mhz 1.5-v hstl class ii 225 200 200 200 mhz 1.8-v hstl class i 250 225 200 200 mhz 1.8-v hstl class ii 225 200 200 200 mhz 3.3-v pci 350 300 250 250 mhz 3.3-v pci-x 1.0 350 300 250 250 mhz compact pci 350 300 250 250 mhz agp 1 350 300 250 250 mhz agp 2 350 300 250 250 mhz ctt 200 200 200 200 mhz differential 1.5-v hstl c1 225 200 200 200 mhz differential 1.8-v hstl class i 250 225 200 200 mhz differential 1.8-v hstl class ii 225 200 200 200 mhz differential sstl-2 (6) 200 200 167 167 mhz lvpecl (2) 500 500 500 500 mhz pcml (2) 350 350 350 350 mhz lv d s (2) 500 500 500 500 mhz hypertransport technology (2) 350 350 350 350 mhz table 4?120. stratix maximum output clock rate for pll[5, 6, 11, 12] pins in flip-chip packages (part 2 of 2) i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit altera corporation 4?83 january 2006 stratix device handbook, volume 1 dc & switching characteristics table 4?121. stratix maximum output cloc k rate (using i/o pins) for pll[1, 2, 3, 4] pins in flip-chip packages i/o standard -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit lvttl 400 350 300 300 mhz 2.5 v 400 350 300 300 mhz 1.8 v 400 350 300 300 mhz 1.5 v 350 300 300 300 mhz lvcmos 400 350 300 300 mhz gtl 200 167 125 125 mhz gtl+ 200 167 125 125 mhz sstl-3 class i 167 150 133 133 mhz sstl-3 class ii 167 150 133 133 mhz sstl-2 class i 150 133 133 133 mhz sstl-2 class ii 150 133 133 133 mhz sstl-18 class i 150 133 133 133 mhz sstl-18 class ii 150 133 133 133 mhz 1.5-v hstl class i 250 225 200 200 mhz 1.5-v hstl class ii 225 225 200 200 mhz 1.8-v hstl class i 250 225 200 200 mhz 1.8-v hstl class ii 225 225 200 200 mhz 3.3-v pci 250 225 200 200 mhz 3.3-v pci-x 1.0 225 225 200 200 mhz compact pci 400 350 300 300 mhz agp 1 400 350 300 300 mhz agp 2 400 350 300 300 mhz ctt 300 250 200 200 mhz lvpecl (2) 717 717 500 500 mhz pcml (2) 420 420 420 420 mhz lv d s (2) 717 717 500 500 mhz hypertransport technology (2) 420 420 420 420 mhz 4?84 altera corporation stratix device handbook, volume 1 january 2006 timing model table 4?122. stratix maximum output clock rate for pll[5, 6, 11, 12] pins in wire-bond packages (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 175 150 150 mhz 2.5 v 175 150 150 mhz 1.8 v 175 150 150 mhz 1.5 v 175 150 150 mhz lvcmos 175 150 150 mhz gtl 125 100 100 mhz gtl+ 125 100 100 mhz sstl-3 class i 110 90 90 mhz sstl-3 class ii 133 125 125 mhz sstl-2 class i 166 133 133 mhz sstl-2 class ii 133 100 100 mhz sstl-18 class i 110 100 100 mhz sstl-18 class ii 110 100 100 mhz 1.5-v hstl class i 167 167 167 mhz 1.5-v hstl class ii 167 133 133 mhz 1.8-v hstl class i 167 167 167 mhz 1.8-v hstl class ii 167 133 133 mhz 3.3-v pci 167 167 167 mhz 3.3-v pci-x 1.0 167 133 133 mhz compact pci 175 150 150 mhz agp 1 175 150 150 mhz agp 2 175 150 150 mhz ctt 125 100 100 mhz differential 1.5-v hstl c1 167 133 133 mhz differential 1.8-v hstl class i 167 167 167 mhz differential 1.8-v hstl class ii 167 133 133 mhz differential sstl-2 (1) 110 100 100 mhz lvpecl (2) 311 275 275 mhz pcml (2) 250 200 200 mhz altera corporation 4?85 january 2006 stratix device handbook, volume 1 dc & switching characteristics lv d s (2) 311 275 275 mhz hypertransport technology (2) 311 275 275 mhz table 4?123. stratix maximum output cloc k rate (using i/o pins) for pll[1, 2, 3, 4] pins in wire-bond packages (part 1 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit lvttl 200 175 175 mhz 2.5 v 200 175 175 mhz 1.8 v 200 175 175 mhz 1.5 v 200 175 175 mhz lvcmos 200 175 175 mhz gtl 125 100 100 mhz gtl+ 125 100 100 mhz sstl-3 class i 110 90 90 mhz sstl-3 class ii 150 133 133 mhz sstl-2 class i 90 80 80 mhz sstl-2 class ii 110 100 100 mhz sstl-18 class i 110 100 100 mhz sstl-18 class ii 110 100 100 mhz 1.5-v hstl class i 225 200 200 mhz 1.5-v hstl class ii 200 167 167 mhz 1.8-v hstl class i 225 200 200 mhz 1.8-v hstl class ii 200 167 167 mhz 3.3-v pci 200 175 175 mhz 3.3-v pci-x 1.0 200 175 175 mhz compact pci 200 175 175 mhz agp 1 200 175 175 mhz agp 2 200 175 175 mhz ctt 125 100 100 mhz lvpecl (2) 311 270 270 mhz pcml (2) 400 311 311 mhz table 4?122. stratix maximum output clock rate for pll[5, 6, 11, 12] pins in wire-bond packages (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit 4?86 altera corporation stratix device handbook, volume 1 january 2006 timing model lv d s (2) 400 311 311 mhz hypertransport technology (2) 420 400 400 mhz notes to tables 4?120 through 4?123 : (1) differential sstl-2 outputs are on ly available on column clock pins. (2) these parameters are only available on row i/o pins. (3) sstl-2 in maximum drive strength condition. see table 4?101 on page 4?62 for more information on exact loading conditions for each i/o standard. (4) sstl-2 in minimum drive strength with 10pf output load condition. (5) sstl-2 in minimum drive strength with > 10pf output load condition. (6) differential sstl-2 outputs are on ly supported on column clock pins. table 4?123. stratix maximum output cloc k rate (using i/o pins) for pll[1, 2, 3, 4] pins in wire-bond packages (part 2 of 2) i/o standard -6 speed grade -7 speed grade -8 speed grade unit altera corporation 4?87 january 2006 stratix device handbook, volume 1 dc & switching characteristics high-speed i/o specification table 4?124 provides high-spe ed timing specific ations definitions. table 4?124. high-speed timing s pecifications & terminology high-speed timing spec ification terminology t c high-speed receiver/transmitter input and output clock period. f hsclk high-speed receiver/transmitter input and output clock frequency. t rise low-to-high transmission time. t fall high-to-low transmission time. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ). f hsdr maximum lvds data transfer rate (f hsdr = 1/tui). channel-to-channel skew (tccs) the timing differenc e between the fastest and slowest output edges, including t co variation and clock skew. the clock is included in the tccs measurement. sampling window (sw) the period of time during which the data must be valid to be captured correctly. the setup and hold time s determine the ideal strobe position within the sampling window. sw = t sw (max) ? t sw (min). input jitter (peak-to-peak) peak-to-p eak input jitter on high-speed plls. output jitter (peak-to-peak) peak-to-p eak output jitter on high-speed plls. t duty duty cycle on high-speed transmitter output clock. t lock lock time for high-speed transmitter and receiver plls. j deserialization factor (width of internal data bus). w pll multiplication factor. 4?88 altera corporation stratix device handbook, volume 1 january 2006 high-speed i/o specification tables 4?125 and 4?126 show the high-speed i/o timing for stratix devices. table 4?125. high-speed i/o spec ifications for flip-chip packages (part 1 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max min typ max f hsclk (clock frequency) (lvds, lvpecl, hypertransport technology) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 210 10 210 10 156 10 115.5 mhz w = 2 (serdes bypass) 50 231 50 231 50 231 50 231 mhz w = 2 (serdes used) 150 420 150 420 150 312 150 231 mhz w = 1 (serdes bypass) 100 462 100 462 100 462 100 462 mhz w = 1 (serdes used) 300 717 300 717 300 624 300 462 mhz f hsdr device operation (lvds, lvpecl, hypertransport technology) j = 10 300 840 300 840 300 640 300 462 mbps j = 8 300 840 300 840 300 640 300 462 mbps j = 7 300 840 300 840 300 640 300 462 mbps j = 4 300 840 300 840 300 640 300 462 mbps j = 2 100 462 100 462 100 640 100 462 mbps j = 1 (lvds and lvpecl only) 100 462 100 462 100 640 100 462 mbps altera corporation 4?89 january 2006 stratix device handbook, volume 1 high-speed i/o specification f hsclk (clock frequency) (pcml) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 100 10 100 10 77.75 10 77.75 mhz w = 2 (serdes bypass) 50 200 50 200 50 150 50 150 mhz w = 2 (serdes used) 150 200 150 200 150 155.5 150 155.5 mhz w = 1 (serdes bypass) 100 250 100 250 100 200 100 200 mhz w = 1 (serdes used) 300 400 300 400 300 311 300 311 mhz f hsdr device operation (pcml) j = 10 300 400 300 400 300 311 300 311 mbps j = 8 300 400 300 400 300 311 300 311 mbps j = 7 300 400 300 400 300 311 300 311 mbps j = 4 300 400 300 400 300 311 300 311 mbps j = 2 100 400 100 400 100 300 100 300 mbps j = 1 100 250 100 250 100 200 100 200 mbps tccs all 200 200 300 300 ps table 4?125. high-speed i/o spec ifications for flip-chip packages (part 2 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max min typ max 4?90 altera corporation stratix device handbook, volume 1 january 2006 high-speed i/o specification sw pcml ( j = 4, 7, 8, 10) 750 750 800 800 ps pcml ( j = 2) 900 900 1,200 1,200 ps pcml ( j = 1) 1,500 1,500 1,700 1,700 ps lvds and lvpecl ( j =1) 500 500 550 550 ps lv d s, lvpecl, hypertransport technology ( j = 2 through 10) 440 440 500 500 ps input jitter tolerance (peak-to-peak) all 250 250 250 250 ps output jitter (peak-to-peak) all 160 160 200 200 ps output t rise lvds 80 110 120 80 110 120 80 110 120 80 110 120 ps hypertransport technology 110 170 200 110 170 200 120 170 200 120 170 200 ps lvpecl 90 130 150 90 130 150 100 135 150 100 135 150 ps pcml 80 110 135 80 110 135 80 110 135 80 110 135 ps output t fall lvds 80 110 120 80 110 120 80 110 120 80 110 120 ps hypertransport technology 110 170 200 110 170 200 110 170 200 110 170 200 ps lvpecl 90 130 160 90 130 160 100 135 160 100 135 160 ps pcml 105 140 175 105 140 175 110 145 175 110 145 175 ps table 4?125. high-speed i/o spec ifications for flip-chip packages (part 3 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max min typ max altera corporation 4?91 january 2006 stratix device handbook, volume 1 high-speed i/o specification t duty lv d s ( j =2 through 10) 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % lv d s ( j =1) and lvpecl, pcml, hypertransport technology 45 50 55 45 50 55 45 50 55 45 50 55 % t lock all 100 100 100 100 s notes to table 4?125 : (1) when j = 4, 7, 8, and 10, the serdes block is used. (2) when j = 2 or j = 1, the serdes is bypassed. table 4?125. high-speed i/o spec ifications for flip-chip packages (part 4 of 4) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max min typ max 4?92 altera corporation stratix device handbook, volume 1 january 2006 high-speed i/o specification table 4?126. high-speed i/o s pecifications for wire-b ond packages (part 1 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max f hsclk (clock frequency) (lvds,lvpecl, hypertransport technology) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 156 10 115.5 10 115.5 mhz w = 2 (serdes bypass) 50 231 50 231 50 231 mhz w = 2 (serdes used) 150 312 150 231 150 231 mhz w = 1 (serdes bypass) 100 311 100 270 100 270 mhz w = 1 (serdes used) 300 624 300 462 300 462 mhz f hsdr device operation, (lvds,lvpecl, hypertransport technology) j = 10 300 624 300 462 300 462 mbps j = 8 300 624 300 462 300 462 mbps j = 7 300 624 300 462 300 462 mbps j = 4 300 624 300 462 300 462 mbps j = 2 100 462 100 462 100 462 mbps j = 1 (lvds and lvpecl only) 100 311 100 270 100 270 mbps f hsclk (clock frequency) (pcml) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 77.75 mhz w = 2 (serdes bypass) 50 150 50 77.5 50 77.5 mhz w = 2 (serdes used) 150 155.5 mhz w = 1 (serdes bypass) 100 200 100 155 100 155 mhz w = 1 (serdes used) 300 311 mhz device operation, f hsdr (pcml) j = 10 300 311 mbps j = 8 300 311 mbps j = 7 300 311 mbps j = 4 300 311 mbps j = 2 100 300 100 155 100 155 mbps j = 1 100 200 100 155 100 155 mbps tccs all 400 400 400 ps altera corporation 4?93 january 2006 stratix device handbook, volume 1 high-speed i/o specification sw pcml (j = 4, 7, 8, 10) only 800 800 800 ps pcml (j = 2) only 1,200 1,200 1,200 ps pcml (j = 1) only 1,700 1,700 1,700 ps lvds and lvpecl (j = 1) only 550 550 550 ps lvds, lvpecl, hypertransport technology (j = 2 through 10) only 500 500 500 ps input jitter tolerance (peak-to-peak) all 250 250 250 ps output jitter (peak-to- peak) all 200 200 200 ps output t rise lvds 80 110 120 80 110 120 80 110 120 ps hypertransport technology 120 170 200 120 170 200 120 170 200 ps lvpecl 100 135 150 100 135 150 100 135 150 ps pcml 80 110 135 80 110 135 80 110 135 ps output t fall lvds 80 110 120 80 110 120 80 110 120 ps hypertransport 110 170 200 110 170 200 110 170 200 ps lvpecl 100 135 160 100 135 160 100 135 160 ps pcml 110 145 175 110 145 175 110 145 175 ps t duty lvds (j = 2 through10) only 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % lvds (j =1) and lvpecl, pcml, hypertransport technology 45 50 55 45 50 55 45 50 55 % t lock all 100 100 100 s table 4?126. high-speed i/o s pecifications for wire-b ond packages (part 2 of 2) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max 4?94 altera corporation stratix device handbook, volume 1 january 2006 pll specifications pll specifications tables 4?127 through 4?129 describe the stratix device enhanced pll specifications. table 4?127. enhanced pll specifications for -5 speed grades (part 1 of 2) symbol parameter min typ max unit f in input clock frequency 3 (1) , (2) 684 mhz f inpfd input frequency to pfd 3 420 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (3) ps t einjitter external feedback clock period jitter 200 (3) ps t fcomp external feedback clock compensation time (4) 6ns f out output frequency for internal global or regional clock 0.3 500 mhz f out_ext output frequency for external clock (3) 0.3 526 mhz t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (6) 100 ps for >200-mhz outclk 20 mui for <200-mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk t scanclk scanclk frequency (5) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) 100 s t lock time required to lock from end of device configuration 10 400 s f vco pll internal vco operating range 300 800 (8) mhz t lskew clock skew between two external clock outputs driven by the same counter 50 ps altera corporation 4?95 january 2006 stratix device handbook, volume 1 dc & switching characteristics t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (10) 0.4 0.5 0.6 % t areset minimum pulse width on areset signal 10 ns t areset_recon fig minimum pulse width on the areset signal when using pll reconfiguration. reset the pll after scandataout goes high. 500 ns table 4?128. enhanced pll specifications for -6 speed grades (part 1 of 2) symbol parameter min typ max unit f in input clock frequency 3 (1) , (2) 650 mhz f inpfd input frequency to pfd 3 420 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (3) ps t einjitter external feedback clock period jitter 200 (3) ps t fcomp external feedback clock compensation time (4) 6ns f out output frequency for internal global or regional clock 0.3 450 mhz f out_ext output frequency for external clock (3) 0.3 500 mhz t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (6) 100 ps for >200-mhz outclk 20 mui for <200-mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk table 4?127. enhanced pll specifications for -5 speed grades (part 2 of 2) symbol parameter min typ max unit 4?96 altera corporation stratix device handbook, volume 1 january 2006 pll specifications t scanclk scanclk frequency (5) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) (11) (9) 100 s t lock time required to lock from end of device configuration (11) 10 400 s f vco pll internal vco operating range 300 800 (8) mhz t lskew clock skew between two external clock outputs driven by the same counter 50 ps t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (10) 0.4 0.5 0.6 % t areset minimum pulse width on areset signal 10 ns table 4?129. enhanced pll specifications for -7 speed grade (part 1 of 2) symbol parameter min typ max unit f in input clock frequency 3 (1) , (2) 565 mhz f inpfd input frequency to pfd 3 420 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (3) ps t einjitter external feedback clock period jitter 200 (3) ps t fcomp external feedback clock compensation time (4) 6ns f out output frequency for internal global or regional clock 0.3 420 mhz f out_ext output frequency for external clock (3) 0.3 434 mhz table 4?128. enhanced pll specifications for -6 speed grades (part 2 of 2) symbol parameter min typ max unit altera corporation 4?97 january 2006 stratix device handbook, volume 1 dc & switching characteristics t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (6) 100 ps for >200-mhz outclk 20 mui for <200-mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk t scanclk scanclk frequency (5) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) (11) (9) 100 s t lock time required to lock from end of device configuration (11) 10 400 s f vco pll internal vco operating range 300 600 (8) mhz t lskew clock skew between two external clock outputs driven by the same counter 50 ps t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (10) 0.5 0.6 % t areset minimum pulse width on areset signal 10 ns table 4?130. enhanced pll specifications for -8 speed grade (part 1 of 3) symbol parameter min typ max unit f in input clock frequency 3 (1) , (2) 480 mhz f inpfd input frequency to pfd 3 420 mhz f induty input clock duty cycle 40 60 % f einduty external feedback clock input duty cycle 40 60 % t injitter input clock period jitter 200 (3) ps table 4?129. enhanced pll specifications for -7 speed grade (part 2 of 2) symbol parameter min typ max unit 4?98 altera corporation stratix device handbook, volume 1 january 2006 pll specifications t einjitter external feedback clock period jitter 200 (3) ps t fcomp external feedback clock compensation time (4) 6ns f out output frequency for internal global or regional clock 0.3 357 mhz f out_ext output frequency for external clock (3) 0.3 369 mhz t outduty duty cycle for external clock output (when set to 50 % ) 45 55 % t jitter period jitter for external clock output (6) 100 ps for >200-mhz outclk 20 mui for <200-mhz outclk ps or mui t config5,6 time required to reconfigure the scan chains for plls 5 and 6 289/f scanclk t config11,12 time required to reconfigure the scan chains for plls 11 and 12 193/f scanclk t scanclk scanclk frequency (5) 22 mhz t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) (11) (9) 100 s t lock time required to lock from end of device configuration (11) 10 400 s f vco pll internal vco operating range 300 600 (8) mhz table 4?130. enhanced pll specifications for -8 speed grade (part 2 of 3) symbol parameter min typ max unit altera corporation 4?99 january 2006 stratix device handbook, volume 1 dc & switching characteristics t lskew clock skew between two external clock outputs driven by the same counter 50 ps t skew clock skew between two external clock outputs driven by the different counters with the same settings 75 ps f ss spread spectrum modulation frequency 30 150 khz % spread percentage spread for spread spectrum frequency (10) 0.5 0.6 % t areset minimum pulse width on areset signal 10 ns notes to tables 4?127 through 4?130 : (1) the minimum input clock frequency to the pfd (f in / n ) must be at least 3 mhz for st ratix device enhanced plls. (2) use this equation (f out = f in * ml ( n post-scale counter)) in co njunction with the specified f inpfd and f vco ranges to determine the al lowed pll settings. (3) see ?maximum input & output clock rates? on page 4?76 . (4) t fcomp can also equal 50 % of the input clock period multiplied by the pre-scale divider n (whichever is less). (5) this parameter is timing analyzed by the quartus ii software because the scanclk and scandata ports can be driven by the logic array. (6) actual jitter performance may vary based on the system configuration. (7) total required time to reconfigure and lock is equal to t dlock + t config . if only post-scale co unters and delays are changed, then t dlock is equal to 0. (8) when using the spread-spectrum feature, the min imum vco frequency is 500 mhz. the maximum vco frequency is determined by the speed grade selected. (9) lock time is a function of pll configuration and may be significantly faster dependin g on bandwidth settings or feedback counter change increment. (10) exact, user-controllable valu e depends on the pll settings. (11) the lock circuit on stratix plls does not work for industrial devices below -20c unless the pfd frequency > 200 mhz. see the stratix fpga errata sheet for more information on the pll. table 4?130. enhanced pll specifications for -8 speed grade (part 3 of 3) symbol parameter min typ max unit 4?100 altera corporation stratix device handbook, volume 1 january 2006 pll specifications tables 4?131 through 4?133 describe the stratix device fast pll specifications. table 4?131. fast pll specifications for -5 & -6 speed grade devices symbol parameter min max unit f in clkin frequency (1) , (2) , (3) 10 717 mhz f inpfd input frequency to pfd 10 500 mhz f out output frequency for internal global or regional clock (3) 9.375 420 mhz f out_diffio output frequency for external clock driven out on a differential i/o data channel (2) (5) (5) f vco vco operating frequency 300 1,000 mhz t induty clkin duty cycle 40 60 % t injitter period jitter for clkin pin 200 ps t duty duty cycle for dffio 1 clkout pin (6) 45 55 % t jitter period jitter for diffio clock out (6) (5) ps t lock time required for pll to acquire lock 10 100 s m multiplication factors for m counter (6) 1 32 integer l 0, l 1, g 0 multiplication factors for l 0, l 1, and g 0 counter (7) , (8) 1 32 integer t areset minimum pulse width on areset signal 10 ns table 4?132. fast pll specifications for -7 speed grades (part 1 of 2) symbol parameter min max unit f in clkin frequency (1) , (3) 10 640 mhz f inpfd input frequency to pfd 10 500 mhz f out output frequency for internal global or regional clock (4) 9.375 420 mhz f out_diffio output frequency for external clock driven out on a differential i/o data channel (5) (5) mhz f vco vco operating frequency 300 700 mhz t induty clkin duty cycle 40 60 % t injitter period jitter for clkin pin 200 ps t duty duty cycle for dffio 1 clkout pin (6) 45 55 % altera corporation 4?101 january 2006 stratix device handbook, volume 1 dc & switching characteristics t jitter period jitter for diffio clock out (6) (5) ps t lock time required for pll to acquire lock 10 100 s m multiplication factors for m counter (7) 1 32 integer l 0, l 1, g 0 multiplication factors for l 0, l 1, and g 0 counter (7) , (8) 1 32 integer t areset minimum pulse width on areset signal 10 ns table 4?133. fast pll specifications for -8 speed grades (part 1 of 2) symbol parameter min max unit f in clkin frequency (1) , (3) 10 460 mhz f inpfd input frequency to pfd 10 500 mhz f out output frequency for internal global or regional clock (4) 9.375 420 mhz f out_diffio output frequency for external clock driven out on a differential i/o data channel (5) (5) mhz f vco vco operating frequency 300 700 mhz t induty clkin duty cycle 40 60 % t injitter period jitter for clkin pin 200 ps t duty duty cycle for dffio 1 clkout pin (6) 45 55 % t jitter period jitter for diffio clock out (6) (5) ps t lock time required for pll to acquire lock 10 100 s m multiplication factors for m counter (7) 1 32 integer l 0, l 1, g 0 multiplication factors for l 0, l 1, and g 0 counter (7) , (8) 1 32 integer table 4?132. fast pll specifications for -7 speed grades (part 2 of 2) symbol parameter min max unit 4?102 altera corporation stratix device handbook, volume 1 january 2006 dll specifications dll specifications table 4?134 reports the jitter for the dll in the dqs phase shift reference circuit. f for more information on dll jitter, see the ddr sram section in the stratix architecture chapter of the stratix device handbook, volume 1 . table 4?135 lists the stratix dll low frequency limit for full phase shift across all pvt conditions. the stra tix dll can be used below these frequencies, but it will not achieve the full phase shift requested across all t areset minimum pulse width on areset signal 10 ns notes to tables 4?131 through 4?133 : (1) see ?maximum input & output clock rates? on page 4?76 . (2) plls 7, 8, 9, and 10 in the ep1s80 device support up to 717-mhz input and output. (3) use this equation (f out = f in * ml ( n post-scale counter)) in conjunction with the specified f inpfd and f vco ranges to determine the allowed pll settings. (4) when using the serdes, high-speed differential i/o mode supports a maximum output frequency of 210 mhz to the global or regional clocks (that is, the maximum data rate 840 mbps divided by the smallest serdes j factor of 4). (5) refer to the section ?high-speed i/o specification? on page 4?87 for more information. (6) this parameter is for high-spe ed differential i/o mode only. (7) these counters have a maximum of 32 if programmed for 50/50 duty cycle. otherwise, they have a maximum of 16. (8) high-speed differential i/o mode supports w = 1 to 16 and j = 4, 7, 8, or 10. table 4?133. fast pll specifications for -8 speed grades (part 2 of 2) symbol parameter min max unit table 4?134. dll jitter for dqs ph ase shift reference circuit frequency (mhz) dll jitter (ps) 197 to 200 100 160 to 196 300 100 to 159 500 altera corporation 4?103 january 2006 stratix device handbook, volume 1 dc & switching characteristics process and operating conditions. run the timing analyzer in the quartus ii software at the fast and slow operating conditions to see the phase shift range that is achieved below these frequencies. table 4?135. stratix dll low frequen cy limit for full phase shift phase shift minimum frequency for full phase shift unit 72 119 mhz 90 149 mhz 4?104 altera corporation stratix device handbook, volume 1 january 2006 dll specifications altera corporation 5?1 september 2004 5. reference & ordering information software stratix ? devices are supported by the altera ? quartus ? ii design software, which provides a comprehe nsive environment for system-on-a- programmable-chip (sopc) design. the quartus ii software includes hdl and schematic design entry, comp ilation and logic synthesis, full simulation and advanced ti ming analysis, signaltap ? ii logic analyzer, and device configuration. see the design software selector guide for more details on the quartus ii software features. the quartus ii software supports the windows xp/2000/nt/98, sun solaris, linux red hat v7.1 and hp-ux operating systems. it also supports seamless integr ation with industry-leading eda tools through the nativelink ? interface. device pin-outs stratix device pin-outs can be found on the altera web site (www.altera.com). ordering information figure 5?1 describes the ordering codes for stratix devices. for more information on a specif ic package, see the package information for stratix devices chapter. s51005-2.1 5?2 altera corporation stratix device handbook, volume 1 september 2004 ordering information figure 5?1. stratix device pa ckaging ordering information device type package type 5, 6, or 7, with 5 bein g the fastest number of pins for a particular bga or fineline bga packa g e es: b: f: ball- g rid array (bga) fineline bga ep1s: stratix 10 20 25 30 40 60 80 c: i: commercial temperature (t j = 0 ? c to 85 ? c) industrial temperature (t j = -40 ? c to 100 ? c) optional suffix family signature operating temperature speed grade pin count en g ineerin g sample 7 ep1s 8 0c 150 8 fes indicates specific device options or shipment method. altera corporation index?1 index a accumulator 2?63 adder/output blocks 2?61 adder/subtractor 2?63 accumulator 2?63 agp 1x specifications 4?13 agp 2x specifications 4?13 architecture 2?1 36 x 36 multiply mode 2?66 addnsub signal 2?8 block diagram 2?2 bus hold 2?121 byte alignment 2?140 carry-select chain 2?11 clear & preset logic control 2?13 combined resources 2?78 dedicated circuitry 2?137 device resources 2?3 device routing scheme 2?20 digital signal pr ocessing block 2?52 direct link connection 2?5 dynamic arithmetic mode 2?10 in le 2?11 four-multipliers adder mode 2?68 functional description 2?1 lab interconnects 2?4 logic array blocks 2?3 structure 2?4 le operating modes 2?8 logic elements 2?6 modes of operation 2?64 multiplier size & configurations per dsp block 2?70 multiply-accumulator mode 2?67 multitrack interconnect 2?14 normal mode 2?9 in le 2?9 open-drain output 2?120 power sequencing & hot socketing 2?140 programmable drive strength 2?119 programmable pull-up resistor 2?122 simple multiplier mode 2?64 single-port mode 2?51 slew-rate control 2?120 two-multipliers adder mode 2?67 adder mode implementing complex multiply 2?68 c class i specifications 4?11 , 4?12 class ii specifications 4?11 , 4?12 , 4?13 clocks clock feedback 2?96 clock multiplication & division 2?88 , 2?101 clock switchover 2?88 delay 2?97 ep1s10, ep1s20 & ep1s25 device i/o clock groups 2?80 ep1s25, ep1s20 & ep1s 10 device fast clock pin connections to fast regional clocks 2?77 ep1s30 device fast re gional clock pin con- nections to fast regional clocks 2?78 ep1s30, ep1s40, ep1s60, ep1s80 device i/o clock groups 2?81 external clock inputs 2?102 outputs 2?92 , 2?103 outputs for enhanced plls 11 & 12 2?95 outputs for plls 5 & 6 2?93 fast regional clock external i/o timing parameters 4?34 fast regional clock network 2?76 index?2 altera corporation stratix device handbook, volume 1 global & hierarchical clocking 2?73 global & regional clock connections from side pins & fast pll outputs 2?85 from top clock pins & enhanced pll outputs 2?86 global clock external i/o timing parameters 4?35 global clock network 2?74 global clocking 2?75 independent clock mode 2?44 input/output clock mode 2?46 simple dual-port mode 2?48 true dual-port mode 2?47 maximum input & output clock rates 4?76 maximum input clock rate for clk (0, 2, 9, 11) pins in flip-chip packages 4?77 wire-bond packages 4?79 (1, 3, 8, 10) pins in flip-chip packages 4?78 wire-bond packages 4?80 (7..4) & clk(15..12) pins in flip-chip packages 4?76 wire-bond packages 4?78 maximum output clock rate for pll (1, 2, 3, 4) pins in flip-chip packages 4?83 wire-bond packages 4?85 (5, 6, 11, 12) pins in flip-chip packages 4?81 wire-bond packages 4?84 phase & delay shifting 2?96 phase delay 2?96 pll clock networks 2?73 read/write clock mode 2?49 in simple dual-port mode 2?50 regional clock 2?75 external i/o timing parameters 4?34 regional clock bus 2?79 regional clock network 2?75 spread-spectrum clocking 2?98 configuration 3?5 32-bit idcode 3?3 and testing 3?1 data sources for configuration 3?7 local update mode 3?12 local update transition diagram 3?12 operating modes 3?5 partial reconfiguration 3?7 remote update 3?8 remote update transition diagram 3?11 schemes 3?7 signaltap ii embedded logic analyzer 3?5 stratix fpgas with jrunner 3?7 control signals 2?104 d dc switching absolute maximum ratings 4?1 bus hold parameters 4?16 capacitance 4?17 dc & switching characteristics 4?1 external timing parameters 4?33 operating conditions 4?1 performance 4?20 power consumption 4?17 recommended operating conditions 4?1 ddr double-data rate i/o pins 2?111 device features ep1s10, ep1s20, ep1s25, ep1s30, 1?3 ep1s40, ep1s60, ep1s80, 1?3 altera corporation index?3 stratix device handbook, volume 1 differential hstl specifications 4?15 dsp block diagram configuration for 18 x 18-bit 2?55 for 9 x 9-bit 2?56 block interconnect interface 2?71 block interface 2?70 block signal sources & destinations 2?73 blocks arranged in columns 2?53 in stratix devices 2?54 input register modes 2?60 input registers 2?58 multiplier 2?60 block 2?57 signed representation 2?60 sub-block 2?57 sub-blocks using input shift register connections 2?59 pipeline/post mu ltiply register 2?61 e ep1s10 devices column pin fast regional clock external i/o timing parameters 4?36 global clock external i/o timing parameters 4?37 regional clock ex ternal i/o timing parameters 4?36 row pin fast regional clock external i/o timing parameters 4?37 global clock external i/o timing parameters 4?38 regional clock ex ternal i/o timing parameters 4?38 ep1s20 devices column pin fast regional clock external i/o timing parameters 4?39 global clock external i/o timing parameters 4?40 regional clock ex ternal i/o timing parameters 4?39 row pin fast regional clock external i/o timing parameters 4?40 global clock exte rnal i/o timing parameters 4?41 regional clock external i/o timing parameters 4?41 ep1s25 devices column pin fast regional clock external i/o timing parameters 4?42 global clock exte rnal i/o timing parameters 4?43 regional clock external i/o timing parameters 4?42 row pin fast regional clock external i/o timing parameters 4?43 global clock exte rnal i/o timing parameters 4?44 regional clock external i/o timing parameters 4?44 ep1s30 devices column pin fast regional clock external i/o timing parameters 4?45 global clock exte rnal i/o timing parameters 4?45 regional clock external i/o timing parameters 4?45 row pin fast regional clock external i/o timing parameters 4?46 global clock exte rnal i/o timing parameters 4?47 regional clock external i/o timing parameters 4?47 ep1s40 devices column pin fast regional clock external i/o timing parameters 4?48 global clock exte rnal i/o timing parameters 4?49 regional clock external i/o timing parameters 4?48 row pin index?4 altera corporation stratix device handbook, volume 1 fast regional clock external i/o timing parameters 4?49 global clock external i/o timing parameters 4?50 regional clock ex ternal i/o timing parameters 4?50 ep1s60 devices column pin fast regional clock external i/o timing parameters 4?51 global clock external i/o timing parameters 4?52 regional clock ex ternal i/o timing parameters 4?51 m-ram interface locations 2?38 row pin fast regional clock external i/o timing parameters 4?52 global clock external i/o timing parameters 4?53 regional clock ex ternal i/o timing parameters 4?53 ep1s80 devices column pin fast regional clock external i/o timing parameters 4?54 global clock external i/o timing parameters 4?55 regional clock ex ternal i/o timing parameters 4?54 global clock external i/o timing parameters 4?56 row pin fast regional clock external i/o timing parameters 4?55 regional clock ex ternal i/o timing parameters 4?56 h hstl class i specifications 4?14 , 4?15 class ii specifications 4?14 , 4?15 i i/o standards 1.5-v 4?14 , 4?15 i/o specifications 4?4 1.8-v i/o specifications 4?4 2.5-v i/o specifications 4?3 3.3-v 4?13 lvds i/o specifications 4?6 pci specifications 4?9 pcml specifications 4?8 advanced i/o standard support 2?122 column i/o block connection to the interconnect 2?107 column pin input delay adders 4?66 control signal selection per ioe 2?109 ctt i/o specifications 4?16 differential lvds input on-chip termination 2?128 external i/o delay parameters 4?66 gtl+ i/o specifications 4?10 high-speed differential i/o support 2?130 hypertransport technology specifications 4?9 i/o banks 2?125 i/o structure 2?104 i/o support by bank 2?126 ioe structure 2?105 lvcmos specifications 4?3 lvds performance on fast pll input 2?103 lvpecl specifications 4?8 lvttl specifications 4?3 multivolt i/o interface 2?129 multivolt i/o support 2?130 output delay adders for fast slew rate on column pins 4?68 output delay adders for fast slew rate on row pins 4?69 output delay adders for slow slew rate on column pins 4?70 package options & i/o pin counts 1?4 receiver input waveforms for differential altera corporation index?5 stratix device handbook, volume 1 i/o standards 4?5 row i/o block connection to the interconnect 2?106 row pin input delay adders 4?67 signal path through the i/o block 2?108 sstl-18 4?11 sstl-2 4?12 sstl-3 4?12 , 4?13 stratix ioe in bidirectional i/o configuration 2?110 supported i/o standards 2?123 transmitter output waveforms for differ- ential i/o standards 4?6 interconnect c4 connections 2?18 dsp block interfac e to interconnect 2?72 left-facing m-ram to interconnect interface 2?40 lut chain register chain interconnects 2?17 m-ram column unit interface to interconnect 2?42 row unit interface to interconnect 2?41 r4 connections 2?15 ioe internal timing microparameters 4?29 j jtag boundary-scan register length 3?3 support 3?1 stratix jtag instructions 3?2 waveforms 3?4 l lab control signals 2?5 wide control signals 2?6 lut chain & register chain 2?8 m memory architecture byte enable for m4k ram block 2?32 byte enable for m-ram block 2?35 external ram interfacing 2?115 m4k block internal timing microparameter descriptions 4?24 microparameters 4?31 ram block 2?30 configurations (simple dual- port) 2?31 configurations (true dual- port) 2?31 control signals 2?33 lab row interface 2?33 m512 block internal timing microparameter descriptions 4?24 microparameters 4?30 ram block architecture 2?27 configurations (simple dual-port ram) 2?27 control signals 2?29 lab row interface 2?30 memory block size 2?26 memory modes 2?21 m-ram block 2?34 configurations (simple dual- port) 2?34 configurations (true dual- port) 2?35 block control signals 2?37 block internal timing microparameter descriptions 4?25 combined byte selection for x144 index?6 altera corporation stratix device handbook, volume 1 mode 2?36 row & column interface unit signals 2?43 parity bit support 2?24 shift register memory configuration 2?26 support 2?25 simple dual-port & single-port memory configurations 2?23 stratix ioe in ddr input i/o configuration 2?112 stratix ioe in ddr output i/o configuration 2?114 trimatrix memory 2?21 true dual-port memory configuration 2?22 o ordering information 5?1 device pin-outs 5?1 packaging ordering information 5?2 reference & ordering information 5?1 output registers 2?64 output selection multiplexer 2?64 p packaging bga package sizes 1?4 device speed grades 1?5 fineline bga package sizes 1?5 pci-x 1.0 specifications 4?10 phase shifting 2?103 pll advanced clear & enable control 2?98 dynamically programmable counters & de- lays in stratix device enhanced plls 2?91 enhanced fast plls 2?81 fast pll 2?100 channel layout ep1s10, ep1s20 or ep1s25 devices 2?138 channel layout ep1s30 to ep1s80 devices 2?139 port i/o standards 2?102 i/o standards supported for enhanced pll pins 2?94 lock detect & programmable gated locked 2?98 pll locations 2?84 programmable bandwidth 2?91 programmable delay chain 2?111 programmable duty cycle 2?98 reconfiguration 2?90 t testing temperature sensing diode 3?13 electrical characteristics 3?14 external 3?14 temperature vs. temperature-sensing diode voltage 3?15 timing dsp block internal timing microparameter descriptions 4?23 microparameters 4?29 dual-port ram timing microparameter waveform 4?27 external timing in stratix devices 4?33 high-speed i/o timing 4?87 high-speed timing specifications & terminology 4?87 internal parameters 4?22 ioe internal timing microparameter descriptions 4?22 le internal timing microparameters 4?28 logic elements internal timing microparam- eter descriptions 4?22 model 4?19 pll timing 4?94 preliminary & final 4?19 stratix device timing model status 4?19 stratix jtag timing parameters & values 3?4 trimatrix memory trimatrix memory features 2?21 101 innovation drive san jose, ca 95134 (408) 544-7000 http://www.altera.com stratix device handbook, volume 2 s5v2-3.5 copyright ? 2006 altera corporation. all righ ts reserved. altera, the programmable solu tions company, the stylized altera logo, specific device des- ignations, and all other words and logos that are identified as tr ademarks and/or service marks ar e, unless noted otherwise, th e trademarks and service marks of altera corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. al- tera products are protected under numerous u.s. and foreign patents and pending app lications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time with out notice. altera assumes no responsibility or liabil- ity arising out of the application or use of any information, produc t, or service described herein except as expressly agreed to in writing by al tera corporation. altera customers are advised to obtain the latest ver- sion of device specifications before relying on an y published information and before placing orders for products or services . ii altera corporation altera corporation iii contents chapter revision dates ......................................................................... xiii about this handb ook ............................................................................. xv how to find information ........................................................................................................ .............. xv how to contact altera .......................................................................................................... ................. xv typographic conventions ........................................................................................................ ............ xvi section i. clock management revision history ............................................................................................................... ........ section i?1 chapter 1. general-purpose plls in stratix & stratix gx devices introduction ................................................................................................................... ......................... 1?1 enhanced plls .................................................................................................................. ..................... 1?5 clock multiplication & division ................................................................................................ .... 1?9 external clock outputs ......................................................................................................... ........ 1?10 clock feedback ................................................................................................................. .............. 1?14 phase shifting ................................................................................................................. ................ 1?14 lock detect .................................................................................................................... .................. 1?15 programmable duty cycle ........................................................................................................ ... 1?16 general advanced clear & enable contro l ............................................................................... 1?16 programmable bandwidth ......................................................................................................... ... 1?18 clock switchover ............................................................................................................... ............. 1?25 spread-spectrum clocking ....................................................................................................... .... 1?25 pll reconfiguration ............................................................................................................ .......... 1?30 enhanced pll pins .............................................................................................................. .......... 1?30 fast plls ...................................................................................................................... .............. ........... 1?31 clock multiplication & division ................................................................................................ .. 1?34 external clock outputs ......................................................................................................... ........ 1?34 phase shifting ................................................................................................................. ................ 1?35 programmable duty cycle ........................................................................................................ ... 1?36 control signals ................................................................................................................ ................ 1?36 pins ........................................................................................................................... ........................ 1?37 clocking ....................................................................................................................... .............. ........... 1?39 global & hierarchical clocking ................................................................................................. .. 1?39 clock input connections ........................................................................................................ ....... 1?41 clock output connections ....................................................................................................... ..... 1?43 board layout ................................................................................................................... .......... ........... 1?50 vcca & gnda .................................................................................................................... ......... 1?50 iv altera corporation contents stratix device handbook, volume 2 vccg & gndg .................................................................................................................... .......... 1?52 external clock output power .................................................................................................... .. 1?53 guidelines ..................................................................................................................... ................... 1?56 conclusion ..................................................................................................................... ............ ........... 1?56 section ii. memory revision history ............................................................................................................... ...... section ii?1 chapter 2. trimatrix embedded memory blocks in stratix & stratix gx devices introduction ................................................................................................................... ......................... 2?1 trimatrix memory ............................................................................................................... .................. 2?1 clear signals .................................................................................................................. .................... 2?3 parity bit support ............................................................................................................. ................ 2?3 byte enable support ............................................................................................................ ............ 2?4 using trimatrix memory ......................................................................................................... ............ 2?7 implementing single-port mode .................................................................................................. .. 2?7 implementing simple dual-port mode ......................................................................................... 2?8 implementing true dual-port mode .......................................................................................... 2?11 implementing shift-register mode ............................................................................................. 2? 14 implementing rom mode .......................................................................................................... .. 2?15 implementing fifo buffers ...................................................................................................... .... 2?16 clock modes .................................................................................................................... ..................... 2?16 independent clock mode ......................................................................................................... ..... 2?16 input/output clock mode ........................................................................................................ ... 2?18 read/write clock mode .......................................................................................................... ..... 2?21 single-port mode ............................................................................................................... ............. 2?23 designing with trimatrix memory ................................................................................................ .. 2?23 selecting trimatrix memory blocks ............................................................................................ 2? 24 pipeline & flow-through modes ................................................................................................ 2? 24 power-up conditions & memory initiali zation ......................................................................... 2?25 read-during-write operation at the sa me address ......... ........... ............ ........... ........... ......... ...... 2?25 same-port read-during-write mode .......................................................................................... 2?25 mixed-port read-during-write mode ............................ ............................................................ 2?26 conclusion ..................................................................................................................... ............ ........... 2?27 chapter 3. external memory interfac es in stratix & stratix gx devices introduction ................................................................................................................... ......................... 3?1 external memory standards ...................................................................................................... .......... 3?1 ddr sdram ...................................................................................................................... .............. 3?1 rldram ii ...................................................................................................................... ................. 3?4 qdr & qdrii sram ............................................................................................................... ....... 3?6 zbt sram ....................................................................................................................... .................. 3?8 ddr memory support overview .................................................................................................... . 3?10 ddr memory interface pins ...................................................................................................... ... 3?11 dqs phase-shift circuitry ...................................................................................................... ...... 3?15 altera corporation v contents contents ddr registers .................................................................................................................. ............... 3?20 pll ............................................................................................................................ ....................... 3?27 conclusion ..................................................................................................................... ............ ........... 3?27 section iii. i/o standards revision history ............................................................................................................... ..... section iii?1 chapter 4. selectable i/o standa rds in stratix & stratix gx devices introduction ................................................................................................................... ......................... 4?1 stratix & stratix gx i/o standards ............................................................................................. ....... 4?1 3.3-v low voltage transistor-transistor logi c (lvttl) - eia/jedec standard jesd8-b . 4?2 3.3-v lvcmos - eia/jedec standard jesd8-b ........................................................................ 4?3 2.5-v lvttl normal voltage range - eia/jedec standard eia/jesd8-5 .......................... 4?3 2.5-v lvcmos normal voltage range - eia/jedec standard eia/jesd8-5 ..................... 4?3 1.8-v lvttl normal voltage range - eia/jedec standard eia/jesd8-7 .......................... 4?4 1.8-v lvcmos normal voltage range - eia/jedec standard eia/jesd8-7 ..................... 4?4 1.5-v lvcmos normal voltage ra nge - eia/jedec standard jesd8-11 ............................ 4?4 1.5-v hstl class i & ii - eia/jedec standard eia/jesd8-6 ................................................. 4?5 1.5-v differential hstl - eia/jedec standard eia/je sd8-6 ................................................ 4?6 3.3-v pci local bus - pci special interest group pci local bus specification rev. 2.3 ....... 4?6 3.3-v pci-x 1.0 local bus - pci-sig pci-x local bu s specification revision 1.0a ................ 4?7 3.3-v compact pci bus - pci sig pci local bus specification revision 2.3 .......................... 4?7 3.3-v 1 agp - intel corporation accelerated gr aphics port interface specification 2.0 ..... 4?7 3.3-v 2 agp - intel corporation accelerated gr aphics port interface specification 2.0 ..... 4?8 gtl - eia/jedec standard eia/jesd8-3 .................................................................................. 4?8 gtl+ ........................................................................................................................... ....................... 4?8 ctt - eia/jedec standard jesd8-4 ............................................................................................ 4?9 sstl-3 class i & ii - eia/jedec standard jesd8-8 .................................................................. 4?9 sstl-2 class i & ii - eia/jedec standard jesd8-9a ............................................................. 4?10 sstl-18 class i & ii - eia/jedec preliminary standard jc42.3 ............................................ 4?11 differential sstl-2 - eia/jedec standa rd jesd8-9a ............................................................. 4?11 lvds - ansi/tia/eia standard ansi/tia/eia-644 .......................................................... 4?12 lvpecl ......................................................................................................................... .................. 4?13 pseudo current mode logic (pcml) ......................................................................................... 4?13 hypertransport techno logy - hypertransport consortium ......... ........................................ 4?14 high-speed interfaces .......................................................................................................... ......... ...... 4?15 oif-spi4.2 ..................................................................................................................... ................... 4?15 oif-sfi4.1 ..................................................................................................................... ................... 4?15 10 gigabit ethernet sixteen bit interface (xsbi) - ieee draft standard p802.3ae/d2.0 ...... 4?16 rapidio interconnect specification revision 1.1 ....................................................................... 4?16 hypertransport techno logy - hypertransport consortium ......... ........................................ 4?17 utopia level 4 ? atm forum technical commi ttee standard af-phy -0144.001 ........... 4?17 stratix & stratix gx i/o banks ................................................................................................. ......... 4?17 non-voltage-referenced standards ............................................................................................ 4?2 4 voltage-referenced standards ................................................................................................... .. 4?24 vi altera corporation contents stratix device handbook, volume 2 mixing voltage referenced & non-vo ltage referenced standards ....................................... 4?25 drive strength ................................................................................................................. ........ ............. 4?26 standard current drive strength ................................................................................................ .4?26 programmable current drive strength ...................................................................................... 4?27 hot socketing .................................................................................................................. ........ ............. 4?27 dc hot socketing specification ................................. ................................................................ .. 4?28 ac hot socketing specification ................................................................................................. .. 4?28 i/o termination ................................................................................................................ .................. 4?28 voltage-referenced i/o standards ............................. ................................................................ 4? 28 differential i/o standards ..................................................................................................... ....... 4?29 differential termination (rd) ............. ..................................................................................... .... 4?29 transceiver termination ........................................................................................................ ....... 4?30 i/o pad placement guidelines ................................................................................................... ....... 4?30 differential pad placement guidelines ....................................................................................... 4?3 0 vref pad placement guidelines ................................................................................................. 4 ?31 output enable group logic option in quartus ii .................................................................... 4?34 toggle rate logic option in quartus ii ...................................................................................... 4?3 5 dc guidelines .................................................................................................................. ............... 4?35 power source of various i/o standards ......................... ................................................................ 4 ?38 quartus ii software support ..................................................................................................... ......... 4?38 compiler settings .............................................................................................................. ............. 4?38 device & pin options ........................................................................................................... ......... 4?39 assign pins .................................................................................................................... .................. 4?39 programmable drive strength settings .......................... ............................................................ 4?40 i/o banks in the floorplan view ................................................................................................ .4?40 auto placement & verificati on of selectable i/o standards ................................................... 4?41 conclusion ..................................................................................................................... ............ ........... 4?42 more information ............................................................................................................... ........... ...... 4?42 references ..................................................................................................................... ......... ......... ...... 4?42 chapter 5. high-speed d ifferential i/o interfaces in stratix devices introduction ................................................................................................................... ......................... 5?1 stratix i/o banks .............................................................................................................. ..................... 5?1 stratix differential i/o standards ............................................................................................. .... 5?2 stratix differential i/o pin location .......................................................................................... ... 5?5 principles of serdes operation ................................................................................................. ........ 5?6 stratix differential i/o receiver operat ion ................................................................................. 5?7 stratix differential i/o transmitter operation ........................................................................... 5?9 transmitter clock output ....................................................................................................... ...... 5?10 divided-down transmitter clock output ................................................................................. 5?10 center-aligned transmitter clock output ................................................................................ 5?11 sdr transmitter clock output ................................................................................................... .5?12 using serdes to implement ddr .................................................................................................. . 5?13 using serdes to implement sdr .................................................................................................. .. 5?14 differential i/o interface & fast plls .. ....................................................................................... .... 5?16 clock input & fast pll output relationship ............................................................................ 5?18 fast pll specifications ........................................................................................................ .......... 5?20 altera corporation vii contents contents high-speed phase adjust ........................................................................................................ ..... 5?21 counter circuitry .............................................................................................................. ............. 5?22 fast pll serdes channel support .............................. .............................................................. 5?23 advanced clear & enable control .............................................................................................. 5? 25 receiver data realignment ..................................... ................................................................. .......... 5?25 data realignment principles of operation ................... .............................................................. 5?25 generating the txloaden signal ............................................................................................. 5?27 realignment implementation ..................................................................................................... .. 5?28 source-synchronous timing budget .............................. ................................................................. . 5?30 differential data orientation ........... ....................................................................................... ...... 5?30 differential i/o bit position .................................................................................................. ....... 5?31 timing definition .............................................................................................................. ............. 5?32 input timing waveform .......................................................................................................... ..... 5?39 output timing .................................................................................................................. .............. 5?40 receiver skew margin ........................................................................................................... ........ 5?40 switching characteristics ...................................................................................................... ........ 5?42 timing analysis ................................................................................................................ .............. 5?42 serdes bypass ddr differential signa ling .............. ............ ........... ........... ........... ......... ......... ...... 5?42 serdes bypass ddr differential interface review ................................................................. 5?42 serdes clock domains ........................................................................................................... ..... 5?42 serdes bypass ddr differential signaling receiver operation .......................................... 5?43 serdes bypass ddr differential signaling transmitter operation ..................................... 5?44 high-speed interface pin locations ............................................................................................. .... 5?45 differential i/o termination ................................................................................................... .......... 5?46 r d differential termination ...................................................................................................... .... 5?46 hypertransport & lvpecl differential termination ............................................................. 5?47 pcml differential termination .................................................................................................. .5?47 differential hstl termination ........... ....................................................................................... .. 5?48 differential sstl-2 termination ............ .................................................................................... .. 5?49 board design consideration ..................................................................................................... ......... 5?50 software support ............................................................................................................... .................. 5?51 differential pins in stratix .................................. ................................................................. .......... 5?51 fast plls ...................................................................................................................... .................... 5?52 lvds receiver block ............................................................................................................ ......... 5?60 lvds transmitter module ........................................................................................................ ... 5?65 serdes bypass mode ............................................................................................................. ...... 5?70 summary ........................................................................................................................ ............ ........... 5?75 section iv. digital sign al processing (dsp) revision history ............................................................................................................... ..... section iv?1 chapter 6. dsp blocks in st ratix & stratix gx devices introduction ................................................................................................................... ......................... 6?1 dsp block overview ............................................................................................................. ................ 6?2 architecture ................................................................................................................... ......................... 6?5 viii altera corporation contents stratix device handbook, volume 2 multiplier block ............................................................................................................... ................. 6?5 adder/output block ............................................................................................................. .......... 6?9 routing structure & control signals ........................................................................................... 6 ?12 operational modes .............................................................................................................. ................ 6?18 simple multiplier mode ......................................................................................................... ....... 6?18 multiply accumulator mode ...................................................................................................... .. 6?22 two-multiplier adder mode ...................................................................................................... .. 6?23 four-multiplier adder mode ..................................................................................................... .. 6?24 software support ............................................................................................................... .................. 6?28 conclusion ..................................................................................................................... ............ ........... 6?28 chapter 7. implementing hig h performance dsp functions in stratix & stratix gx devices introduction ................................................................................................................... ......................... 7?1 stratix & stratix gx dsp block overview ......................................................................................... 7?1 trimatrix memory overview ..................................... ................................................................. ........ 7?4 dsp function overview .......................................................................................................... ............. 7?5 finite impulse response (fir) filters .......................................................................................... ....... 7?5 fir filter background .......................................................................................................... ............ 7?6 basic fir filter ............................................................................................................... ................... 7?7 time-domain multiplexed fir filters ........................................................................................ 7?13 polyphase fir interpolation filters ............................................................................................ .7?17 polyphase fir decimation filters ............................................................................................... .7?24 complex fir filter ............................................................................................................. ............ 7?31 infinite impulse response (iir) filters ........................................................................................ ..... 7?34 iir filter background .......................................................................................................... .......... 7?34 basic iir filters .............................................................................................................. ................. 7?36 butterworth iir filters ........................................................................................................ ........... 7?39 matrix manipulation ............................................................................................................ ......... ...... 7?45 background on matrix manipulation .......................................................................................... 7?45 two-dimensional filtering & video imaging ........................................................................... 7?46 discrete cosine transform (dct) ................................................................................................ ..... 7?52 dct background ................................................................................................................. ........... 7?52 2-d dct algorithm .............................................................................................................. ......... 7?53 arithmetic functions ........................................................................................................... ................ 7?59 background ..................................................................................................................... ................ 7?59 arithmetic function implementation ......................................................................................... 7?60 arithmetic function implementation results ............................................................................ 7?62 arithmetic function design example ......................................................................................... 7?62 conclusion ..................................................................................................................... ............ ........... 7?62 references ..................................................................................................................... ......... ......... ...... 7?63 section v. ip & design considerations revision history ............................................................................................................... ...... section v?1 altera corporation ix contents contents chapter 8. implementing 10-gigabit ethern et using stratix & stratix gx devices introduction ................................................................................................................... ......................... 8?1 related links .................................................................................................................. ................... 8?1 10-gigabit ethernet ............................................................................................................ .................... 8?1 interfaces ..................................................................................................................... ............................ 8?5 xsbi ........................................................................................................................... ......................... 8?5 xgmii .......................................................................................................................... ..................... 8?13 xaui ........................................................................................................................... ...................... 8?19 i/o characteristics for xsbi, xgmii & xaui ...... ........... ........... ........... ........... ........... ............ ........ 8?21 software implementation ........................................................................................................ ...... 8?22 ac/dc specifications ........................................................................................................... ........ 8?22 10-gigabit ethernet mac core ................................................................................................... .8?24 conclusion ..................................................................................................................... .................. 8?25 chapter 9. implementing sfi-4 in stratix & stratix gx devices introduction ................................................................................................................... ......................... 9?1 system topology ................................................................................................................ .............. 9?3 interface implementation in stratix & stratix gx device s ......................................................... 9?5 ac timing specifications ....................................................................................................... ....... 9?10 electrical specifications ...................................................................................................... ........... 9?12 software implementation ........................................................................................................ ...... 9?13 conclusion ..................................................................................................................... .................. 9?13 chapter 10. transitioning apex design s to stratix & stratix gx devices introduction ................................................................................................................... ............ ........... 10?1 general architecture ........................................................................................................... ................ 10?1 logic elements ................................................................................................................. ............... 10?2 multitrack interconnect ........................................................................................................ ........ 10?3 directdrive technology ......................................................................................................... ....... 10?4 architectural element names .................................................................................................... .. 10?5 trimatrix memory ............................................................................................................... ................ 10?8 same-port read-during-write mode ........ ........... ........... ........... ............ ........... ........... ............. 10?10 mixed-port read-during-write mode ....... ............... ........... ........... ........... ......... ......... ............. 10?11 memory megafunctions ........................................................................................................... ... 10?12 fifo conditions ................................................................................................................ ........... 10?13 design migration mode in quartus ii software ............ ........... ............ ........... ........... ............. 10?13 dsp block ...................................................................................................................... ......... ............. 10?16 dsp block megafunctions ........................................................................................................ ... 10?16 plls & clock networks .......................................................................................................... ......... 10?18 clock networks ................................................................................................................. ........... 10?18 plls ........................................................................................................................... ..................... 10?19 i/o structure .................................................................................................................. ........... ......... 10?25 external ram interfacing ....................................................................................................... .... 10?25 i/o standard support ........................................................................................................... ...... 10?26 high-speed differential i/o standards ... ................. ........... ........... ........... ......... ......... ............. 10?26 altlvds megafunction ........................................................................................................... ........ 10?29 configuration .................................................................................................................. ........ ........... 10?30 x altera corporation contents stratix device handbook, volume 2 configuration speed & schemes ............ .................................................................................... 10 ?30 remote update configuration ................................... ................................................................ 1 0?31 jtag instruction support ....................................................................................................... .... 10?31 conclusion ..................................................................................................................... ............ ......... 10?32 section vi. system configuration & upgrades revision history ............................................................................................................... ..... section vi?2 chapter 11. configuring stra tix & stratix gx devices introduction ................................................................................................................... ............ ........... 11?1 device configuration overview .................................................................................................. ..... 11?2 msel[2..0] pins ................................................................................................................ ............... 11?3 v ccsel pins .......................................................................................................................... ............ 11?3 porsel pins .................................................................................................................... ............... 11?5 nio_pullup pins ................................................................................................................ ......... 11?5 tdo & nceo pins ................................................................................................................ .......... 11?6 configuration file size ........................................................................................................ ......... ...... 11?6 altera configuration devices ................................. .................................................................. ......... 11?7 configuration schemes .......................................................................................................... ............. 11?7 ps configuration ............................................................................................................... ............. 11?7 fpp configuration .............................................................................................................. .......... 11?21 ppa configuration .............................................................................................................. ......... 11?30 jtag programming & config uration ......... ........... ............ ........... ........... ........... ......... ............. 11?36 jtag programming & configur ation of multiple devices ............. ........... ............ ........... .... 11?39 configuration with jrunner software dr iver ................ ........... ............ ........... ........... ............. 11?41 jam stapl programming & test language ............ ........... ........... ........... ......... ......... ............. 11?42 configuring using the microblaster driver .................................................................................. 11?5 1 device configuration pins ...................................................................................................... ......... 11?51 chapter 12. remote system configuratio n with stratix & stratix gx devices introduction ................................................................................................................... ............ ........... 12?1 remote configuration operation ......... ........................................................................................ ..... 12?1 remote system configuration modes ........................................................................................ 12?3 remote system configuration components ..................... ......................................................... 12?5 quartus ii software support .................................................................................................... ........ 12?12 altremote_update megafunction ................................................................................................ 12 ?14 remote update wysiwyg atom ........... ........... ........... ........... ............ ........... ........... ............. 12?17 using enhanced configuration devices .......................... .............................................................. 12? 19 local update programming file genera tion ........... ........... ........... ........... ......... ......... ............. 12?21 remote update programming file gene ration ........... ........... ........... ........... ............ ........... .... 12?32 combining max devices & flash memory .. ........... ........... ........... ............ ........... ........... ............. 12?42 using an external processor .................................................................................................... ........ 12?43 conclusion ..................................................................................................................... ............ ......... 12?44 altera corporation xi contents contents section vii. pcb layout guidelines revision history ............................................................................................................... ... section vii?1 chapter 13. package inform ation for stratix devices introduction ................................................................................................................... ............ ........... 13?1 device & package cross reference ............................................................................................... .... 13?1 thermal resistance ............................................................................................................. ........... ...... 13?2 package outlines ............................................................................................................... .................. 13?3 484-pin fineline bga - flip chip ............................................................................................... 13?4 672-pin fineline bga - flip chip ............................................................................................... 13?6 780-pin fineline bga - flip chip ............................................................................................... 13?8 956-pin ball grid array (bga) - flip chip .......... ........... ........... ............ ........... ........... ............. 13?10 1,020-pin fineline bga - flip chip ...... ........... ........... ........... ........... ........... ........... ............ ...... 13? 12 1,508-pin fineline bga - flip chip ...... ........... ........... ........... ........... ........... ........... ............ ...... 13? 14 chapter 14. designing with 1.5-v devices introduction ................................................................................................................... ............ ........... 14?1 power sequencing & hot socketing ............................................................................................... .. 14?1 using multivolt i/o pins ....................................................................................................... ............ 14?2 voltage regulators ............................................................................................................. ........... ...... 14?3 linear voltage regulators ...................................................................................................... ....... 14?5 switching voltage regulators ................................................................................................... ... 14?7 maximum output current ......................................................................................................... .. 14?8 selecting voltage regulators ................................................................................................... ..... 14?9 voltage divider network ........................................................................................................ .... 14?10 1.5-v regulator circuits ....................................................................................................... ....... 14?10 1.5-v regulator application examples .......................................................................................... 1 4?19 synchronous switching regulator exampl e ............ ........... ........... ........... ......... ......... ............. 14?20 board layout ................................................................................................................... .......... ......... 14?21 split-plane method ............................................................................................................. .......... 14?23 conclusion ..................................................................................................................... ............ ......... 14?23 references ..................................................................................................................... ......... ............. 14?24 xii altera corporation contents stratix device handbook, volume 2 altera corporation xiii chapter revision dates the chapters in this book, stratix device handbook, volume 2 , were revised on the following dates. where chapters or groups of chapters are av ailable separately, part numbers are listed. chapter 1. general-purpose plls in stratix & stratix gx devices revised: july 2005 part number: s52001-3.2 chapter 2. trimatrix embedded memory blocks in stratix & stratix gx devices revised: july 2005 part number: s52003-3.3 chapter 3. external memory interfac es in stratix & stratix gx devices revised: june 2006 part number: sii52003-3.3 chapter 4. selectable i/o standards in stratix & stratix gx devices revised: june 2006 part number: s52004-3.4 chapter 5. high-speed differential i/ o interfaces in stratix devices revised: july 2005 part number: s52005-3.2 chapter 6. dsp blocks in stratix & stratix gx devices revised: july 2005 part number: s52006-2.2 chapter 7. implementing high performance d sp functions in stratix & stratix gx devices revised: september 2004 part number: s52007-1.1 chapter 8. implementing 10-gigabit ethern et using stratix & stratix gx devices revised: july 2005 part number: s52010-2.0 chapter 9. implementing sfi-4 in stratix & stratix gx devices revised: july 2005 part number: s52011-2.0 xiv altera corporation chapter revision dates stratix device handbook, volume 2 chapter 10. transitioning apex desi gns to stratix & stratix gx devices revised: july 2005 part number: s52012-3.0 chapter 11. configuring stra tix & stratix gx devices revised: july 2005 part number: s52013-3.2 chapter 12. remote system configuratio n with stratix & stratix gx devices revised: september 2004 part number: s52015-3.1 chapter 13. package information for stratix devices revised: july 2005 part number: s53008-3.0 chapter 14. designing with 1.5-v devices revised: january 2005 part number: c51012-1.1 altera corporation xv about this handbook this handbook provides comprehe nsive information about the altera ? stratix ? family of devices. how to find information you can find more information in the following ways: the adobe acrobat find feature, which searches the text of a pdf document. click the binoculars toolba r icon to open the find dialog box. acrobat bookmarks, which serve as an additional table of contents in pdf documents. thumbnail icons, which provide miniature previews of each page and provide a link to the pages. numerous links, shown in green text, which allow you to jump to related information. how to contact altera for the most up-to-date information about altera products, go to the altera world-wide web site at www.altera.com . for technical support on this product, go to www.altera.com/mysupport . for additional information about altera products , consult the sources shown below. information type usa & canada all other locations technical support www.altera.com/mysupport/ www.altera.com/mysupport/ (800) 800-epld (3753) (7:00 a.m. to 5:00 p.m. pacific time) +1 408-544-8767 7:00 a.m. to 5:00 p.m. (gmt -8:00) pacific time product literature www.altera.com www.altera.com altera literature services literature@altera.com literature@altera.com non-technical customer service (800) 767-3753 + 1 408-544-7000 7:00 a.m. to 5:00 p.m. (gmt -8:00) pacific time ftp site ftp.altera.com ftp.altera.com xvi altera corporation typographic conventions stratix device handbook, volume 2 typographic conventions this document uses the typogr aphic conventions shown below. visual cue meaning bold type with initial capital letters command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. example: save as dialog box. bold type external timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and softw are utility names are shown in bold type. examples: f max , \qdesigns directory, d: drive, chiptrip.gdf file. italic type with initial capital letters document titles are shown in italic ty pe with initial capital letters. example: an 75: high-speed board designs. italic type internal timing parameters and variables are shown in italic type. examples: t pia , n + 1. variable names are enclosed in angle br ackets (< >) and shown in italic type. example: altera corporation section i?1 section i. clock management this section provides information on the different types of phase-lock loops (plls). the feature-rich, enhanc ed plls assist you in managing clocks internally and also have the ability to drive off-chip to control system-level clock networks. the fast plls offer general-purpose clock management with multiplication an d phase shifting as well as high-speed outputs to manage the high -speed differential i/o interfaces. this chapter contains detailed information on the features, the interconnections to the core and off-chi p, and the specifications for both types of plls. this section contains the following: chapter 1, general-purpose plls in stratix & stratix gx devices revision history the table below shows th e revision history for chapter 1 . chapter date/version changes made 1 july 2005, v3.2 removed information regarding delay shift (time delay elements). updated ta b l e 1 ? 8 . updated ?clock switchover? section. updated figure 1?22 . updated ?control signals? section. updated table 1?16 . september 2004, v3.1 updated note 1 in table 1?17 on page 1?32 . updated note 1 in table 1?21 on page 1?48 . updated table 1?12 on page 1?34 . april 2004, v3.0 changed pci-x to pci-x 1.0 throughout volume. note 3 added to columns 11 and 12 in table 1?1 . deleted ?stratix gx clock input sources for enhanced and fast plls? table. deleted ?stratix gx global and regional clock output line sharing for enhanced and fast plls? table. deleted ?stratix gx clk and fpllclk input pin connections to global & regional clock networks? table. changed clk checkmarks in table 1?14 . updated notes to table 1?3 . and figure 1?3 . added table 1?7 . clock switchover section has been moved to an 313 . changed rclk values in figures 1?20 and 1?22 . section i?2 altera corporation clock management stratix device handbook, volume 2 1 november 2003, v2.2 updated the ?lock detect? section. october 2003, v2.1 updated the ?vccg & gndg? section. updated figure 1?14 . july 2003, v2.0 updated clock multiplication and division, spread spectrum, and notes 1 and 8 in table 1-3. updated inclk[1..0] port name in table 1-4. updated ranges for epll post-scale and pre-scale di viders on page 1-9 added 1.8v hstl support for epll in table 1-6 and 1-13. new requirement to assert are set signal each pll when it has to re- acquire lock on either a new clock after loss of lock (page 1-16) corrected input port extswitch to clkswitch throughout this chapter. updated clkloss description in table 1-9. updated text on jitter for spread spectrum on page 1-38. removed pll specifications. see chapter 4 of volume 1. chapter date/version changes made altera corporation 1?1 july 2005 1. general-purpose plls in stratix & stratix gx devices introduction stratix ? and stratix gx devices have highly versatile phase-locked loops (plls) that provide robust clock ma nagement and synt hesis for on-chip clock management, external system clock management, and high-speed i/o interfaces. there are two types of plls in each stratix and stratix gx device: enhanced plls and fast plls. each device has up to four enhanced plls, which are feature-rich, general-purpose plls supporting advanced capabilities such as external feedback, clock switchover, phase and delay control, pll reconfiguration, spread spectrum clocking, and programmable bandwidth. there are also up to eight fast plls per device, which offer general-purpose clock management with multiplication and phase shifting as well as high-speed outputs to manage the high-speed differential i/o interfaces. the altera ? quartus ? ii software enables the plls and their features without requiring any external devices. tables 1?1 and 1?2 show pll availability for stratix and stratix gx devices, respectively. table 1?1. stratix device pll availability device fast plls enhanced plls 1234 7 8 9 10 5 (1) 6 (1) 11 (2) 12 (2) ep1s10 vvvv v v ep1s20 vvvv v v ep1s25 vvvv v v ep1s30 vvvvv (3) v (3) v (3) v (3) vv ep1s40 vvvvv (3) v (3) v (3) v (3) vvv (3) v (3) ep1s60 vvvv v v v v v v v v ep1s80 vvvv v v v v v v v v notes to ta b l e 1 ? 1 : (1) plls 5 and 6 each have eight single-e nded outputs or four differential outputs. (2) plls 11 and 12 each have one single-ended output. (3) ep1s30 and ep1s40 devices do not support these plls in the 780-pin fineline bga ? package. s52001-3.2 1?2 altera corporation stratix device handbook, volume 2 july 2005 introduction table 1?2. stratix gx de vice pll availability device fast plls enhanced plls 1278561112 ep1s10c vv vv ep1s10d vv vv ep1s25c vv vv ep1s25d vv vv ep1s25f vv vv ep1s40d vvvvvvvv ep1s40g vvvvvvvv altera corporation 1?3 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices table 1?3 shows the enhanced and fast pll features in stratix and stratix gx devices. table 1?3. stratix & stratix gx pll features feature enhanced pll fast pll clock multiplication and division m /( n post-scale counter) (1) m /(post-scale counter) (2) phase shift down to 156.25-ps increments (3) , (4) down to 125-ps increments (3) , (4) clock switchover v pll reconfiguration v programmable bandwidth v spread spectrum clocking v programmable duty cycle vv number of internal clock outputs 6 3 (5) number of external clock outputs f our differential/eight singled-ended or one single-ended (6) (7) number of feedback clock inputs 2 (8) notes to ta b l e 1 ? 3 : (1) for enhanced plls, m , n , range from 1 to 512 and post-scale counters g, l, e range from 1 to 1024 with 50% duty cycle. with a non-50% duty cycle the post-scale counters g, l, e range from 1 to 512. (2) for fast plls, m , n , and post-scale counters range from 1 to 32. (3) the smallest phase shif t is determined by the voltage controlle d oscillator (vco) period divided by 8. (4) for degree increments, stratix and stratix gx devices can shift all output frequencies in increments of at least 45 . smaller degree increments are possible dependin g on the frequency an d divide parameters. (5) plls 7, 8, 9, and 10 have two output ports per pll. plls 1, 2, 3, and 4 have three output ports per pll. on stratix gx devices, plls 3, 4, 9, and 10 are not available for general-purpose use. (6) every stratix and stratix gx device has two enhanced plls (plls 5 and 6) with either eight single-ended outputs or four differential outputs each. two additional enhanced plls (plls 11 and 12) in ep1s80, ep1s60, ep1s40 (pll 11 and 12 not supported for f780 package), and ep1s gx40 devices each have one single-ended output. (7) fast plls can drive to any i/o pin as an external clock. for high-speed differential i/o pins, the device uses a data channel to generate txclkout . (8) every stratix and stratix gx device has two enhanced plls with one single-ended or diff erential external feedback input per pll. 1?4 altera corporation stratix device handbook, volume 2 july 2005 introduction figure 1?1 shows a top-level diagram of the stratix device and pll floorplan. figure 1?2 shows a top-level diagram of the stratix gx device and pll floorplan. see ?clocking? on page 1?39 for more detail on pll connections to global and regional clocks. figure 1?1. strati x pll locations fpll7clk fpll10clk fpll9clk clk8-11 fpll8clk clk0-3 7 1 2 8 10 4 3 9 11 5 12 6 clk4-7 clk12-15 plls altera corporation 1?5 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices figure 1?2. stratix gx pll locations enhanced plls stratix and stratix gx devices contai n up to four enhanced plls with advanced clock mana gement features. figure 1?3 shows a diagram of the enhanced pll. lvdsclk0 hssi hssi lvdsclk1 clk0-3 7 1 2 8 11 5 12 6 clk4-7 clk12-15 plls 1?6 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls figure 1?3. stratix & st ratix gx enhanced pll notes to figure 1?3 : (1) external feedback is available in plls 5 and 6. (2) this single-ended external output is available from the g 0 counter for plls 11 and 12. (3) these four counters and external outputs are available in plls 5 and 6. (4) this connection is only available on ep1sgx40 stratix gx devices and ep1s40 and larger stratix devices. for example, plls 5 and 11 are adjacent and plls 6 and 12 are adjacent. the ep1s40 device in the f780 package does not support plls 11 and 12. n charge pump vco g 0 g 1 g 2 e 0 8 4 global clocks e 1 e 2 i/o buffers (3) e 3 t t t t t t t t lock detect to i/o or general routing inclk0 inclk1 fbin g 3 l 1 l 0 from adjacent pll (4) m spread spectrum i/o buffers (2) (1) loop filter & filter programmable time delay on each pll port post-scale counters clock switch-over circuitry phase frequency detector (pfd) vco phase selection selectable at each pll output port vco phase selection affecting all outputs t t t n t m regional clocks 4 altera corporation 1?7 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices figure 1?4 shows all the possible po rts of the enhanced plls. figure 1?4. enhanced pll signals notes to figure 1?4 : (1) this input pin is shared by all enhanced and fast plls. (2) these are either single-e nded or differential pins. (3) ep1s10, ep1s20, and ep1s25 devices in 672-pin ball gr id array (bga) and 484- and 672-pin fineline bga packages only have two pairs of external clocks (i.e., pll_out0p , pll_out0n , pll_out1p , and pll_out1n ). inclk0 inclk1 clkswitch scandata scanclk pllenable clk[5..0] locked physical pin clkloss areset clkena[5..0] pfdena si g nal driven by internal lo g ic si g nal driven to internal lo g ic internal clock si g nal extclk4 active_clock extclkena[3..0] pll_out0p fbin only plls 5 and 6 clkbad[1..0] (1) (2) (2) pll_out0n pll_out1p pll_out1n pll_out2p pll_out2n pll_out3p pll_out3n scanaclr (2) only plls 11 and 12 scandataout ( 3 ) ( 3 ) ( 3 ) ( 3 ) 1?8 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls tables 1?4 and 1?5 describe all the enhanced pll ports. table 1?4. enhanced pll input signals port description source destination inclk[1..0] primary and secondary reference clock inputs to pll pin n counter fbin external feedback input to the pll (plls 5 and 6 only) pin phase frequency detector (pfd) pllena enable pin for enabling or disabling all or a set of plls ? active high pin general pll control signal clkswitch switchover signal used to initiate external clock switchover control ? this signal switches the clock on the rising edge of clkswitch logic array pll switchover circuit areset signal used to reset the pll which re- synchronizes all the counter outputs ? active high logic array general pll control signal clkena[5..0] enable clock driving regional or global clock ? active high logic array clock output extclkena[3..0] enable clock driving external clock (plls 5 and 6 only) ? active high logic array clock output pfdena enables the outputs from the phase frequency detector ? active high logic array pfd scanclk serial clock signal for t he real-time pll control feature logic array reconfiguration circuit scandata serial input data stream for the real-time pll control feature logic array reconfiguration circuit scanaclr serial shift register reset clearing all registers in the serial shift chain ? active high logic array reconfiguration circuit altera corporation 1?9 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices clock multiplication & division each stratix and stratix gx device enhanced pll provides clock synthesis for pll output ports using m /( n post-scale counter) scaling factors. the input clock is di vided by a pre-scale counter, n , and is then multiplied by the m feedback factor. the contro l loop drives the vco to match f in ( m / n ). each output port has a unique post-scale counter that divides down the high-frequency vco. for multiple pll outputs with differen t frequencies, the vco is set to the least common multiple of the output frequencies that meets its frequency specifications. then, the post-scale counters scale down the output frequency for each output port. fo r example, if output frequencies required from one pll are 33 and 66 mhz, then the quartus ii software sets the vco to 330 mhz (the least common multiple of 33 and 66 mhz within the vco range). there is one pre-scale counter, n , and one multiply counter, m , per pll, with a range of 1 to 512 on each. there are two post-scale counters ( l ) for regional clock output po rts, four counters ( g ) for global clock output ports, and up to four counters ( e ) for external clock outputs, all ranging from 1 to 1024 with a 50% duty cycle setting. the post-scale counters table 1?5. enhanced pll output signals port description source destination clk[5..0] pll outputs driving regional or global clock pll counter internal clock pll_out[3..0]p/n pll_out[3..0] are pll outputs driving the four differential or eight single-ended external clock output pins for plls 5 or 6. p or n are the positive (p) and negative (n) pins for differential pins. pll counter pin(s) extclk4 pll output driving external clock output pin from plls 11 and 12 pll g 0 counter pin clkloss signal indicating the switchover circuit detected a switchover condition pll switchover circuit logic array clkbad[1..0] signals indicating which reference clock is no longer toggling. clkbad1 indicates inclk1 status, clkbad0 indicates inclk0 status pll switchover circuit logic array locked lock output from lock detect circuit ? active high pll lock detect logic array activeclock signal to indicate which clock ( 1 = inclk0 or 0 = inclk1 ) is driving the pll. pll clock multiplexer logic array scandataout output of the last shift register in the scan chain pll scan chain logic array 1?10 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls range from 1 to 512 with any non-50% duty cycle setting. the quartus ii software automatically chooses the a ppropriate scaling factors according to the input frequency, multiplication, and division values entered into the altpll megawizard plug-in manager. external clock outputs enhanced plls 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). see figure 1?5 . altera corporation 1?11 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices figure 1?5. external clock outputs for plls 5 & 6 notes to figure 1?5 : (1) le: logic element. (2) the design can use each external clock output pin as a general-purpose output pin from the logic array. these pins are multiplexed with ioe outputs. (3) two single-ended outputs ar e possible per output counter ? either two outputs of the same frequency and phase or one shifted 180 . (4) ep1s10, ep1s20, and ep1s25 devices in 672-pin ball gr id array (bga) and 484- and 672-pin fineline bga packages only have two pairs of external clocks (i.e., pll_out0p , pll_out0n , pll_out1p , and pll_out1n ). any of the four external output coun ters can drive the single-ended or differential clock outputs for plls 5 and 6. this means one counter or frequency can drive all output pins available from pll 5 or pll 6. each e 0 counter pll_out0p ( 3 ), (4 ) pll_out0n ( 3 ), (4 ) pll_out1p ( 3 ), (4 ) pll_out1n ( 3 ), (4 ) pll_out2p ( 3 ), (4 ) pll_out2n ( 3 ), (4 ) pll_out3p ( 3 ), (4 ) pll_out3n ( 3 ), (4 ) e 1 counter e 2 counter e 3 counter from ioe (1), ( 2 ) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) from ioe (1) 4 ( 3 ) 1?12 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls pair of output pins (four pins total) has dedicated vcc and gnd pins to reduce the output clock?s overall ji tter by providing im proved isolation from switching i/o pins. for plls 5 and 6, each pi n of a single-ended output pair can either be in phase or 180 out of phas e. the quartus ii software transfers the not gate in the design into the ioe to implement 180 phase with respect to the other pin in the pair. the clock output pin pairs support the same i/o standards as standard output pins (i n the top and bottom banks) as well as lvds, lvpecl, pcml, hypertransport tm technology, differential hstl, and differential sstl. table 1?6 shows which i/o standards the enhanced pll clock pins support. when in single-ended or differential mode, one power pin supports two differ ential or four single-ended pins. both outputs use the same standards in single-ended mode to maintain performance. you can also use the ex ternal clock output pins as user output pins if external enhanc ed pll clocking is not needed. the enhanced pll can also drive out to any regular i/o pin through the global or regional clock network. th e jitter on the output clock is not guaranteed for this case. table 1?6. i/o standards supported for enhanced pll pins (part 1 of 2) i/o standard input output inclk fbin pllenable extclk lv t t l vvvv lv c m o s vvvv 2.5 v vv v 1.8 v vv v 1.5 v vv v 3.3-v pci vv v 3.3-v pci-x 1.0 vv v lvpecl vv v pcml vv v lv d s vv v hypertransport technology vv v differential hstl vv differential sstl v 3.3-v gtl vv v altera corporation 1?13 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices enhanced plls 11 and 12 support one single-ended output each (see figure 1?6 ). these outputs do not have their own vcc and gnd signals. therefore, to minimize jitter, do not place switching i/o pins next to this output pin. figure 1?6. external clock outputs for enhanced plls 11 & 12 note to figure 1?6 : (1) for pll11, this pin is clk13n ; for pll 12 this pin is clk6n . 3.3-v gtl+ vv v 1.5-v hstl class i vv v 1.5-v hstl class ii vv v 1.8-v hstl class i vv v 1.8-v hstl class ii vv v sstl-18 class i vv v sstl-18 class ii vv v sstl-2 class i vv v sstl-2 class ii vv v sstl-3 class i vv v sstl-3 class ii vv v agp (1 and 2 ) vv v ctt vv v table 1?6. i/o standards supported for enhanced pll pins (part 2 of 2) i/o standard input output inclk fbin pllenable extclk clk13n, i/o, pll11_out or clk6n, i/o, pll12_out (1 ) from internal logic or ioe g 0 counter 1?14 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls stratix and stratix gx devices can drive any enhanced pll driven through the global clock or regional clock network to any general i/o pin as an external output clock. the jitter on the output clock is not guaranteed for these cases. clock feedback the following three feedback modes in stratix and stratix gx device enhanced plls allow multiplication and/or phase shifting: zero delay buffer: the external cl ock output pin is phase-aligned with the clock input pin for zero de lay. altera recommends using the same i/o standard on the input clock and the output clocks for optimum performance. external feedback: the external fe edback input pin, fbin, is phase- aligned with the clock in put, clk, pin. aligning these clocks allows you to remove clock delay and skew between devices. this mode is only possible for plls 5 and 6. pl ls 5 and 6 each support feedback for one of the dedicated external ou tputs, either one single-ended or one differential pair. in this mo de, one encounter feeds back to the pll fbin input, becoming pa rt of the feedback loop. normal mode: if an internal clock is used in this mode, it is phase- aligned to the input cloc k pin. the external cl ock output pin has a phase delay relative to the clock in put pin if connected in this mode. no compensation: in this mode, the pll does not compensate for any clock networks or external clock outputs. table 1?7 shows which modes are supported by which pll type. phase shifting stratix and stratix gx device enhanced plls provide advanced programmable phase shifting. you set these parameters in the quartus ii software. table 1?7. clock feedback mode availability clock feedback mode mode available in enhanced plls fast plls no compensation mode yes yes normal mode yes yes zero delay buffer mode yes no external feedback mode yes no altera corporation 1?15 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices phase delay the quartus ii software automatically sets the phase taps and counter settings according to the phase shift en try. you enter a desired phase shift and the quartus ii software automa tically sets the closest setting achievable. this type of phase shift is not reconfigurable during system operation. for phase shifting, enter a phase shift (in degrees or time units) for each pll clock output port or fo r all outputs together in one shift. you can select phase-shifting values in time units with a resolution of 156.25 to 416.66 ps. this reso lution is a function of frequency input and the multiplication and division factors (t hat is, it is a function of the vco period), with the finest step being equal to an eighth ( 0.125) of the vco period. each clock output counter ca n choose a different phase of the vco period from up to eight taps for individual fine-step selection. also, each clock output counter can use a unique initial count setting to achieve individual coarse-shift selection in steps of one vco period. the combination of coarse and fine shifts allows phase shifting for the entire input clock period. the equation to determin e the precision of the ph ase shifting in degrees is: 45 post-scale counter value. therefore, the maximum step size is 45 , and smaller steps are possible depending on the multiplication and division ratio necessary on the output counter port. this type of phase shift provides the highest precision since it is the least sensitive to process, supply, and temperature variation. lock detect the lock output indicates that there is a stable clock output signal in phase with the reference clock. withou t any additional ci rcuitry, the lock signal may toggle as the pll begins tr acking the reference clock. you may need to gate the lock signal for use as a system control. the lock signal from the locked port can drive the logic array or an output pin. whenever the pll loses lock for any reason (be it excessive inclk jitter, clock switchover, pll reconfiguration, power supply noise, etc.), the pll must be reset with the areset signal to guarantee correct phase relationship between the pll output clocks. if the ph ase relationship between the input clock versus outp ut clock, and between different output clocks from the pll is not im portant in your design, the pll need not be reset. f see the stratix fpga errata sheet for more information on implementing the gated lock signal in your design. 1?16 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls programmable duty cycle the programmable duty cycle allows enhanced plls to generate clock outputs with a variable duty cycle. this featur e is supported on each enhanced pll post-scale counter ( g 0.. g 3, l 0.. l 3, e 0.. e 3). the duty cycle setting is achieved by a low and high time count setting for the post-scale counters. the quartus ii software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. the precision of the duty cycle is determ ined by the post-scale counter value chosen on an output. the precision is defined by 50 % divided by the post- scale counter value. the closest value to 100 % is not achievable for a given counter value. for example, if the g 0 counter is 10, then steps of 5 % are possible for duty cycle choices between 5 to 90 % . if the device uses external feedback , you must set the duty cycle for the counter driving off the device to 50 % . general advanced clear & enable control there are several control signals for clearing and enabling plls and pll outputs. you can use these signals to control pll resynchronization and gate pll output clocks for low-power applications. the pllenable pin is a dedicated pin that enables/disables plls. when the pllenable pin is low, the clock ou tput ports are driven by gnd and all the plls go out of lock. when the pllenable pin goes high again, the plls relock and resynchronize to th e input clocks. you can choose which plls are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. the areset signals are reset/re synchronization inputs for each pll. the areset signal should be asserted ev ery time the pll loses lock to guarantee correct phase relationship between the pll output clocks. users should include the areset signal in designs if any of the following conditions are true: pll reconfiguration or clock switchover enables in the design phase relationships between output clocks need to be maintained after a loss of lock condition the device input pins or logic el ements (les) can drive these input signals. when driven high, the pll counters reset, clearing the pll output and placing the pll out of lock . the vco sets back to its nominal setting (~700 mhz). when driven low again, the pll resynchronizes to its input as it relocks. if the target vco frequency is below this nominal altera corporation 1?17 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices frequency, then the output frequency starts at a higher value than desired as the pll locks. if the syst em cannot tolerate this, the clkena signal can disable the output cloc ks until the pll locks. the pfdena signals control the phase frequency detector (pfd) output with a programmable gate. if you disa ble the pfd, the vco operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. the system continues running when the pll goes out of lock or the input clock is disabled. by maintaining the last locked frequency, the system has time to store its current settings before shutting down. you can either us e your own control signal or a clkloss status signal to trigger pdfena . the clkena signals control the enhanced pll regional and global outputs. each regional and global output port has its own clkena signal. the clkena signals synchronously disable or enable the clock at the pll output port by gating the outputs of the g and l counters. the clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. figure 1?7 shows the waveform example fo r a pll clock port enable. the pll can remain locked independent of the clkena signals since the loop- related counters are not affected. this feature is useful for applications that require a low power or sleep mode. upon re-enabling, the pll does not need a resynchronization or relock period. the clkena signal can also disable clock outputs if the sy stem is not toler ant to frequency overshoot during resynchronization. the extclkena signals work in the same way as the clkena signals, but they control the external clock output counters ( e 0, e 1, e 2, and e 3). upon re-enabling, the pll does not need a resynchronization or relock period unless the pll is using external feedback mode. in order to lock in external feedback mode, the external output must drive the board trace back to the fbin pin. 1?18 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls figure 1?7. extclkena signals programmable bandwidth enhanced plls provide advanced control of the pll bandwidth using the programmable characteristics of th e pll loop, including loop filter and charge pump. background the pll bandwidth is the measure of the plls ability to track the input clock and jitter. it is determined by the ? 3-db frequency of the closed-loop gain in the pll or approximately the unity gain point for open loop pll response. as figure 1?8 shows, these points correspond to approximately the same frequency. counter output clkena clkout altera corporation 1?19 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices figure 1?8. open- & closed -loop response bode plots a high-bandwidth pll provid es a fast lock time and tracks jitter on the reference clock source, passing it through to the pll output. a low- bandwidth pll filters out reference cl ock jitter, but incr eases lock time. stratix device enhanced plls allow you to control the bandwidth over a increasing the pll's bandwidth in effect pushes the open loop response out. gain gain 0 db frequency frequency open-loop reponse bode plot closed-loop reponse bode plot 1?20 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls finite range to customiz e the pll characteristics for a particular application. applications that requ ire clock switchover (such as tdma, frequency hopping wireless, and redu ndant clocking) can benefit from the programmable bandwidth feature of the stratix and stratix gx plls. the bandwidth and stability of such a system is determined by a number of factors including the charge pump current, the loop filter resistor value, the high-frequency capacitor va lue (in the loop filter), and the m - counter value. you can use the quartu s ii software to control these factors and to set the bandwidth to the de sired value within a given range. you can set the bandwidth to the appropriate value to balance the need for jitter filtering and lock time. figures 1?9 and 1?10 show the output of a low- and high-bandwidth pll, respectively, as it locks onto the input clock. figure 1?9. low-bandwidth pll lock time 05 15 10 time ( s) frequency (mhz) 120 125 130 135 140 145 150 155 160 lock time = 8 s altera corporation 1?21 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices figure 1?10. high-bandwidth pll lock time a high-bandwidth pll may benefit a system with two cascaded plls. if the first pll uses spread spectrum (a s user-induced jitter), the second pll needs a high bandwidth so it can tr ack the jitter that is feeding it. a low-bandwidth pll may, in this case, lose lock due to the spread spectrum-induced jitte r on the input clock. a low-bandwidth pll may benefit a system using clock switchover. when the clock switchover happens, the pll input temporarily stops. a low-bandwidth pll would react more slowly to changes to its input clock and take longer to drift to a lo wer frequency (caused by the input stopping) than a hi gh-bandwidth pll. figures 1?11 and 1?12 demonstrate this property. the two plots show the effects of cloc k switchover with a low- or high- bandwidth pll. when the clock swit chover happens, the output of the low-bandwidth pll (see figure 1?11 ) drifts to lower frequency much slower than the high-band width pll output (see figures 1?12 ). 0 120 125 130 135 140 145 150 155 160 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time ( s) frequency (mhz) lock time = 4 s 1?22 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls figure 1?11. effect of low bandwidth on clock switchover 0 150 152 154 156 158 160 162 164 5 10152025303540 time ( s) frequency (mhz) initial lock input clock stops re-lock switchover altera corporation 1?23 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices figure 1?12. effect of high bandwidth on clock switchover implementation traditionally, external components such as the vco or loop filter control a pll?s bandwidth. most loop filters are made up of passive components, such as resistors and capacitors, which take up unnecessary board space and increase cost. with stratix and stratix gx device enhanced plls, all the components are contained within the device to increase performance and decrease cost. stratix and stratix gx device enha nced plls implement programmable bandwidth by giving you control of the charge pump current and loop filter resistor (r) and high-frequency capacitor (c h ) values (see table 1?8 ). the stratix and stratix gx device enhanced pll bandwidth ranges from approximately 150 khz to 2 mhz. 0 125 130 135 140 145 150 155 160 2 4 6 8 10 12 14 16 18 20 time ( s) frequency (mhz) initial lock input clock stops re-lock switchover 1?24 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls the charge pump current directly affects the pll bandwidth. the higher the charge pump current, the higher the pll bandwidth. you can choose from a fixed set of values for the charge pump current. figure 1?13 shows the loop filter and the components that you can set via the quartus ii software. figure 1?13. loop filter programmable components software support the quartus ii software provides tw o levels of programmable bandwidth control. the first level allows you to enter a value for the desired bandwidth directly into the quartus ii software using the megawizard ? plug-in manager. alternat ively, you can set the bandwidth parameter in the altpll function to the desired band width. the quartus ii software then chooses each individual ba ndwidth parameter to achieve the desired setting. if designs cannot ac hieve the desired bandwidth setting, the quartus ii software selects the cl osest achievable value. for preset low, medium, and high bandwidth setti ngs, the quartus ii software sets the bandwidth as follows: low bandwidth is set at 150 khz medium bandwidth is set at 800 khz high bandwidth is set at 2 mhz if you choose auto bandwidth, the qu artus ii software chooses the pll settings and you can get a bandwidt h setting outside the 150-khz to 2-mhz range. i up i dn c h pfd r c altera corporation 1?25 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices an advanced level of control is also possible for precise control of the loop filter parameters. this level allows you to specifically select the charge pump current, loop filter re sistor value, and loop filter (high frequency) capacitor value. these pa rameters are: charge_pump_current, loop_filter_r, and loop_filter_c. ea ch parameter supports the specific range of values listed in table 1?8 . f for more information on pll soft ware support in the quartus ii software, see the altpll megafunction user guide . clock switchover f for more information on implementing clock switchover, see an 313: implementing clock switchover in stratix & stratix gx devices. spread-spectrum clocking digital clocks are generally square waves with short rise times and a 50 % duty cycle. these high-speed digital clocks concentrate a significant amount of energy in a narrow bandwidth at the target frequency and at the higher frequency harmonics. this results in high energy peaks and increased electromagnetic interference (emi). the radiated noise from the energy peaks travels in free air and, if not minimized, can lead to corrupted data and intermittent system errors, which can jeopardize system reliability. background traditional methods for limiting emi include shielding, filtering, and multi-layer printed circuit boards (pcbs). however, these methods significantly increase the overall system cost and sometimes are not enough to meet emi compliance. sp read-spectrum technology provides a simple and effective technique for reducing emi emissions without additional cost and the trou ble of re-designing a board. table 1?8. advanced loop filter parameters parameter values resistor values (k ) 1, 2, 3, 4, 7, 8, 9, 10 high-frequency capacitance values (pf) 5, 10, 15, 20 charge pump current settings ( a) 10, 15, 20, 24, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 100, 112, 135, 148, 164, 212 1?26 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls spread-spectrum technology modulates the target frequency over a small range. for example, if a 100-mhz signal has a 0.5 % down-spread modulation, then the frequency is swept from 99.5 to 100 mhz. figure 1?14 gives a graphical representation of the energy present in a spread-spectrum signal as opposed to a non-spread-spectrum signal. it is apparent that instead of concentrating the energy at the target frequency, the energy is re-distributed across a wider band of frequencies, which reduces peak energy. not only is there a reduction in th e fundamental peak emi components, but there is also a reduction in emi of the higher order harmonics. since some regulations focus on peak emi emissions, rather than average emi emissions, spread-spectrum technolo gy is a valuable method of emi reduction. figure 1?14. spread-spectrum signal energy ve rsus non-spread-spectrum signal energy spread-spectrum technology would benefit a design with high emi emissions and/or strict emi requir ements. device-generated emi is dependent on frequency, output voltage swing amplitude, and slew rate. for example, a design using lvds already has low emi emissions = 0.5 % = ~5 db amplitude (db) frequency (mhz) spread-spectrum signal non-spread-spectrum signal altera corporation 1?27 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices because of the low-voltage swing. th e differential lvds signal also allows for emi rejection within the si gnal. therefore, this situation may not require spread-spectrum technology. description stratix and stratix gx device enha nced plls feature spread-spectrum technology to reduce the emi emitted from the device. the enhanced pll provides up to a 0.5 % down spread (?0.5 % ) using a tria ngular, also known as linear, modulation profil e. the modulation frequency is programmable and ranges from approx imately 30 to 150 khz. the spread percentage is based on the cl ock input to the pll and the m and n settings. spread-spectrum technology reduces th e peak energy by 2 to 5 db at the target frequency. however, this number is dependent on bandwidth and the m and n counter values and can vary from design to design. spread percentage, also known as mo dulation width, is defined as the percentage that the design modulates the target frequency. a negative (?) percentage indicates a down sp read, a positive (+) percentage indicates an up spread, and a ( ) indicates a center spread. modulation frequency is the frequency of the spre ading signal or how fast the signal sweeps from the minimum to the maximum frequency. down-spread modulation shifts the target freq uency down by half the spread percentage, centering the modulated waveforms on a new target frequency. the m and n counter values are toggled at the same time between two fixed values. the loop fi lter then slowly changes the vco frequency to provide the spreading effect, which re sults in a triangular modulation. an additional spread-spectrum counter (shown in figure 1?15 ) sets the modulation frequency. figure 1?15 shows how spread-spectrum technology is implemented in the stratix device enhanced pll. 1?28 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls figure 1?15. spread-spectrum circuit block diagram figure 1?16 shows a vco frequency waveform when toggling between different counter values. since the enhanced pll switches between two different m and n values, the result is a straight line between two frequencies, which gives a linear modulation. the magnitude of modulation is determined by the ratio of two m / n sets. the percent spread is determined by: percent spread = ( f vcomax ? f vcomin )/ f vcomax = 1 ? [( m 2 n 1 )/( m 1 n 2 )] the maximum and minimum vco frequency is defined as: f vcomax = ( m 1 / n 1 ) f ref f vcomin = ( m 2 / n 2 ) f ref n n count1 n count2 pfd up down spread spectrum counter m m count1 m count2 refclk altera corporation 1?29 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices figure 1?16. vco frequency modulation waveforms software support you can enter the desired down-spread percentage and modulation frequency in the megawizard plug-i n manager through the quartus ii software. alternatively, the megawizard plug-in manager can set the downspread parameter in the altpll megafunction to the desired down-spread percentage. timing analys is ensures the design operates at the maximum spread frequency and meets all timing requirements. f for more information on pll software support in the quartus ii software, see the altpll megafunction user guide . guidelines if the design cascades plls, the sour ce, or upstream pll should have a low bandwidth setting, while the dest ination, or downstream pll should have a high bandwidth setting. th e upstream pll must have a low bandwidth setting because a pll does no t generate jitter higher than its bandwidth. the downstream pll must have a high bandwidth setting to track the jitter. the design must use the spread-spectrum feature in a low- bandwidth pll and, therefore, the quar tus ii software automatically sets the spread-spectrum pll?s bandwidth to low. 1 designs cannot use spread-spectrum plls with the programmable bandwidth feature. stratix and stratix gx devices can ac cept a spread-spectrum input with typical modulation frequencies. however, the device cannot automatically detect that the input is a spread-spectrum signal. instead, the input signal looks like determin istic jitter at the input of the downstream pll. spread spectrum should only have a minor effect on period jitter, but period jitter increases. period jitter is the deviation of a clock?s cycle time from its previous cycle position. peri od jitter measures the variation of a clock?s output transition from its ideal position over consecutive edges. count2 values count1 values vco frequency 1?30 altera corporation stratix device handbook, volume 2 july 2005 enhanced plls with down-spread modulation, the pe ak of the modulated waveform is the actual target frequency. therefore, the system never exceeds the maximum clock speed. to maintain reliable communication, the entire system/subsystem should us e the stratix or stratix gx device as the clock source. communication could fail if the stratix or stratix gx logic array is clocked by the spread-spectrum cloc k, but the data it receives from another device is not. since spread spectrum affects the m counter values, all spread-spectrum pll outputs are affected. therefore, if only one spread-spectrum signal is needed, the clock signal should use a separate pll without other outputs from that pll. no special considerations are needed when using spread spectrum with the clock switchover feature. this is because the clock switchover feature does not affect the m and n counter values, which are the counter values that are switching when using spread spectrum. pll reconfiguration f see an 282: implementing pll reconfig uration in stratix & stratix gx devices for information on pll reconfiguration. enhanced pll pins table 1?9 shows the physical pins and their purpose for the enhanced plls. for inclk port connections to pins see ?clocking? on page 1?39 . table 1?9. enhanced pll pins (part 1 of 2) pin description clk4p/n single-ended or differential pins that can drive the inclk port for pll 6. clk5p/n single-ended or differential pins that can drive the inclk port for pll 6. clk6p/n single-ended or differential pins that can drive the inclk port for pll 12. clk7p/n single-ended or differential pins that can drive the inclk port for pll 12. clk12p/n single-ended or differential pins that can drive the inclk port for pll 11. clk13p/n single-ended or differential pins that can drive the inclk port for pll 11. clk14p/n single-ended or differential pins that can drive the inclk port for pll 5. clk15p/n single-ended or differential pins that can drive the inclk port for pll 5. pll5_fbp/n single-ended or differential pins that can drive the fbin port for pll 5. pll6_fbp/n single-ended or differential pins that can drive the fbin port for pll 6. pllenable dedicated input pin that drives the pllena port of all or a set of plls. if you do not use this pin, connect it to ground. altera corporation 1?31 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices fast plls stratix devices contain up to eight fast plls and stratix gx devices contain up to four fast plls. both device plls have high-speed differential i/o interfac e ability along with ge neral-purpose features. figure 1?17 shows a diagram of the fast pll. this section discusses the pll5_out[3..0]p/n single-ended or differential pins driven by extclk[3..0] ports from pll 5. pll6_out[3..0]p/n single-ended or differential pins driven by extclk[3..0] ports from pll 6. pll11_out, clk13n single-ended output pin driven by clk0 port from pll 11. pll12_out, clk6n single-ended output pin driven by clk0 port from pll 12. vcca_pll5 analog power for pll 5. connect this pin to 1.5 v, even if the pll is not used. vccg_pll5 guard ring power for pll 5. connect this pin to 1.5 v, even if the pll is not used. gnda_pll5 analog ground for pll 5. you can connect this pin to the gnd plane on the board. gndg_pll5 guard ring ground for pll 5. you can connect this pin to the gnd plane on the board. vcca_pll6 analog power for pll 6. connect this pin to 1.5 v, even if the pll is not used. vccg_pll6 guard ring power for pll 6. connect this pin to 1.5 v, even if the pll is not used. gnda_pll6 analog ground for pll 6. you can connect this pin to the gnd plane on the board. gndg_pll6 guard ring ground for pll 6. you can connect this pin to the gnd plane on the board. vcca_pll11 analog power for pll 11. connect this pin to 1.5 v, even if the pll is not used. vccg_pll11 guard ring power for pll 11. connect this pin to 1.5 v, even if the pll is not used. gnda_pll11 analog ground for pll 11. you can connect this pin to the gnd plane on the board. gndg_pll11 guard ring ground for pll 11.you can connect this pin to the gnd plane on the board. vcca_pll12 analog power for pll 12. connect this pin to 1.5 v, even if the pll is not used. vccg_pll12 guard ring power for pll 12. connect this pin to 1.5 v, even if the pll is not used. gnda_pll12 analog ground for pll 12. you can connect this pin to the gnd plane on the board. gndg_pll12 guard ring ground for pll 12. you can connect this pin to the gnd plane on the board. vcc_pll5_outa external clock output v ccio power for pll5_out0p , pll5_out0n , pll5_out1p , and pll5_out1n outputs from pll 5. vcc_pll5_outb external clock output v ccio power for pll5_out2p , pll5_out2n , pll5_out3p , and pll5_out3n outputs from pll 5. vcc_pll6_outa external clock output v ccio power for pll5_out0p , pll5_out0n , pll5_out1p , and pll5_out1n outputs from pll 6. vcc_pll6_outb external clock output v ccio power for pll5_out2p , pll5_out2n , pll5_out3p , and pll5_out3n outputs from pll 6. table 1?9. enhanced pll pins (part 2 of 2) pin description 1?32 altera corporation stratix device handbook, volume 2 july 2005 fast plls general purpose abilities of the fast pll. for information on the high- speed differential i/o interface capabilities, see the high-speed differential i/o interfaces in stratix devices chapter. figure 1?17. stratix & stratix gx fast pll block diagram notes to figure 1?17 : (1) the global or regional clock input can be driven by an output from another pll or any dedicated clk or fclk pin. it cannot be driven by intern ally-generated global signals. (2) in high-speed differential i/o support mode, this high-s peed pll clock feeds the serdes. stratix and stratix gx devices only support one rate of da ta transfer per fast pll in high-s peed differential i/o support mode. (3) this signal is a high-speed differential i/o support serdes control signal. char g e pump vco g 0 8 clock input pfd l 1 l 0 m loop filter p h ase f req u e n c y detect o r v co p h ase se l ect ion se l ectab l e at eac h p ll o u tp u t p o rt p o st - sca l e c oun ters global or re g ional clock global or re g ional clock global or re g ional clock diffioclk2 ( 2 ) diffioclk1 ( 2 ) txload_en ( 3 ) rxload_en ( 3 ) global or re g ional clock (1) altera corporation 1?33 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices figure 1?18 shows all possible ports related to fast plls. figure 1?18. fast pll ports & physical destinations notes to figure 1?18 : (1) this input pin is shared by all enhanced and fast plls. (2) this input pin is either single-ended or differential. tables 1?10 and 1?11 show the description of all fast pll ports. clk[2..0] locked pllena inclk0 areset pfdena fast pll si g nals (1) ( 2 ) physical pin si g nal driven by internal lo g ic si g nal driven to internal lo g ic internal clock si g nal table 1?10. fast pll input signals name description source destination inclk1 reference clock input to pll pin pfd pllena enable pin for enabling or disabling all or a set of plls ? active high pin pll control signal areset signal used to reset the pll which re- synchronizes all the counter outputs ? active high logic array pll control signal pfdena enables the up/down outputs from the phase- frequency detector ? active high logic array pfd table 1?11. fast pll output signals name description source destination clk[2..0] pll outputs driving regional or globa l clock pll counter internal clock locked lock output from lock detect circuit ? active high pll lock detect logic array 1?34 altera corporation stratix device handbook, volume 2 july 2005 fast plls clock multiplication & division stratix and stratix gx device fast plls provide clock synthesis for pll output ports using m /(post scaler) scaling fac tors. the input clock is multiplied by the m feedback factor. each output port has a unique post scale counter to divide down the high-frequency vco. there is one multiply counter, m , per fast pll with a range of 1 to 32. there are three post-scale counters ( g 0, l 0, and l 1) for the regional and global clock output ports. all post-scale counters range from 1 to 32. if the design uses a high-speed serial interf ace, you can set the output counter to 1 to allow the high-speed vco frequency to drive the serdes. external clock outputs each fast pll supports differential or single-ended outputs for source- synchronous transmitters or for gene ral-purpose external clocks. there are no dedicated external clock outp ut pins. the fast pll global or regional outputs can drive any i/o pin as an external clock output pin. the i/o standards supported by any particular bank determines what standards are possible for an external clock output driven by the fast pll in that bank. see the selectable i/o standards in stratix & stratix gx devices chapter in the stratix device handbook, volume 2 or the stratix gx device handbook, volume 2 for output standard support. table 1?12 shows the i/o standards supported by fast pll input pins. table 1?12. fast pll port i/o standards (part 1 of 2) i/o standard input inclk pllenable lv t t l vv lv c m o s vv 2.5 v v 1.8 v v 1.5 v v 3.3-v pci 3.3-v pci-x 1.0 lvpecl v pcml v lv d s v hypertransport technology v differential hstl v altera corporation 1?35 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices phase shifting stratix and stratix gx device fast pl ls have advanced clock shift ability to provide programmable phase shift. these parameters are set in the quartus ii software. the quartus ii software automatically sets the phase taps and counter settings according to the phase shift en try. enter a desired phase shift and the quartus ii software automatically sets the closest setting achievable. this type of phase shift is not reco nfigurable during system operation. you can enter a phase shift (in degrees or time units) for each pll clock output port or for all outputs togethe r in one shift. you can perform phase shifting in time units with a resolu tion range of 125 to 416.66 ps to create a function of frequency input and th e multiplication and division factors (that is, it is a function of the vco pe riod), with the finest step being equal to an eighth ( 0.125) of the vco period. each clock output counter can choose a different phase of the vco period from up to eight taps for individual fine-step selection. also, each clock output counter can use a unique initial count setting to achieve individual coarse shift selection in steps of one vco period. the combin ation of coarse and grain shifts allows phase shifting for th e entire input clock period. differential sstl 3.3-v gtl 3.3-v gtl+ v 1.5-v hstl class i v 1.5-v hstl class ii 1.8-v hstl class i v 1.8-v hstl class ii sstl-18 class i v sstl-18 class ii sstl-2 class i v sstl-2 class ii v sstl-3 class i v sstl-3 class ii v agp (1 and 2 ) ctt v table 1?12. fast pll port i/o standards (part 2 of 2) i/o standard input inclk pllenable 1?36 altera corporation stratix device handbook, volume 2 july 2005 fast plls the equation to determine the prec ision of phase in degrees is: 45 post- scale counter value. therefore, the maximum step size is 45 , and smaller steps are possible depending on the multiplication and division ratio necessary on the output counter port. this type of phase shift provides the highest precision since it is the least sensitive to process, supply, and temperature variation. programmable duty cycle the programmable duty cycle allows the fast pll to generate clock outputs with a variable duty cycle. th is feature is supported on each fast pll post-scale counter. g 0, l 0, and l 1 all support prog rammable duty. you use a low- and high-time count setting for the post-scale counters to set the duty cycle. the quartus ii software uses the frequency input and multiply/divide rate desired to select the post-sca le counter, which determines the possible choices for each duty cycle. the precision of the duty cycle is determined by the post-scale counte r value chosen on an output. the precision is defined by 50 % divided by the post-scale counter value. the closest value to 100 % is not achievable for a given counter value. for example, if the g 0 counter is 10, then steps of 5 % are possible for duty cycle choices between 5 to 90 % . if the device uses external feedback , you must set the duty cycle for the counter driving off the device to 50 % . control signals the lock output indicates a stable clock output signal in phase with the reference clock. unlike enhanced plls, fast plls do not have a lock filter counter. the pllenable pin is a dedicated pin that enables/disables both plls. when the pllenable pin is low, the clock ou tput ports are driven by gnd and all the plls go out of lock. when the pllenable pin goes high again, the plls relock and resync hronize to the input clocks. you can choose which plls are controlled by the pllenable by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. the areset signals are reset/resynchronization inputs for each fast pll. the stratix and stratix gx devices can drive these input signals from an input pin or from les. when driven high, the pll counters reset, clearing the pll output and placing the pll ou t of lock. the vco sets back to its nominal setting (~700 mhz). when driven low again, the pll altera corporation 1?37 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices resynchronizes to its input clock as it relocks. if the target vco frequency is below this nominal frequency, then the output frequency starts at a higher value then desired as it locks. the pfdena signals control the pfd output with a programmable gate. if you disable the pfd, the vco operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. the system continues running when the pll goes out of lock or the input clock disables. by maintaining the last locked frequency, the system has time to store its current se ttings before shutting down. if the pll loses lock for any reason (for example, because of excessive inclk jitter, clock switchover, pll reconfiguration, or power supply noise), the pll must be reset with the areset signal to guarantee correct phase relationship between the pl l output clocks. if the phase relationship between the input cloc k and the output clock and between different output clocks from the pll is not important in your design, it is not necessary to reset the pll. pins table 1?13 shows the physical pins and th eir purpose for the fast plls. for inclk port connections to pins see ?clocking? on page 1?39 . table 1?13. fast pll pins (part 1 of 3) pin description clk0p/n single-ended or differential pins that c an drive the inclk port for pll 1 or 7. clk1p/n single-ended or differential pins that can drive the inclk port for pll 1. clk2p/n single-ended or differential pins that c an drive the inclk port for pll 2 or 8. clk3p/n single-ended or differential pins that can drive the inclk port for pll 2. clk8p/n single-ended or differential pins that c an drive the inclk port for pll 3 or 9. (1) clk9p/n single-ended or differential pins that can drive the inclk port for pll 3. (1) clk10p/n single-ended or differential pins that c an drive the inclk port for pll 4 or 10. (1) clk11p/n single-ended or differential pins that can drive the inclk port for pll 4. (1) fpll7clkp/n single-ended or differential pins that can drive the inclk port for pll 7. fpll8clkp/n single-ended or differential pins that can drive the inclk port for pll 8. fpll9clkp/n single-ended or differential pins that can drive the inclk port for pll 9. (1) fpll10clkp/n single-ended or differential pins that can drive the inclk port for pll 10. (1) pllenable dedicated input pin that drives the pllena port of all or a set of plls. if you do not use this pin, connect it to ground. vcca_pll1 analog power for pll 1. connect this pin to 1.5 v, even if the pll is not used. 1?38 altera corporation stratix device handbook, volume 2 july 2005 fast plls vccg_pll1 guard ring power for pll 1. connect this pin to 1.5 v, even if the pll is not used. gnda_pll1 analog ground for pll 1. you can connect this pin to the gnd plane on the board. gndg_pll1 guard ring ground for pll 1. you can connect this pin to the gnd plane on the board. vcca_pll2 analog power for pll 2. connect this pin to 1.5 v, even if the pll is not used. vccg_pll2 guard ring power for pll 2. connect this pin to1.5 v, even if the pll is not used. gnda_pll2 analog ground for pll 2. you can connect this pin to the gnd plane on the board. gndg_pll2 guard ring ground for pll 2. you can connect this pin to the gnd plane on the board. vcca_pll3 analog power for pll 3. connect this pin to 1.5 v, even if the pll is not used. (1) vccg_pll3 guard ring power for pll 3. connect this pin to 1.5 v, even if the pll is not used. (1) gnda_pll3 analog ground for pll 3. you can connect this pin to the gnd plane on the board. (1) gndg_pll3 guard ring ground for pll 3. you can connect this pin to the gnd plane on the board. (1) vcca_pll4 analog power for pll 4. connect this pin to 1.5 v, even if the pll is not used. (1) vccg_pll4 guard ring power for pll 4. connect this pin to 1.5 v, even if the pll is not used. (1) gnda_pll4 analog ground for pll 4. you can connect this pin to the gnd plane on the board. (1) gndg_pll4 guard ring ground for pll 4. you can connect this pin to the gnd plane on the board. (1) vcca_pll7 analog power for pll 7. connect this pin to 1.5 v, even if the pll is not used. vccg_pll7 guard ring power for pll 7. connect this pin to 1.5 v, even if the pll is not used. gnda_pll7 analog ground for pll 7. you can connect this pin to the gnd plane on the board. gndg_pll7 guard ring ground for pll 7. you can connect this pin to the gnd plane on the board. vcca_pll8 analog power for pll 8. connect this pin to 1.5 v, even if the pll is not used. vccg_pll8 guard ring power for pll 8. connect this pin to 1.5 v, even if the pll is not used. gnda_pll8 analog ground for pll 8. you can connect this pin to the gnd plane on the board. gndg_pll8 guard ring ground for pll 8. you can connect this pin to the gnd plane on the board. vcca_pll9 analog power for pll 9. connect this pin to 1.5 v, even if the pll is not used. (1) vccg_pll9 guard ring power for pll 9. connect this pin to 1.5 v, even if the pll is not used. (1) table 1?13. fast pll pins (part 2 of 3) pin description altera corporation 1?39 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices clocking stratix and stratix gx devices provide a hierarchical clock structure and multiple plls with advanced features. the large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast plls provides a co mplete clock mana gement solution. global & hierarchical clocking stratix and stratix gx devices pr ovide 16 dedicated global clock networks, 16 regional clock networks (4 per device quadrant), and 8 dedicated fast regional clock netw orks. these clocks are organized into a hierarchical clock structure that al lows for up to 22 cl ocks per device region with low skew and delay. this hierarchical clocking scheme provides up to 48 unique clock doma ins within stratix and stratix gx devices. there are 16 dedicated clock pins ( clk[15..0] ) on stratix devices and 12 dedicated clock pins ( clk[11..0] ) on stratix gx devices to drive either the global or regional clock networks. four clock pins drive each side of the stratix device, as shown in figures 1?19 and 1?20 . on stratix gx devices, four clock pins drive th e top, left, and bottom sides of the device. the clocks on the right side of the device are not available for general-purpose plls. enha nced and fast pll outputs can also drive the global and regional clock networks. gnda_pll9 analog ground for pll 9. you can connect this pin to the gnd plane on the board. (1) gndg_pll9 guard ring ground for pll 9. you can connect this pin to the gnd plane on the board. (1) vcca_pll10 analog power for pll 10. connect this pi n to 1.5 v, even if the pll is not used. (1) vccg_pll10 guard ring power for pll 10. connect this pin to 1.5 v, even if the pll is not used. (1) gnda_pll10 analog ground for pll 10. connect this pin to the gnd plane on the board. (1) gndg_pll10 guard ring ground for pll 10. you can connect this pin to the gnd plane on the board. (1) note to table 1?13 : (1) plls 3, 4, 9, and 10 are not available on stratix gx de vices for general-purpose config uration. these plls are part of the hssi block. see an 236: using source-synchronous signaling with dpa in stratix gx devices for more information. table 1?13. fast pll pins (part 3 of 3) pin description 1?40 altera corporation stratix device handbook, volume 2 july 2005 clocking global clock network these clocks drive throughout the entire device, feeding all device quadrants. all resources within the device?ioes, les, dsp blocks, and all memory blocks?can us e the global clock networ ks as clock sources. these resources can also be used for control signals, such as clock enables and synchronous or asynchronous cl ears fed from the external pin. internal logic can also drive the gl obal clock networks for internally generated global clocks and asynchrono us clears, clock enables, or other control signals with large fanout. figure 1?19 shows the 16 dedicated clk pins driving global clock networks. figure 1?19. global clocking regional clock network there are four regional clock networks within each quadrant of the stratix or stratix gx device that are driven by the same dedicated clk[15..0] input pins or from pll outputs. from a top view of the silicon, rclk[0..3] are in the top-left quadrant, rclk[8..11] are in the top-right quadrant, rclk[4..7] are in the bottom-left quadrant, and global clock [15..0] clk[15..12] clk[3..0] clk[7..4] clk[11..8] global clock [15..0] altera corporation 1?41 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices rclk[12..15] are in the bottom-right quadrant. the regional clock networks only pertain to the quadrant they drive into. the regional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant. rclk clock networks cannot be driven by internal logic. the clk clock pins symmetrically drive the rclk networks within a particular qu adrant, as shown in figure 1?20 . see figures 1?21 and 1?22 for rclk connections from plls and clk pins. figure 1?20. regional clocks clock input connections two clk pins drive each enhanced pll. you can use either one or both pins for clock switchover inputs in to the pll. either pin can be the primary clock source for clock switchover, which is controlled in the quartus ii software. enhanced plls 5 and 6 also have feedback input pins as shown in table 1?14 . rc lk[1..0] rc lk[4..5] rc lk[6..7] rc lk[1 2 ..1 3 ] rc lk[ 2 .. 3 ] rc lk[11..10] rc lk[14..15] rc lk[9.. 8 ] clk[15..12] clk[3..0] clk[7..4] clk[11..8] reg ion a l c lo c k s o nly dr iv e a de vi ce qu adra n t fr o m spec i f i ed c lk p in s o r p ll s wi t hin t h at qu adra n t 1?42 altera corporation stratix device handbook, volume 2 july 2005 clocking input clocks for fast plls 1, 2, 3, and 4 come from clk pins. stratix gx devices use plls 3 and 4 in the hssi block only. a multiplexer chooses one of two possible clk pins to drive each pll. this multiplexer is not a clock switchover multiplexer and is only used for clock input connectivity. either a fpllclk input pin or a clk pin can drive the fast plls in the corners (7, 8, 9, and 10) when used for general purpose. clk pins cannot drive these fast plls in high-speed differential i/o mode. plls 9 and 10 are used for the hssi block in stra tix gx devices and are not available. table 1?14 shows which plls are availabl e for each stratix device and which input clock pin drives which plls. table 1?14. stratix clock input source s for enhanced & fast plls (part 1 of 2) clock input pins all stratix devices ep1s30, ep1s40, ep1s60 & ep1s80 devices only ep1s40 (3) , ep1s60 & ep1s80 devices only pll 1 (1) pll 2 (1) pll 3 (1) pll 4 (1) pll 5 (2) pll 6 (2) pll 7 (1) pll 8 (1) pll 9 (1) pll 10 (1) pll 11 (2) pll 12 (2) clk0p/n vv clk1p/n v clk2p/n vv clk3p/n v clk4p/n v clk5p/n v clk6p/n v clk7p/n v clk8p/n vv clk9p/n v clk10p/n vv clk11p/n v clk12p/n v clk13p/n v clk14p/n v clk15p/n v altera corporation 1?43 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices clock output connections enhanced plls have outputs for tw o regional clock outputs and four global outputs. there is line shar ing between clock pins, global and regional clock networks an d all pll outputs. check tables 1?15 and 1?16 and figures 1?21 and 1?22 to make sure that the cl ocking scheme is valid. the quartus ii software automatically maps to regional and global clocks to avoid any restrictions. enhanced plls 5 and 6 drive out to single- ended pins as shown in table 1?15 . plls 11 and 12 drive out to single- ended pins. you can connect each fast pll 1, 2, 3, or 4 outputs ( g 0, l 0, and l 1) to either a global or a regional clock. (plls 3 and 4 are not available on stratix gx devices.) there is line sharing between clock pins, fpllclk pins, global and regional clock networks and all pll outputs. check figures 1?21 and 1?22 to make sure that the clocking is valid. the quartus ii software automatically maps to regional and global clocks to avoid any restrictions. fpll7clk v fpll8clk v fpll9clk v fpll10clk v clock feedback input pins pll5_fbp/n v pll6_fbp/n v notes to table 1?14 : (1) this is a fast pll. the global or regional clocks in a fa st pll?s quadrant can drive the fast pll input. a pin or other pll must drive the global or regional source. the source cannot be driven by internally generated logic before driving the fast pll. (2) this is an enhanced pll. (3) the ep1s40 device in the f780 package does not support plls 11 and 12. table 1?14. stratix clock input source s for enhanced & fast plls (part 2 of 2) clock input pins all stratix devices ep1s30, ep1s40, ep1s60 & ep1s80 devices only ep1s40 (3) , ep1s60 & ep1s80 devices only pll 1 (1) pll 2 (1) pll 3 (1) pll 4 (1) pll 5 (2) pll 6 (2) pll 7 (1) pll 8 (1) pll 9 (1) pll 10 (1) pll 11 (2) pll 12 (2) 1?44 altera corporation stratix device handbook, volume 2 july 2005 clocking table 1?15 shows the global and regional clocks that each pll drives outputs to for stratix devices. table 1?16 shows the global and regional clock network each of the clk and fpllclk pins drive when bypassing the pll. table 1?15. stratix global & regional clock output line sharing for enhanced & fast plls (part 1 of 2) clock network all devices ep1s30, ep1s40, ep1s60 & ep1s80 devices only ep1s40 (5) , ep1s60 & ep1s80 devices only pll 1 (1) pll 2 (1) pll 3 (1) pll 4 (1) pll 5 (2) pll 6 (2) pll 7 (1) pll 8 (1) pll 9 (1) pll 10 (1) pll 11 (2) pll 12 (2) gclk0 vv vv gclk1 vv vv gclk2 vv vv gclk3 vv vv gclk4 vv gclk5 vv gclk6 vv gclk7 vv gclk8 vv vv gclk9 vv vv gclk10 vv vv gclk11 vv vv gclk12 vv gclk13 vv gclk14 vv gclk15 vv rclk0 vv v rclk1 vv v rclk2 vv rclk3 vv rclk4 vv v rclk5 vv v altera corporation 1?45 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices rclk6 vv rclk7 vv rclk8 vv v rclk9 vv v rclk10 vv rclk11 vv rclk12 vv rclk13 vv rclk14 vv v rclk15 vv v external clock output pll5_out [3..0]p/n v pll6_out [3..0]p/n v pll11_out (3) v pll12_out (4) v notes to table 1?15 : (1) this is a fast pll. (2) this is an enhanced pll. (3) this pin is a tri-purpose pi n; it can be an i/o pin, clk13n , or used for pll 11 output. (4) this pin is a tri-purpose pi n; it can be an i/o pin, clk7n , or used for pll 12 output. (5) the ep1s40 device in the f780 package does not support plls 11 and 12. table 1?15. stratix global & regional clock output line sharing for enhanced & fast plls (part 2 of 2) clock network all devices ep1s30, ep1s40, ep1s60 & ep1s80 devices only ep1s40 (5) , ep1s60 & ep1s80 devices only pll 1 (1) pll 2 (1) pll 3 (1) pll 4 (1) pll 5 (2) pll 6 (2) pll 7 (1) pll 8 (1) pll 9 (1) pll 10 (1) pll 11 (2) pll 12 (2) 1?46 altera corporation stratix device handbook, volume 2 july 2005 clocking table 1?16. stratix clk & fpllclk input pin connections to globa l & regional clock networks note (1) clock network clk pins fpllclk (2) 012345678910111213141578910 gclk0 vvv gclk1 vvv gclk2 vvv gclk3 vvv gclk4 v gclk5 v gclk6 v gclk7 v gclk8 vvv gclk9 vvv gclk10 vvv gclk11 vvv gclk12 v gclk13 v gclk14 v gclk15 v rclk0 vv rclk1 vv rclk2 vv rclk3 vv rclk4 v rclk5 v rclk6 v rclk7 v rclk8 vv rclk9 vv rclk10 vv rclk11 vv rclk12 v altera corporation 1?47 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices the fast plls also drive high-speed serdes clocks for differential i/o interfacing. for information on these fpllclk pins, see the high-speed differential i/ o interfaces in stratix devices chapter. figure 1?21 shows the global and region al clock input and output connections from the enhanced. figure 1?21 shows graphically the same information as tables 1?15 and 1?16 but with the added detail of where each specific pll output port drives to. rclk13 v rclk14 v rclk15 v notes to table 1?16 : (1) the clk and fpllclk pins cannot drive. (2) the fpllclk pin is only available in ep1s80, ep1s60, ep1s40, and ep1s30 devices. table 1?16. stratix clk & fpllclk input pin connections to globa l & regional clock networks note (1) clock network clk pins fpllclk (2) 012345678910111213141578910 1?48 altera corporation stratix device handbook, volume 2 july 2005 clocking figure 1?21. global & regional cl ock connections from side cloc k pins & fast pll outputs notes to figures 1?21 : (1) the global or regional clocks in a fast pll?s quadrant can drive the fast pll input. a dedicated pin or other pll must drive the global or regional source. the source cannot be driven by internally ge nerated logic before driving the fast pll. (2) plls 3, 4, 9, and 10 are used for the hssi block in stratix gx devices and are not available for this use. when using a fast pll to compensate for clock delays to drive logic on the chip, the clock delay from the inpu t pin to the clock input port of the pll is compensated only if the clock is fed by the dedicated input pin closest to the pll. if the fast pll ge ts its input clock from a global or regional clock or from another de dicated clock pin, which does not directly feed the fast pll, the clock signal is first routed onto a global clock network. the signal then drives into the pll. in this case, the clock delay is not fully compensated and the delay compensation is equal to the clock delay from the dedicated clock pin closest to the pll to the clock input port of the pll. for example, if you use clk0 to feed pll 7, the input clock path delay is not fully compensated, but if fpll7clk feeds pll 7, the input clock path delay is fully compensated. figure 1?22 shows the global and region al clock input and output connections from the fast plls. figure 1?22 shows graphically the same information as tables 1?15 and 1?16 but with the added detail of where each specific pll output port drives to. 2 clk0 clk1 clk2 clk3 g0 fpll7clk g1 g2 g3 rclk0 rclk1 rclk4 rclk5 g10 g11 g8 g9 rclk9 rclk8 rclk15 rclk14 g lo ba l c lo c k s reg ion a l c lo c k s pll 7 l 0 l 1 g 0 pll 1 pll 2 fpll8clk pll 8 2 clk10 clk11 clk8 clk9 fpll10cl k pll 10 pll 4 pll 3 fpll9clk pll 9 reg ion a l c lo c k s l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 l 0 l 1 g 0 altera corporation 1?49 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices figure 1?22. global & regional cl ock connections from top cloc k pins & enhanced pll outputs notes to figures 1?22 : (1) clk4 , clk6 , clk12 , and clk14 feed the corresponding pll?s inclk0 port. (2) clk5 , clk7 , clk13 , and clk15 feed the corresponding pll?s inclk1 port. g12 g13 g14 g15 rclk10 rclk11 rclk2 rclk3 g7 g6 g5 g4 rclk13 rclk12 rclk7 rclk6 pll 12 l0 l1 g0 g1 g2 g3 clk7 clk6 clk5 clk4 pll 6 g0 g1 g2 g3 l0 l1 pll 11 l0 l1 g0 g1 g2 g3 clk13 clk12 clk14 clk15 pll 5 g0 g1 g2 g3 l0 l1 e[0..3] pll12_out pll6_ou t[3..0] pll11_out pll5_out[3..0] pll5_fb pll6_fb g lo ba l c lo c k s reg ion a l c lo c k s reg ion a l c lo c k s (1) ( 2 ) (1) ( 2 ) ( 2 ) ( 2 ) (1) (1) 1?50 altera corporation stratix device handbook, volume 2 july 2005 board layout board layout the enhanced and fast pll circuits in stratix and stratix gx devices contain analog components embedded in a digital device. these analog components have separate power an d ground pins to minimize noise generated by the digital componen ts. both stratix and stratix gx enhanced and fast plls use separate vcc and ground pins to isolate circuitry and improve noise resistance. vcca & gnda each enhanced and fast pll uses separate vcc and ground pin pairs for their analog circuitry. the analog ci rcuit power and ground pin for each pll is called pll < pll number > _vcca and pll < pll number > _gnda . connect the vcca power pin to a 1.5-v power su pply, even if you do not use the pll. isolate the power connected to vcca from the power to the rest of the stratix and stratix gx devi ce or any other digital device on the board. you can use one of three different methods of isolating the vcca pin: separate v cca power planes, a partitioned v cca island within the v ccint plane, and thick v cca traces. separate v cca power plane a mixed signal system is already partitioned into analog and digital sections, each with its own power pl anes on the board. to isolate the vcca pin using a separate v cca power plane, connect the vcca pin to the analog 1.5-v power plane. partitioned v cca island within v ccint plane fully digital systems do not have a separate analog power plane on the board. because it is expensive to add new planes to the board, you can create islands for vcca_pll . figure 1?23 shows an example board layout with an analog power island. the di electric boundary that creates the island should be 25 mils thick. figure 1?23 shows a partitioned plane within v ccint for v cca . altera corporation 1?51 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices figure 1?23. v ccint plane partitioned for v cca island thick v cca trace because of board constraints, you might not be able to partition a v cca island. instead, run a thick trac e from the power supply to each v cca pin. the traces should be at least 20 mils thick. in each of these three cases, you should filter each v cca pin with a decoupling circuit shown in figure 1?24 . place a ferrite bead that exhibits high impedance at frequencies of 50 mhz or higher and a 10- f tantalum parallel capacitor where the power enters the board. decouple each v cca pin with a 0.1- f and 0.001- f parallel combination of ceramic capacitors located as close as possible to the stratix or stratix gx device. you can connect the gnda pins directly to the same gr ound plane as the device?s digital ground. 1?52 altera corporation stratix device handbook, volume 2 july 2005 board layout figure 1?24. pll power schematic fo r stratix or st ratix gx plls vccg & gndg the guard ring power and ground pins are called pll < pll number > _vccg and pll < pll number > _gndg . the guard ring isolates the pll circuit from the rest of the device. connect these guard ring v ccg pins to the quietest digital supply on the board. in most systems, this is the digital 1.5-v supply supplied to the device's v ccint pins. connect the v ccg pins to a power supply even if you do not use the pll. you can connect the gndg pins directly to the same ground plane as the device?s digital ground. see figure 1?24 . 0.1 f 0.001 f 10 f ferrite bead 1.5-v suppl y stratix device pll< pll number >_vcca pll< pll number >_gnda pll< pll number >_vccg pll< pll number >_gndg repeat f o r e ac h p ll p ow er a n d gr oun d set v ccint altera corporation 1?53 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices external clock output power enhanced plls 5 and 6 also have isol ated power pins for their dedicated external clock outputs ( vcc_pll5_outa and vcc_pll5_outb , or vcc_pll6_outa and vcc_pll6_outb , respectively). pl ls 5 and 6 both have two banks of outputs. each bank is powered by a unique output power, outa or outb , as illustrated in figure 1?25 . these outputs can by powered by 3.3, 2.5, 1.8, or 1.5 v depending on the i/o standard for the clock output in the a or b groups. 1?54 altera corporation stratix device handbook, volume 2 july 2005 board layout figure 1?25. external clock output pi n association to output power note (1) note to figure 1?25 : (1) these pins apply to pll 5. the figure for pll 6 is similar, except that the pin names begin with the prefix pll6 instead of pll5 . pll5_out0p vcc_pll5_outa pll5_out0n pll5_out0p pll5_out0n pll5_out2p vcc_pll5_outb pll5_out2n pll5_out3p pll5_out3n altera corporation 1?55 july 2005 stratix device handbook, volume 2 general-purpose plls in stratix & stratix gx devices filter each isolated power pin with a decoupling circuit shown in figure 1?26 . decouple the isolated power pins with a 0.1- f and a 0.001- f parallel combination of ceramic capacitors located as close as possible to the stratix device. figure 1?26. stratix pll external cl ock output power ball connections note (1) note to figure 1?26 : (1) figure 1?26 also applies to vcc_pll6_outa/b . vcc_pll5_outa v ccio supply stratix device vcc_pll5_outb 0.1 f 0.001 f 0.1 f 0.001 f 1?56 altera corporation stratix device handbook, volume 2 july 2005 conclusion guidelines use the following guidelines for optimal jitter performance on the external clock outputs from enhanced plls 5 and 6. if all outputs are running at the same frequency, these guidelines are not necessary to improve performance. when driving two or more clock outputs from pll 5 or 6, separate the outputs into the two groups shown in figure 1?24 . for example, if you are driving 100- and 200-mhz clock outputs off-chip from pll 5, place one output on pll5_out0p (powered by vcc_pll5_outa ) and the other output on pll5_out2p (powered by vcc_pll5_outb ). since the output buffers are powered by different pins, they are less susceptible to bimodal jitter. bimodal jitter is a deterministic jitter not caused by the pll but rather by coincident edges of clock outputs that are multiples of each other. use phase shift to ensure edges are not coincident on all the clock outputs. use phase shift to skew clock edges with respect to each other for best jitter performance. 1 delay shift (time delay elements) are no longer supported in stratix plls. use the phase shift feature to implement the desired time shift. if you cannot drive multiple clocks of different frequencies and phase shifts or isolate banks, you should control the drive capability on the lower frequency clock. reducing how much current the output buffer has to supply can reduce the noise. minimize capacitive load on the slower fr equency output and configure the output buffer to drive slow slew rate and lower current strength. the higher frequency output should ha ve an improved performance, but this may degrade the performance of your lower frequency clock output. conclusion stratix and stratix gx device enhanced plls provide you with complete control of your clocks and system timing. these plls are capable of offering flexible system level clock management that was previously only available in discrete pll devices. the embedded plls meet and exceed the features offered by these high-end discrete devices, reducing the need for other timing devices in the system. altera corporation section ii?1 section ii. memory this section provides information on the trimatrix ? embedded memory blocks internal to stratix ? devices and the supported external memory interfaces. it contains the fo llowing chapters: chapter 2, trimatrix embedded memory blocks in stratix & stratix gx devices chapter 3, external memory inte rfaces in stratix & stratix gx devices the qdr sram controller reference design for stratix & stratix gx devices chapter is removed in this version of the stratix device handbook . the information is available in an 349: interfacing qdr sram with stratix and stratix gx devices . revision history the table below shows th e revision history for chapters 2 and 3 . chapter date/version changes made comments 2 july 2005, v3.3 updated ?implementing true dual-port mode? section. january 2005, v3.2 minor technical content update. september 2004, v3.1 updated note 1 in figure 2?12 on page 2?22 . updated description about using two different clocks in a dual-port ram on page 2?27 . deleted description of m-ram block and document references on page 2?27 . april 2004, v3.0 synchronous occurrences are renamed to pipelined. pseudo-synchronous occurrenc es are renamed flow- through. added and gate to figure 2?12 . july 2003, v2.0 updated performance specification for trimatrix memory in table 2-1. added addressing example for a ram that is using mixed-width mode, page 2-9. added note 1 to tables 2-9 and 2-10, note 3 to figure 2- 11, and note 2 to figures 2-12 and 2-13. section ii?2 altera corporation memory stratix device handbook, volume 2 3 june 2006, v3.3 changed the name of the chapter from external memory interfaces to external memory interfaces in stratix & stratix gx devices to reflect its shared status between those device handbooks. added cross reference regardi ng frequency limits for 72 and 90 phase shift for dqs. july 2005, v3.2 updated mathematical symbols in table 3?3 . updated ?dqs phase-shift circuitry? section. september 2004, v3.1 moved figure 8 to become figure 1, ?example of where a dqs signal is center-aligned in the ioe? on page 3?3 . updated table 3?1 on page 3?10 , updated note 4. note 4, 5, and 6, are now note 5, 6, and 7, respectively. updated table 3?2 on page 3?10 . updated table 3?3 on page 3?13 . updated note on page 3?14 . moved the ?external memory standards? on page 3?1 to follow the introduction section. moved ?conclusion? on page 3?27 to end of chapter. april 2004, v3.0 chapter renamed chapter 3, external memory interfaces in stratix & stratix gx devices . table 3?1 : ddr sdram - side banks row added, zbt sram row updated. added tables 3?2 and 3?4 . dqsn pins removed (page 3-5) deleted ?qdr sram interfacing? figure. replaced ?t zx & t xz timing diagram.? november 2003, v2.1 removed support for series and parallel on-chip termination. july 2003, v2.0 altddio_bidir function is used for dqs in versions before quartus ii 3.0. (page 3-2) updated naming convention for dqs pins on page 3-9 to match pin tables. clarified input clock to pll must come from an external input pin on page 3-12. chapter date/version changes made comments altera corporation 2?1 july 2005 2. trimatrix embedded memory blocks in stratix & stratix gx devices introduction stratix ? and stratix gx devices feature the trimatrix? memory structure, composed of three sizes of embedded ram blocks. trimatrix memory includes 512-bit m512 blocks , 4-kbit m4k blocks, and 512-kbit m-ram blocks, each of which is conf igurable to support a wide range of features. offering up to 10 mbits of ra m and up to 12 terabits per second of device memory bandwidth, the trimatrix memory structure makes the stratix and stratix gx families ideal for memory-intensive applications. trimatrix memory trimatrix memory structures can implement a wide variety of complex memory functions. for ex ample, use the small m512 blocks for first-in first-out (fifo) functions and clock domain buffering where memory bandwidth is critical. the m4k blocks are an ideal size for applications requiring medium-sized memory, such as asynchronous transfer mode (atm) cell processing. m-ram bloc ks enhance programmable logic device (pld) memory capabilities for large buffering applications, such as internet protocol (ip) packet buffering and system cache. trimatrix memory blocks support various memory configurations, including single-port, simple dual-p ort, true dual-port (also known as bidirectional dual-port), shift-re gister, rom, and fifo mode. the trimatrix memory architecture also includes advanc ed features and capabilities, such as byte enable support, parity-bit support, and mixed- port width support. this chapter descr ibes the various trimatrix memory modes and features. table 2?1 summarizes the features supported by the three sizes of trimatrix memory. f for more information on selectin g which memory block to use, see an 207: trimatrix memory selectio n using the quartus ii software. s52003-3.3 2?2 altera corporation stratix device handbook, volume 2 july 2005 trimatrix memory table 2?1. summary of trimatrix memory features feature m512 block m4k block m-ram block performance 319 mhz 290 mhz 287 mhz total ram bits (including parity bits) 576 4,608 589,824 configurations 512 1 256 2 128 4 64 8 64 9 32 16 32 18 4k 1 2k 2 1k 4 512 8 512 9 256 16 256 18 128 32 128 36 64k 8 64k 9 32k 16 32k 18 16k 32 16k 36 8k 64 8k 72 4k 128 4k 144 parity bits vvv byte enable vv single-port memory vvv simple dual-port memory vvv true dual-port memory vv embedded shift register vv rom vv fifo buffer vvv simple dual-port mixed width support vvv true dual-port mixed width support vv memory initialization file ( .mif ) vv mixed-clock mode vvv power-up condition outputs cleared outputs cleared outputs unknown register clears input and output registers (1) input and output registers (2) output registers same-port read-during-write new data available at positive clock edge new data available at positive clock edge new data available at positive clock edge mixed-port read-during-write outputs set to unknown or old data outputs set to unknown or old data unknown output notes to ta b l e 2 ? 1 : (1) the rden register on the m512 memory bl ock does not have a clear port. (2) on the m4k block, asserting the clear port of the rden and byte enable registers drives the output of these registers high. altera corporation 2?3 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices the extremely high memory bandwidth of the stratix and stratix gx device families is a result of increased memory capacity and speed. table 2?2 shows the memory capacity for trimatrix memory blocks in each stratix device. table 2?3 shows the memory capacity for trimatrix memory blocks in each stratix gx device. clear signals when applied to input registers, the asynchronous clear signal for the trimatrix embedded memory immediately clears the input registers. however, the output of the memory block does not show the effects until the next clock edge. when applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately. parity bit support the memory blocks support a parity bi t for each byte. parity bits are in addition to the amount of memory in each ram block. for example, the m512 block has 576 bits, 64 of which ar e optionally used for parity bit table 2?2. trimatrix memory dist ribution in stratix devices device m512 columns/blocks m4k columns/blocks m-ram blocks total ram bits ep1s10 4 / 94 2 / 60 1 920,448 ep1s20 6 / 194 2 / 82 2 1,669,248 ep1s25 6 / 224 3 / 138 2 1,944,576 ep1s30 7 / 295 3 / 171 4 3,317,184 ep1s40 8 / 384 3 / 183 4 3,423,744 ep1s60 10 / 574 4 / 292 6 5,215,104 ep1s80 11 / 767 4 / 364 9 7,427,520 table 2?3. trimatrix memory distri bution in stratix gx devices device m512 columns/blocks m4k columns/blocks m-ram blocks total ram bits ep1sgx10 4 / 94 2 / 60 1 920,448 ep1sgx25 6 / 224 3 / 138 2 1,944,576 ep1sgx40 8 / 384 3 / 183 4 3,423,744 2?4 altera corporation stratix device handbook, volume 2 july 2005 trimatrix memory storage. the parity bit, along with logic implemented in logic elements (les), can implement parity checking for error detection to ensure data integrity. parity-size data words can al so store user-specified control bits. byte enable support in the m4k and m-ram blocks, byte enables can mask the input data so that only specific bytes of data are written. the unwritten bytes retain the previous written value. the write enable signals ( wren ), in conjunction with the byte enable signals ( byteena ), controls the ram block?s write operations. the default value for the byteena signals is high (enabled), in which case writing is controlled only by the wren signals. asserting the clear port of the byte enable registers drives the byte enable signals to their default high level. m4k blocks m4k blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. table 2?4 summarizes the byte selection. table 2?4. byte enable for m4k blocks notes (1) , (2) byteena datain 18 datain 36 [0] = 1 [8..0] [8..0] [1] = 1 [17..9] [17..9] [2] = 1 ? [26..18] [3] = 1 ? [35..27] notes to ta b l e 2 ? 4 : (1) any combination of byte enables is possible. (2) byte enables can be used in the sa me manner with 8-bit words, i.e., in 16 and 32 modes. altera corporation 2?5 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices m-ram blocks m-ram blocks support byte enables for the 16, 18, 32, 36, 64, and 72 modes. in the 128 or 144 simple dual-port mo de, the two sets of byteena signals ( byteena_a and byteena_b ) combine to form the necessary 16 byte enables. tables 2?5 and 2?6 summarize the byte selection. table 2?5. byte enable for m-ram blocks notes (1) , (2) byteena datain 18 datain 36 datain 72 [0] = 1 [8..0] [8..0] [8..0] [1] = 1 [17..9] [17..9] [17..9] [2] = 1 ? [26..18] [26..18] [3] = 1 ? [35..27] [35..27] [4] = 1 ? ? [44..36] [5] = 1 ? ? [53..45] [6] = 1 ? ? [62..54] [7] = 1 ? ? [71..63] notes to ta b l e 2 ? 5 : (1) any combination of byte enables is possible. (2) byte enables can be used in the same manner with 8-bit words, that is, in 16, 32, and 64 modes. table 2?6. m-ram combined byte selection for 144 mode (part 1 of 2) , notes (1) , (2) byteena_a datain 144 [0] = 1 [8..0] [1] = 1 [17..9] [2] = 1 [26..18] [3] = 1 [35..27] [4] = 1 [44..36] [5] = 1 [53..45] [6] = 1 [62..54] [7] = 1 [71..63] [8] = 1 [80..72] [9] = 1 [89..81] [10] = 1 [98..90] [11] = 1 [107..99] 2?6 altera corporation stratix device handbook, volume 2 july 2005 trimatrix memory byte enable functional waveform figure 2?1 shows how both the wren and the byteena signals control the write operations of the ram. figure 2?1. byte enable fun ctional waveform note (1) note to figure 2?1 : (1) for more information on simulation output when a read-durin g-write occurs at the same address location, see ?read-during-write operation at the same address? on page 2?25 . [12] = 1 [116..108] [13] = 1 [125..117] [14] = 1 [134..126] [15] = 1 [143..135] notes to ta b l e 2 ? 6 : (1) any combination of byte enables is possible. (2) byte enables can be used in the sa me manner with 8-bit words, i.e., in 16, 32, 64, and 128 modes. table 2?6. m-ram combined byte selection for 144 mode (part 2 of 2) , notes (1) , (2) byteena_a datain 144 inclock wren address data_in asynch_data_out an xxxx a0 a1 a2 a0 a1 a2 doutn abxx xxcd abcd abff ffcd abcd byteena xx 10 01 11 xxxx xx abcd abcd ffff ffff ffff abff ffcd contents at a0 contents at a1 contents at a2 altera corporation 2?7 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices using trimatrix memory the trimatrix memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. all trimatrix memory bl ocks are pipelined, meaning that all inputs are registered, but outputs are either registered or combinatorial. trimatrix memory ca n emulate a flow-through memory by using combinatorial outputs. f for more information, see an 210: converting memo ry from asynchronous to synchronous for stra tix & stratix gx designs . depending on the trimatrix memory block type, the memory can have various modes, including: single-port simple dual-port true dual-port (bidirectional dual-port) shift-register rom fifo implementing single-port mode single-port mode supports non- simultaneous reads and writes. figure 2?2 shows the single-port memory configuration for trimatrix memory. all memory block types support the single-port mode. figure 2?2. single-port memory note (1) note to figure 2?2 : (1) two single-port memory blocks can be implemented in a single m4k block. m4k memory blocks can also be divided in half and used for two independent single-port ram blocks . the altera quartus ii software automatically uses this single-port memory pa cking when running low on memory resources. to force two single-port memories into one m4k block, first ensure that each of the two independent ram blocks is equal to or less than half the size of the m4k block. second, as sign both single- port rams to the same m4k block. data[ ] address[ ] wren inclock inclocken inaclr q[ ] outclock outclocken outaclr 2?8 altera corporation stratix device handbook, volume 2 july 2005 using trimatrix memory in the single-port ram configuratio n, the outputs can only be in read-during-write mode, which means that during the write operation, data written to the ram flows thro ugh to the ram outputs. when the output registers are bypassed, the new da ta is available on the rising edge of the same clock cycle it was writ ten on. for more information about read-during-write mode, see ?read-during-write operation at the same address? on page 2?25 . figure 2?3 shows timing waveforms for read and write operations in single-port mode. figure 2?3. single-port timing waveforms implementing simple dual-port mode simple dual-port memory supports a simultaneous read and write. figure 2?4 shows the simple dual-port memory configuration for trimatrix memory. all memory block types support this configuration. figure 2?4. simple dual-port memory note (1) note to figure 2?4 : (1) simple dual-port ram supports read/write clock mode in addition to the input/output clock mode shown. in clock wren address data_in synch_data_out an-1 din-1 din din4 din5 a6 din6 an a0 a1 a2 a3 a4 a5 asynch_data_out din-2 din-1 din dout0 dout1 dout2 dout3 din4 din-1 din dout0 dout1 dout2 dout3 din4 din5 data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr dual-port memory altera corporation 2?9 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices trimatrix memory supports mixed-width configurations, allowing different read and write port widths. when using mixed-width mode, the lsb is written to or read from first. for ex ample, take a ram that is set up in mixed-width mode with write data width 8 and read data width 2. if a binary 00000001 is written to write dr ess 0, the following is read out of the 2 output side: tables 2?7 to 2?9 show the mixed width conf igurations for the m512, m4k, and m-ram blocks, respectively. read address 2 data 00 01(lsb of 8 data) 01 00 10 00 11 00(msb of 8 data) table 2?7. m512 block mixed-width confi gurations (simple dual-port mode) read port write port 512 1 256 2 128 4 64 8 32 16 64 9 32 18 512 1 vvvvv 256 2 vvvvv 128 4 vvv v 64 8 vv v 32 16 vvv v 64 9 v 32 18 v table 2?8. m4k block mixed-width configurat ions (simple dual-port mode) (part 1 of 2) read port write port 4k 12k 21k 4 512 8 256 16 128 32 512 9 256 18 128 36 4k 1 vvv v v v 2k 2 vvv v v v 1k 4 vvv v v v 512 8 vvv v v v 256 16 vvv v v v 2?10 altera corporation stratix device handbook, volume 2 july 2005 using trimatrix memory m512 blocks support serializer and deserializer (serdes) applications. by using the mixed-width support in combination with double data rate (ddr) i/o standards, the block can function as a serdes to support low- speed serial i/o standards usin g global or regional clocks. f for more information on strati x device i/o structure see the stratix device family data sheet section of the stratix device handbook , volume 1 . for more information on stratix gx device i/o structure see the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 . in simple dual-port mode, the m512 and m4k blocks have one write enable and one read enable signal. th e m512 does not support a clear port on the rden register. on the m4k block, asserting the clear port of the rden register drives rden high, which allows the read operation to occur. when the read enable is deactivated, the current data is retained at the output ports. if the read enable is activated during a write operation with the same address location selected, the simple dual-port ram output is either unknown or can be set to output the old data stored at the memory address. for more information, see ?read-during-write operation at the same address? on page 2?25 . 128 32 vvv v v v 512 9 vv v 256 18 vv v 128 36 vv v table 2?9. m-ram block mixed-width conf igurations (simple dual-port mode) read port write port 64k 932k 18 16k 36 8k 72 4k 144 64k 9 vvvv 32k 18 vvvv 16k 36 vvvv 8k 72 vvvv 4k 144 v table 2?8. m4k block mixed-width configurat ions (simple dual-port mode) (part 2 of 2) read port write port 4k 12k 21k 4 512 8 256 16 128 32 512 9 256 18 128 36 altera corporation 2?11 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices m-ram blocks have one write enable si gnal in simple dual-port mode. to perform a write operation, the write enable is held high. the m-ram block is always enabled for read oper ation. if the read address and the write address select the same address location during a write operation, the m-ram block output is unknown. figure 2?5 shows timing waveforms for read and write operations in simple dual-port mode. figure 2?5. simple dual-port timing waveforms note (1) note to figure 2?5 : (1) the rden signal is not available in the m-ram block. a m-ra m block in simple dual-port mode is always reading out the data stored at the current read address location. implementing true dual-port mode m4k and m-ram blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. figure 2?6 shows the true dual-port memory configuration for trimatrix memory. wrclock wren wraddress data_in synch_data_out an-1 an a0 a1 a2 a3 a4 a5 din-1 din din4 din5 rdclock a6 din6 asynch_data_out rden rdaddress bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 dout0 2?12 altera corporation stratix device handbook, volume 2 july 2005 using trimatrix memory figure 2?6. true dual-port memory note (1) note to figure 2?6 : (1) true dual-port memory supports input/output clock mode in addition to the independent clock mode shown. the widest bit configuration of the m4k and m-ram blocks in true dual- port mode is 256 16-bit ( 18-bit with parity) and 8k 64-bit ( 72-bit with parity), respectively. the 128 32-bit ( 36-bit with parity) configuration of the m4k block and the 4k 128-bit ( 144-bit with parity) configuration of the m-ram block are unavailable because the number of output drivers is equiva lent to the maximum bit width of the respective memory block. because true dual-p ort ram has outputs on two ports, the maximum width of the true dual-port ram equals half of the total number of output drivers. tables 2?10 and 2?11 list the possible m4k ram block and m-ram block co nfigurations, respectively. data a [ ] address a [ ] wren a clock a clocken a q a [ ] aclr a data b [ ] address b [ ] wren b clock b clocken b q b [ ] aclr b ab table 2?10. m4k block mixed-port widt h configurations (true dual-port) port a port b 4k 12k 21k 4 512 8 256 16 512 9 256 18 4k 1 vvvvv 2k 2 vvvvv 1k 4 vvvvv 512 8 vvvvv 256 16 vvvvv 512 9 vv 256 18 vv altera corporation 2?13 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices in true dual-port configuration, the ram outputs can only be configured for read-during-write mode. this means that during write operation, data being written to the a or b port of the ram flows through to the a or b outputs, respectively. when th e output registers are bypassed, the new data is available on the rising edge of the same clock cycle it was written on. for waveforms and inform ation on mixed-port read-during- write mode, see ?read-during-write operation at the same address? on page 2?25 . potential write contentions must be resolved external to the ram because writing to the same address location at both ports results in unknown data storage at that location. data is written on the rising edge of the write clock for the m-ram block. for a va lid write operation to the same address of the m-ram block, the rising edge of the write clock for port a must occur following the maximum writ e cycle time interval after the rising edge of the write clock for port b. since data is written into the m512 and m4k blocks at the falling ed ge of the write clock, the rising edge of the write clock for port a should occur follow ing half of the maximum write cycle time interval afte r the falling edge of the write clock for port b. if this timing is not met, the data stored in that particular address is invalid. f see the stratix device family data sheet section of the stratix device handbook, volume 1 or the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 for the maximum synchronous write cycle time. figure 2?7 shows true dual-port timing waveforms for write operation at port a and read operation at port b. table 2?11. m-ram block mixed-port widt h configurations (true dual-port) port a port b 64k 9 32k 18 16k 36 8k 72 64k 9 vvvv 32k 18 vvvv 16k 36 vvvv 8k 72 vvvv 2?14 altera corporation stratix device handbook, volume 2 july 2005 using trimatrix memory figure 2?7. true dual-port timing waveforms implementing shift-register mode embedded memory block configurations can implement shift registers for digital signal processing (dsp) applications, such as finite impulse response (fir) filters, pseudo-ran dom number generators, multi-channel filtering, and auto-correlation and cr oss-correlation functions. these and other dsp applications require local data storage, traditionally implemented with standard flip-flops that can quickly consume many logic cells for large shift registers. a more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation. the size of a ( w m n) shift register is determined by the input data width ( w ), the length of the taps ( m ), and the number of taps ( n ). the size of a ( w m n) shift register must be less than or equal to the maximum number of memory bits in the resp ective block: 576 bits for the m512 block and 4,608 bits for the m4k bl ock. in addition, the size of w n must be less than or equal to the maximu m width of the respective block: 18 bits for the m512 block and 36 bits fo r the m4k block. if a larger shift register is required, the memory blocks can be cascaded together. 1 m-ram blocks do not support the shift-register mode. a_clk a_wren a_address a_data_in b_synch_data_out an-1 an a0 a1 a2 a3 a4 a5 din-1 din din4 din5 b_clk a6 din6 b_asynch_data_out b_wren b_address bn b0 b1 b2 b3 doutn-2 doutn-1 doutn doutn-1 doutn dout0 a_synch_data_out a_asynch_data_out dout0 dout1 dout1 dout2 din-2 din-1 din dout0 dout1 dout2 dout3 din4 din-1 din dout0 dout1 dout2 dout3 din4 din5 altera corporation 2?15 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices data is written into each address locati on at the falling edge of the clock and read from the address at the rising edge of the clock. the shift-register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. figure 2?8 shows the trimatrix memory block in the shift-register mode. figure 2?8. shift-register memory configuration implementing rom mode the m512 and the m4k blocks support rom mode. use a memory initialization file ( .mif ) to initialize the rom contents of m512 and m4k blocks. the m-ram block does not support rom mode. all stratix memory configurations must have synchronous inputs; therefore, the address lines of the rom are registered. the outputs can be registered or combinator ial. the rom read operation is identical to the read operation in the single-port ram configuration. m -bit shift register w w m -bit shift register m -bit shift register m -bit shift register w w w w w w w m n shift register n numbe r of taps 2?16 altera corporation stratix device handbook, volume 2 july 2005 clock modes implementing fifo buffers while the small m512 memory blocks are ideal for designs with many shallow fifo buffers, all three memory sizes support fifo mode. all memory configurations have sync hronous inputs; however, the fifo buffer outputs are always combinatorial. simultaneous read and write from an empty fifo is not supported. clock modes depending on the trimatrix memory mode, independent, input/output, read/write, and/or single-por t clock modes are available. table 2?12 shows the clock modes supported by the trimatrix memory modes. independent clock mode the trimatrix memory blocks can implement independent clock mode for true dual-port memory. in this mo de, a separate clock is available for each port (a and b). clock a controls all registers on the port a side, while clock b controls all registers on the port b side. each port also supports independent clock enables and asynchronous clear signals for port a and b registers. figure 2?9 shows a trimatrix memory block in independent clock mode. table 2?12. trimatrix memory clock modes clocking mode true-dual port mode simple dual- port mode single-port mode independent v input/output vv read/write v single-port v altera corporation 2?17 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices figure 2?9. independent clock mode note (1) , (2) note to figure 2?9 : (1) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. (2) all registers shown have asynchronous clear port s, except when using the m-ram. m-ram blocks have asynchronous clear ports on their output registers only. 8 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out clken a clock a d ena q wren a 8 lab row clocks q a [ ] 8 data b [ ] address b [ ] clken b clock b wren b q b [ ] ena ab ena d q d ena q byteena a [ ] byte enable a byte enable b byteena b [ ] ena d q ena d q ena d q d q write pulse generator write pulse generator 2?18 altera corporation stratix device handbook, volume 2 july 2005 clock modes input/output clock mode the trimatrix memory blocks can implement input/output clock mode for true and simple dual-port memory. on each of the two ports, a and b, one clock controls all registers for inputs into the memory block: data input, wren , and address. the other clock co ntrols the block?s data output registers. each memory block port also supports independent clock enables and asynchronous clear signal s for input and output registers. figures 2?10 and 2?11 show the memory block in input/output clock mode for true and simple dual-port modes, respectively. altera corporation 2?19 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices figure 2?10. input/output clock mode in true dual-port mode note (1) note to figure 2?10 : (1) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q data a [ ] address a [ ] memory block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1 data in address a write/read enable data out data in address b write/read enable data out clken a clock a d ena q wren a 8 lab row clocks q a [ ] 8 data b [ ] address b [ ] clken b clock b wren b q b [ ] ena ab ena d q ena d q ena d q d q d ena q byteena a [ ] byte enable a byte enable b byteena b [ ] ena d q write pulse generator write pulse generator 2?20 altera corporation stratix device handbook, volume 2 july 2005 clock modes all registers shown have asynchronous clear ports, except when using the m-ram. m-ram blocks have as ynchronous clear ports on their output registers only. figure 2?11. input/output clock mode in simple dual-port mode notes (1) , (2) , (3) , (4) notes to figure 2?11 : (1) the rden signal is not available in the m-ram block. a m-ra m block in simple dual-port mode is always reading out the data stored at the current read address location. (2) for more information on the multitrack? interconnect, see the stratix device family data sheet section of the stratix device handbook, volume 1 or the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 . (3) all registers shown have asynchronous clear port s, except when using the m-ram. m-ram blocks have asynchronous clear ports on their output registers only. (4) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out outclken inclken wrclock rdclock wren rden 8 lab row clocks to multitrac k interconnect d ena q byteena[ ] byte enable write pulse generator altera corporation 2?21 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices read/write clock mode the trimatrix memory blocks can im plement read/write clock mode for simple dual-port memory. this mode can use up to two clocks. the write clock controls the block?s data inputs, wraddress , and wren . the read clock controls the data output, rdaddress , and rden . the memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. figure 2?12 shows a memory block in read/write clock mode. 2?22 altera corporation stratix device handbook, volume 2 july 2005 clock modes figure 2?12. read/write clock m ode in simple dual-port mode notes (1) , (2) , (3) notes to figure 2?12 : (1) for more information on the multitrack interconnect, see the stratix device fa mily data sheet section of the stratix device handbook, volume 1 or the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 . (2) all registers shown have asynchronous clear port s, except when using the m-ram. m-ram blocks have asynchronous clear ports on their output registers only. (3) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. 8 d ena q d ena q d ena q d ena q d ena q data[ ] d ena q wraddress[ ] address[ ] memory block 256 16 512 8 1,024 4 2,048 2 4,096 1 data in read address write address write enable read enable data out rdclocken wrclocken wrclock rdclock wren rden 8 lab row clocks to multitrac k interconnect d ena q byteena[ ] byte enable write pulse generator read pulse generator altera corporation 2?23 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices single-port mode the trimatrix memory blocks can im plement single-port clock mode for single-port memory mode. single-port mode is used when simultaneous reads and writes are not required. see figure 2?13 . a single block in a memory block can support up to two single-port mode ram blocks in m4k blocks. figure 2?13. single-port mode notes (1) , (2) , (3) notes to figure 2?13 : (1) for more information on the multitrack interconnect, see the stratix device family data sheet section of the stratix device handbook, volume 1 or the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 . (2) all registers shown have asynchronous clear port s, except when using the m-ram. m-ram blocks have asynchronous clear ports on their output registers only. (3) violating the setup or hold time on the address register s could corrupt the memory contents. this applies to both read and write operations. designing with trimatrix memory when instantiating trimatrix memory you must understand the various features that set it apart from othe r memory architectures. the following sections describe some of the import ant attributes and functionality of trimatrix memory. 8 d ena q d ena q d ena q d ena q data[ ] address[ ] ram/rom 256 16 512 8 1,024 4 2,048 2 4,096 1 data in address write enable data out outclken inclken inclock outclock write pulse generator wren 8 lab row clocks to multitrac k interconnect 2?24 altera corporation stratix device handbook, volume 2 july 2005 designing with trimatrix memory f for information on the difference between apex-style memory and trimatrix memory, see the transitioning apex desi gns to stratix devices chapter. selecting trimatri x memory blocks the quartus ii software automatically partitions user-defined memory into embedded memory blocks using the most efficient size combinations. the memory can also be manually assigned to a specific block size or a mixture of block sizes. table 2?1 on page 2?2 is a guide for selecting a trimatrix memory block size based on supported features. 1 violating the setup or hold time on the address registers could corrupt the memory contents. this applies to both read and write operations. f for more information on selectin g which memory block to use, see an 207: trimatrix memory selectio n using the quartus ii software . 1 violating the setup or hold time on the address registers could corrupt the memory contents. this applies to both read and write operations. pipeline & flow-through modes trimatrix memory architecture im plements synchronous (pipelined) ram by registering both the input an d output signals to the ram block. all trimatrix memory inputs are regi stered providing synchronous write cycles. in synchronous operation, ram generates its own self-timed strobe write enable ( wren ) signal derived from th e global or regional clock. in contrast, a circuit using asynchronous ram must generate the ram wren signal while ensuring its data and address signals meet setup and hold time specifications relative to the wren signal. the output registers can be bypassed. in an asynchronous memory neit her the input nor the output is registered. while stratix and stra tix gx devices do not support asynchronous memory, they do support a flow-through read where the output data is available during the clock cycle when the read address is driven into it. flow-through reading is possible in the simple and true dual-port modes of the m512 and m4k bl ocks by clocking the read enable and read address registers on the ne gative clock edge and bypassing the output registers. f for more information, see an 210: converting memo ry from asynchronous to synchronous for stratix & stratix gx devices . altera corporation 2?25 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices power-up conditions & memory initialization upon power-up, trimatrix memory is in an idle state. the m512 and m4k block outputs always power-up to zero, regardless of whether the output registers are used or bypassed. even if a memory initialization file is used to pre-load the contents of the ra m block, the output s still power-up cleared. for example, if address 0 is pre-initialized to ff , the m512 and m4k blocks power-up with the output at 00 . m-ram blocks do not support memory in itialization files; therefore, they cannot be pre-loaded with data upon power-up. m-ram blocks combinatorial outputs and memory co ntrols always power-up to an unknown state. if m-ram block outputs are registered, the registers power-up cleared. the undefined outp ut appears one clock cycle later. the output remains undefined until a read operation is performed on an address that has been written to. read-during- write operation at the same address the following two sections describe the functionality of the various ram configurations when reading from an address during a write operation at that same address. there are two ty pes of read-during-write operations: same-port and mixed-port. figure 2?14 illustrates the difference in data flow between same-port and mi xed-port read-during-write. figure 2?14. read-during-write data flow same-port read-during-write mode for read-during-write operation of a single-port ram or the same port of a true dual-port ram, the new data is available on the rising edge of the same clock cycle it was written on. th is behavior is valid on all memory- block sizes. see figure 2?15 for a sample functional waveform. port a data in port b data in port b data out port a data out same-port data flow mixed-port data flow 2?26 altera corporation stratix device handbook, volume 2 july 2005 read-during-write operation at the same address when using byte enables in true dual-port ram mode, the outputs for the masked bytes on the sa me port are unknown. (see figure 2?1 on page 2?6 .) the non-masked bytes are read out as shown in figure 2?15 . figure 2?15. same-port read-during-write functionality note (1) note to figure 2?15 : (1) outputs are not registered. mixed-port read-during-write mode this mode is used when a ram in simple or true dual-port mode has one port reading and the other port writin g to the same addr ess location with the same clock. the read_during_write_mode_mixed_ports parameter for m512 and m4k memory blocks determines wh ether to output the old data at the address or a ?don?t care? value. setting this parameter to old_data outputs the old data at that addr ess. setting this parameter to dont_care outputs a ?don?t care? or unknown value. see figures 2?16 and 2?17 for sample functional waveforms showin g this operation. these figures assume that the outputs are not registered. the dont_care setting allows memory implementation in any trimatrix memory block. the old_data setting restricts memory implementation to only m512 or m4k memory blocks. selecting dont_care gives the compiler more flexibility when placing memory functions into trimatrix memory. inclock data_in wren data_out a b a old altera corporation 2?27 july 2005 stratix device handbook, volume 2 trimatrix embedded memory blocks in stratix & stratix gx devices figure 2?16. mixed-port read-during-write: old_data for mixed-port read-during-write oper ation of the same address location of a m-ram block, the ram outputs are unknown, as shown in figure 2?17 . figure 2?17. mixed-port read- during-write: dont_care mixed-port read-during-write is not supported when two different clocks are used in a dual-port ram. the ou tput value will be unknown during a mixed-port read-during-write operation. conclusion trimatrix memory, an enhanced ram architecture with extremely high memory bandwidth in stratix and stratix gx devices, gives advanced control of memory applications with features such as byte enables, parity bit storage, and shift-register mode, as well as mixed- port width support and true dual-port mode. inclock port a data_in port a wren port b data_out ab a old port b wren b address q address a and address b inclock port a data_in port a wren port b data_out ab b unknown port b wren address q address a and address b 2?28 altera corporation stratix device handbook, volume 2 july 2005 conclusion altera corporation 3?1 june 2006 3. external memory interfaces in stratix & stratix gx devices introduction stratix ? and stratix gx devices support a broad range of external memory interfaces such as double data rate (ddr) sdram, rldram ii, quad data rate (qdr) sram, qdrii sram, zero bus turnaround (zbt) sram, and single data rate (sdr) sdram. the dedicated phase-shift circuitry allows the stratix and strati x gx devices to interface at twice the system clock speed with an extern al memory (up to 200 mhz/400 mbps). typical i/o architectures transmit a single data word on each positive clock edge and are limited to the as sociated clock speed using this protocol. to achieve a 400-megabits pe r second (mbps) transfer rate, a sdr system requires a 400-mhz cloc k. many new applications have introduced a ddr i/o arch itecture as an alternat ive to sdr architectures. while sdr architectures capture data on one edge of a clock, the ddr architectures captures data on both the rising and falling edges of the clock, doubling the throughput for a given clock frequency and accelerating performance. for exam ple, a 200-mhz clock can capture a 400-mbps data stream, enhancing system performance and simplifying board design. most current memory architectures use a ddr i/o interface. these ddr memory standards cover a broad rang e of applications for embedded processor systems, image processing, storage, communications, and networking. this chapter describes th e hardware features in stratix and stratix gx devices that facilitate th e high-speed memory interfacing for each memory standard. it then briefly explains how each memory standard uses the features of th e stratix and stratix gx devices. f you can use this document with an 329: zbt sram controller reference design for stratix & stratix gx devices, an 342: interfacing ddr sdram with stratix & stratix gx devices , and an 349: qdr sram controller reference design for stra tix & stratix gx devices . external memory standards the following sections provide an overview on using the stratix and stratix gx device external memory interfacing features. ddr sdram ddr sdram is a memory architecture that transmits and receives data at twice the clock speed of traditio nal sdr architectures. these devices transfer data on both the rising an d falling edge of the clock signal. s52008-3.3 3?2 altera corporation stratix device handbook, volume 2 june 2006 external memory standards interface pins ddr devices use interface pins including data, data strobe, clock, command, and address pins. data is se nt and captured at twice the clock rate by transferring data on both the positive and negative edge of a clock. the commands and addresses only us e one active edge of a clock. connect the memory device?s dq an d dqs pins to the dq and dqs pins, respectively, as listed in the stratix and stratix gx devices pin table. ddr sdram also uses active-h igh data mask pins for writes. you can connect dm pins to any of the i/o pins in th e same bank as the dq pins of the fpga. there is one dm pin per dqs/dq group. ddr sdram 16 devices use two dqs pins, and each dqs pin is associated with eight dq pins. howe ver, this is not the same as the 16 mode in stratix and stratix gx devices. to support a 16 ddr sdram, you need to configure the stratix and stratix gx fpgas to use two sets of dq pins in 8 mode. similarly if your 32 memory device uses four dqs pins where each dqs pin is associated with eight dq pins, you need to configure the stratix and strati x gx fpga to use four sets of pins in 8 mode. you can also use any i/o pins in bank s 1, 2, 5, or 6 to interface with ddr sdram devices. these banks do not have dedicated circuitry, though. you can also use any of the user i /o pins for commands and addresses to the ddr sdram. f for more information, see an 342: interfacing ddr sdram with stratix & stratix gx devices . if the ddr sdram device supports ecc, the design uses a dqs/dq group for ecc pins. you can use any of the user i/o pins for commands and addresses. because of the symmetrical setup an d hold time for the command and address pins at the memory, you might need to generate these signals from the system clock?s negative edge. the clocks to the sdram device are called ck and ck#. use any of the user i/o pins via the ddr registers to generate the ck and ck# signals to meet the ddr sdram t dqss requirement. the memory device?s t dqss requires that the dqs signal?s posi tive edge write operations must be within 25% of the positive edge of the ddr sdram clock input. using user i/o pins for ck and ck# ensure s that any pvt variations seen by the dqs signal are tracked by these pins, too. altera corporation 3?3 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices read & write operations when reading from the ddr sdram, the dqs signal coming into the stratix and stratix gx device is ed ge-aligned with the dq pins. the dedicated circuitry center-aligns the dqs signal with respect to the dq signals and the shifted dqs bus drives the clock input of the ddr input registers. the ddr input registers brin g the data from the dq signals to the device. the system clock clocks the dqs output enable and output paths. the -90 shifted clock clocks the dq output enable and output paths. figure 3?1 shows an example of the dq and dqs relationship during a burst-of-two read. it shows where the dqs signal is center-aligned in the ioe. figure 3?1. example of where a dqs si gnal is center-aligned in the ioe when writing to the ddr sdram, the dqs signal must be center- aligned with the dq pins. two pll ou tputs are needed to generate the dqs signal and to clock the dq pi ns. the dqs are clocked by the 0 phase-shift pll output, while the dq pins are clocked by the -90 phase- shifted pll output. figure 3?2 shows the dqs and dq relationship during a ddr sdram burst-of-two write. figure 3?2. dq & dqs relationship during a burst-of-two write dqs at dq ioe registers dqs at fpga pin dq at dq ioe registers dq at fpga pin pin to register delay pin to register delay 90 degree shift preamble postamble dqs at fpga pin dq at fpga pin 3?4 altera corporation stratix device handbook, volume 2 june 2006 external memory standards figure 3?3 shows ddr sdram interfacing from the i/o through the dedicated circuitry to the logic array. when the dqs pin acts as an input strobe, the dedicated circuitry shifts the incoming dqs pin by either 72 or 90 and clocks the ddr input regi sters. because of the ddr input registers architecture in stratix and stratix gx devices, the shifted dqs signal must be inverted. the ddr registers outputs are sent to two le registers to be synchronized with the system clock. f refer to the dc & switching characteristics chapter in volume 1 of the stratix device handbook for frequency limits regarding the 72 and 90 phase shift for dqs. figure 3?3. ddr sdram interfacing f for more information on ddr sdram specifications, see jedec standard publications jesd79c from www.jedec.org , or see an 342: interfacing ddr sdram with stratix & stratix gx devices . rldram ii rldram ii provides fast random acce ss as well as high bandwidth and high density, making this memory technology ideal for high-speed network and communication data storage applications. the fast random access speeds in rldram ii devices make them a viable alternative to sram devices at a lower cost. additionally, rldram ii devices have minimal latency to support designs th at require fast response times. user logic/ gnd 2 oe pll ? 90? dqs adjacent lab les dqs bus resynchronizing global clock compensated delay shift ddr oe registers ddr output registers 2 oe ddr oe registers ddr output registers dq i/o elements & periphery ddr input registers le register le register t 2 altera corporation 3?5 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices interface pins rldram ii devices use interface pins such as data, clock, command, and address pins. there are two types of rldram ii memory: common i/o (cio) and separate i/o (sio). the da ta pins in rldram ii cio device are bidirectional while the data pins in a rldram ii sio device are uni-directional. instead of bidirectional data strobes, rldram ii uses differential free-running read and wr ite clocks to accompany the data. as in ddr sdram, data is sent and captured at twice the clock rate by transferring data on both the positive and negative edge of a clock. the commands and addresses still only use one active edge of a clock. if the data pins are bidirectional, connect them to the stratix and stratix gx device dq pins. if the data pins are uni-dire ctional, connect the rldram ii device q ports to the stratix and stratix gx device dq pins and connect the d ports to any user i/o pins in i/o banks 3, 4, 7, and 8. rldram ii also uses active-high data mask pins for writes. you can connect dm pins to any of the i/o pins in the same bank as the dq pins of the fpga. when interfacing with sio devices, connect the dm pins to any of the i/o pins in the same bank as the d pins. there is one dm pin per dqs/dq group. connect the read clock pins (qk) to stratix and stratix gx device dqs pins. you must configure the dqs sign als as bidirectiona l pins. however, since qk pins are output -only pins from the memory, rldram memory interfacing in stratix and stratix gx devices requires that you ground the dqs and dqsn pin output enables. the stratix and stratix gx devices use the shifted qk signal from the dqs logic block to capture data. you can leave the qk# signal of the rldram ii device unconnected. rldram ii devices have both inpu t clocks (ck and ck#) and write clocks (dk and dk#). use the external clock buffer to generate ck, ck#, dk, and dk# to meet the ck, ck#, dk, and dk# skew requirements from the rldram ii device. if you are interfacing with multiple rldram ii devices, perform ibis si mulations to analyze the loading effects on the clock pair. you can use any of the user i/o pins for commands and addresses. rldram ii also offers qvld pins to in dicate the read data availability. connect the qvld pins to the stratix and stratix gx device dqvld pins, listed in the pin table. read & write operations when reading from the rldram ii device, data is sent edge-aligned with the read clock qk or qk# sign al. when writing to the rldram ii device, data must be center-aligned with the write clock (dk or dk# signal). the stratix and stratix gx device rldram ii interface uses the 3?6 altera corporation stratix device handbook, volume 2 june 2006 external memory standards same scheme as in ddr sdram interfaces whereby the dedicated circuitry is used during reads to cent er-align the data and the read clock inside the fpga and the pll center-aligns the data and write clock outputs. the data and clock relati onship for reads and writes in rldram ii is similar to those in ddr sdram as already depicted in figure 3?1 on page 3?3 and figure 3?3 on page 3?4 . qdr & qdrii sram qdr sram provides independent read and write ports that eliminate the need for bus turnaround. the memo ry uses two sets of clocks: k and kn for write access, and optional c and cn for read accesses, where kn and cn are the inverse of the k and c clocks, respectively. you can use differential hstl i/o pins to driv e the qdr sram clock into the stratix and stratix gx devices. the separate write data and read data ports permit a transfer rate up to four words on every cycle through the ddr circuitry. stratix and stratix gx devi ces support both burst-of-two and burst-of-four qdr sram architectures, with clock cycles up to 167 mhz using the 1.5-v hstl class i or class ii i/o standard. figure 3?4 shows the block diagram for qdr sram burst-of-two architecture. figure 3?4. qdr sram block diagram for burst-of-two architecture qdrii sram is a second generation of qdr sram devices. it can transfer four words per clock cycle, fulfilling the requirements facing next-generation communications system designers. qdrii sram devices provide concurrent reads and writes, zero latency, and increased data throughput. stratix and strati x gx devices support qdrii sram at speeds up to 200 mhz since the timi ng requirements for qdrii sram are not as strict as qdr sram. 256k 18 memory array 256k 18 memory array read port rpsn q write port wpsn d a 18 18 data control logic k, kn 18 36 bwsn v ref c, cn 2 2 data 36 discrete qdr sram device altera corporation 3?7 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices interface pins qdr and qdrii sram uses two separate, uni-directional data ports for read and write operations, enabling quad data-rate data transfer. both qdr and qdrii sram use shared addr ess lines for reads and writes. stratix and stratix gx devices utilize dedicated ddr i/o circuitry for the input and output data bus and the k and kn output clock signals. both qdr and qdrii sram burst-of-two devices sample the read address on the rising edge of the k clock and sample the write address on the rising edge of the kn clock while qdr and qdrii sram burst-of- four devices sample both read and write addresses on the k clock's rising edge. you can use any of the stratix and stratix gx device user i/o pins in i/o banks 3, 4, 7, and 8 for th e d write data ports, commands, and addresses. qdr sram uses the following clock si gnals: input clocks k and kn and output clocks c and cn. in addition to the aforementioned two pairs of clocks, qdrii sram also us es echo clocks cq an d cqn. clocks cn, kn, and cqn are logical complements of clocks c, k, and cq respectively. clocks c, cn, k, and kn are inputs to the qdrii sram while clocks cq and cqn are outputs from the qdrii sram. stratix and stratix gx devices use single-clock mode for single-device qdr and qdrii sram interfacing where the k and kn ar e used for both read and write operations, and the c and cn clocks are unused. use both c or cn and k or kn clocks when interfacing wi th a bank of multiple qdrii sram devices with a single controller. you can generate c, cn, k, and kn cl ocks using any of the i/o registers in i/o banks 3, 4, 7, or 8 via th e ddr registers. due to strict skew requirements between k and kn signals, use adjacent pins to generate the clock pair. surround the pair with buffer pins tied to v cc and ground for better noise immunity from other signals. in general, all output signals to th e qdr and qdrii sram should use the top and bottom banks (i/o banks 3, 4, 7, or 8). you can place the input signals from the qdr and qd rii sram in any i/o banks. read & write operations figure 3?5 shows the data and clock relationships in qdrii sram devices at the memory pins during reads. qdr and qdrii sram devices send data within a t co time after each rising edge of the input clock c or cn in multi-clock mode, or the input clock k or kn in single clock mode. data is valid until t doh time, after each rising edge of the c or cn in multi- 3?8 altera corporation stratix device handbook, volume 2 june 2006 external memory standards clock mode, or k or kn in single clock mode. the edge-aligned cq and cqn clocks accompany the read data for data capture in stratix and stratix gx devices. figure 3?5. data & clock relations hip during a qdrii sram read note (1) notes to figure 3?5 : (1) the timing parameter nomenclature is based on the cypress qdrii sram data sheet for cy7c1313v18. (2) co is the data clock-to-out time and t doh is the data output hold time between burst. (3) t clz and t chz are bus turn-on and turn -off times respectively. (4) t cqd is the skew between cqn and data edges. (5) t cqqo and t cqoh are skew between the c or cn (or k or kn in single-clock mode) and the cq or cqn clocks. when writing to qdrii sram devices, data is generated by the write clock, while the k clock is 90 shifte d from the write clock, creating a center-aligned arrangement. f go to www.qdrsram.com for the qdr sram and qdrii sram specifications. for more information on qdr and qdrii sram interfaces in stratix and stratix gx devices, see an 349: qdr sram controller reference design fo r stratix & stratix gx devices . zbt sram zbt sram eliminate dead bus cycles when turning a bidirectional bus around between reads and writes or between writes and reads. zbt allows for 100% bus utilization becaus e zbt sram can be read or written on every clock cycle. bus contention can occur when shif ting from a write cycle to a read cycle or vice versa with no idle cycles in between. zbt sram allows small amounts of bus conten tion. to avoid bus contention, the output clock-to-low-impedance time (t zx ) must be greater qa qa + 1 qa + 2 qa + 3 c/k cn/kn cq cqn q t co (2) t co (2) t clz (3) t ccqo (5) t cqoh (5) t cqd (4) t cqd (4) t doh (2) t chz (3) altera corporation 3?9 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices than the clock-to-high-impedance time (t xz ). stratix and stratix gx device i/o pins can interface with zbt sram devices at up to 200 mhz and can meet zbt t co and t su timing requirements by controlling phase delay in clocks to the oe or output and inpu t registers using an enhanced pll. figure 3?6 shows a flow-through zbt sram operation where a1 and a3 are read addresses and a2 and a4 are write addresses. for pipelined zbt sram operation, data is delayed by another clock cycle. stratix and stratix gx devices support up to 200-mhz zbt sram operation using the 2.5-v or 3.3-v lvttl i/o standard. figure 3?6. t zx & t xz timing diagram interface pins zbt sram uses one system clock inpu t for all clocking purposes. only the rising edge of this clock is us ed, since zbt sram uses a single data rate scheme. the data bus, dq, is bi directional. there are three control signals to the zbt sram: rw_n , bw_n , and adv_ld_n . you can use any of the stratix and stratix gx device user i/o pins to interface to the zbt sram device. f for more information on zbt sram in terfaces in stratix devices, see an 329: zbt sram controller referenc e design for stratix & stratix gx devices . zbt bus sharing device t zx t xz t zx a1 a2 a3 a4 q(a1) q(a3) d(a3) clock addr dataout datain wren 3?10 altera corporation stratix device handbook, volume 2 june 2006 ddr memory support overview ddr memory support overview table 3?1 shows the external ram suppo rt in stratix ep1s10 through ep1s40 devices and all stratix gx devices. table 3?2 shows the external ram support in stratix ep1s60 and ep1s80 devices. table 3?1. external ram support in stratix ep1s 10 through ep1s40 & all stratix gx devices ddr memory type i/o standard maximum clock rate (mhz) -5 speed grade -6 speed grade -7 speed grade -8 speed grade flip-chip flip-chip wire- bond flip- chip wire- bond flip- chip wire- bond ddr sdram (1) , (2) sstl-2 200 167 133 133 100 100 100 ddr sdram - side banks (2) , (3) , (4) sstl-2 150 133 110 133 100 100 100 rldram ii (4) 1.8-v hstl 200 (5) (5) (5) (5) (5) (5) qdr sram (6) 1.5-v hstl 167 167 133 133 100 100 100 qdrii sram (6) 1.5-v hstl 200 167 133 133 100 100 100 zbt sram (7) lvttl 200 200 200 167 167 133 133 notes to ta b l e 3 ? 1 : (1) these maximum clock rates apply if the stratix device uses dqs phase-shift circuit ry to interface with ddr sdram. dqs phase-shift circuitry is only available on th e top and bottom i/o banks (i/o banks 3, 4, 7, and 8). (2) for more informati on on ddr sdram, see an 342: interfacing ddr sdram wi th stratix & stratix gx devices. (3) ddr sdram is supported on the stratix device side i/o banks (i/o banks 1, 2, 5, and 6) without dedicated dqs phase-shift circuitry. the read dqs signal is ignored in this mode. (4) these performance specifications are preliminary. (5) this device does not support rldram ii. (6) for more information on qdr or qdrii sram, see an 349: qdr sram controller reference design for stratix & stratix gx devices . (7) for more information on zbt sram, see an 329: zbt sram controller reference design for stratix and stratix gx devices . table 3?2. external ram support in stratix ep1s60 & ep1s80 (part 1 of 2) ddr memory type i/o standard maximum clock rate (mhz) -5 speed grade -6 speed grade -7 speed grade ddr sdram (1) , (2) sstl-2 167 167 133 ddr sdram - side banks (2) , (3) sstl-2 150 133 133 qdr sram (4) 1.5-v hstl 133 133 133 qdrii sram (4) 1.5-v hstl 167 167 133 altera corporation 3?11 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices stratix and stratix gx devices support th e data strobe or read clock signal (dqs) used in ddr sdram, and rldr am ii devices. dqs signals are associated with a group of data (dq) pins. stratix and stratix gx devices contain dedicated circuitry to shift the incoming dqs signals by 0, 72, an d 90. the dqs phase-shift circuitry uses a frequency reference to dynamica lly generate control signals for the delay chains in each of the dqs pi ns, allowing it to compensate for process, voltage, and temperature (pvt) variations. the dedicated circuitry also creates consistent ma rgins that meet your data sampling window requirements. f refer to the dc & switching characteristics chapter in volume 1 of the stratix device handbook for frequency limits regarding the 72 and 90 phase shift for dqs. in addition to the dqs dedicated phas e-shift circuitry, every i/o element (ioe) in stratix and strati x gx devices contains six registers and one latch to achieve ddr operation. there is also a programmable delay chain in the ioe that can help reduce cont ention when interfacing with zbt sram devices. ddr memory interface pins stratix and stratix gx devices use data (dq), data strobe (dqs), and clock pins to interface with ddr sdram and rldram ii devices. this section explains the pins used in the ddr sdram and rldram ii interfaces. for qdr, qdrii, and zbt sram interfaces, see the ?external memory standards? section. zbt sram (5) lvttl 200 200 167 notes to ta b l e 3 ? 2 : (1) these maximum clock rates apply if the stratix device uses dqs phase-shift circuit ry to interface with ddr sdram. dqs phase-shift circuitry is only available on th e top and bottom i/o banks (i/o banks 3, 4, 7, and 8). (2) for more informati on on ddr sdram, see an 342: interfacing ddr sdram wi th stratix & stratix gx devices. (3) ddr sdram is supported on the side banks (i/o banks 1, 2, 5, and 6) with no dedicat ed dqs phase-shift circuitry. the read dqs signal is ignored in this mode. (4) for more information on qdr or qdrii sram, see an 349: qdr sram controller reference design for stratix & stratix gx devices . (5) for more informati on on zbt sram, see an 329: zbt sram controller reference design for stratix and stratix gx devices . table 3?2. external ram support in stratix ep1s60 & ep1s80 (part 2 of 2) ddr memory type i/o standard maximum clock rate (mhz) -5 speed grade -6 speed grade -7 speed grade 3?12 altera corporation stratix device handbook, volume 2 june 2006 ddr memory support overview figure 3?7 shows the dq and dqs pins in 8 mode. figure 3?7. stratix & stratix gx devi ce dq & dqs groups in 8 mode note to figure 3?7 : (1) there are at least eight dq pins per group. data & data strobe pins stratix and stratix gx data pins for the ddr memory interfaces are called dq pins. the stratix and stratix gx device i/o banks at the top (i/o banks 3 and 4) and the bottom (i/o banks 7 and 8) of the device support ddr sdram and rldram ii up to 200 mhz. these pins support dqs signals with dq bus modes of 8, 16, or 32. stratix and stratix gx devices can support either bidirectio nal data strobes or uni-directional read clocks. depending on the extern al memory interface, either the memory device's read data strobes or read clocks feed the dqs pins. for 8 mode, there are up to 20 groups of programmable dqs and dq pins?10 groups in i/o banks 3 and 4 and 10 groups in i/o banks 7 and 8 (see table 3?3 ). each group consists of one dqs pin and a set of eight dq pins. for 16 mode, there are up to eight groups of programmable dqs and dq pins?four groups in i/o banks 3 and 4, and four groups in i/o banks 7 and 8. the ep1s20 device su pports seven 16 mode groups. the ep1s10 device does not support 16 mode. all other devices support the full eight groups. see table 3?3 . each group consists of one dqs and 16 dq pins. in 16 mode, dqs1t , dqs3t , dqs6t , and dqs8t pins on the top side of the device, and dqs1b , dqs3b , dqs6b , and dqs8b pins on the d q p in s ( 1 ) d q s p in top or bottom i/o bank altera corporation 3?13 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices bottom side of the device are dedicated dqs pins. the dqs2t , dqs7t , dqs2b , and dqs7b pins are dedicated dqs pins for 32 mode, and each group consists of one dqs and 32 dq pins. table 3?3. dqs & dq bus mode support note (1) device package number of 8 groups number of 16 groups number of 32 groups ep1s10 672-pin bga 672-pin fineline bga ? 12 (2) 00 484-pin fineline bga 780-pin fineline bga 16 (3) 04 ep1s20 484-pin fineline bga 18 (4) 7 (5) 4 672-pin bga 672-pin fineline bga 16 (3) 7 (5) 4 780-pin fineline bga 20 7 (5) 4 ep1s25 672-pin bga 672-pin fineline bga 16 (3) 84 780-pin fineline bga 1,020-pin fineline bga 20 8 4 ep1s30 956-pin bga 780-pin fineline bga 1,020-pin fineline bga 20 8 4 ep1s40 956-pin bga 1,020-pin fineline bga 1,508-pin fineline bga 20 8 4 ep1s60 956-pin bga 1,020-pin fineline bga 1,508-pin fineline bga 20 8 4 ep1s80 956-pin bga 1,508-pin fineline bga 1,923-pin fineline bga 20 8 4 notes to ta b l e 3 ? 3 : (1) for v ref guidelines, see the selectable i/o standards in stratix & stratix gx devices chapter of the stratix device handbook, volume 2 or the stratix gx handbook, volume 2 . (2) these packages have six groups in i/o banks 3 and 4 and six groups in i/o banks 7 and 8. (3) these packages have eight grou ps in i/o banks 3 and 4 and eigh t groups in i/o banks 7 and 8. (4) this package has nine groups in i/o banks 3 and 4 and nine groups in i/o banks 7 and 8. (5) these packages have three groups in i/o banks 3 and 4 and four groups in i/o banks 7 and 8. 3?14 altera corporation stratix device handbook, volume 2 june 2006 ddr memory support overview the dqs pins are marked in the stratix and stratix gx device pin table as dqs[9..0]t or dqs[9..0]b , where t stands for top and b for bottom. the corresponding dq pins are marked as dq[9..0]t[7..0] , where [9..0] indicates which dqs group the pins belong to. the numbering scheme starts from right to left on the package bottom view. when not used as dq or dqs pins, these pins are available as user i/o pins. you can also create a design in a mode other than the 8, 16, or 32 mode. the quartus ? ii software uses the next larger mode with the unused dq pins available as regula r use i/o pins. for example, if you create a design for 9 mode for an rldram ii interface (nine dq pins driven by one dqs pin), the quartus i i software implements a 16 mode with seven dq pins unconnected to the dqs bus. these seven unused dq pins can be used as regular i/o pins. 1 on the top and bottom side of the device, the dq and dqs pins must be configured as bidirectional ddr pins to enable the dqs phase-shift circuitry. if you only want to use the dq and/or dqs pins as inputs, you need to set the output enable of the dq and/or dqs pins to ground. use the altdqs and altdq megafunctions to configure the dqs and dq pins, respectively. however, you should use the altera ? ip toolbench to create the data path for your memory interfaces. stratix and stratix gx device side i/o banks (i/o banks 1, 2, 5, and 6) support sdr sdram, zbt sram, qdr sram, qdrii sram, and ddr sdram interfaces and can use any of th e user i/o pins in these banks for the interface. since these i/o banks do not have any dedicated circuitry for memory interfacing, they can support ddr sdram up to 150 mhz in -5 speed grade devices. however, these i/o banks do not support the hstl-18 class ii i/o standard, whic h is required to interface with rldram ii. clock pins you can use any of the ddr i/o registers in the top or bottom bank of the device (i/o banks 3, 4, 7, or 8) to generate clocks to the memory device. you can also use any of the ddr i/o registers in the side i/o banks 1, 2, 5, or 6 to generate clocks for ddr sdram interfaces on the side i/o banks (not using the dqs circuitry). altera corporation 3?15 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices command & address pins you can use any of the user i/o pins in the top or bottom bank of the device (i/o banks 3, 4, 7, or 8) for commands and addresses. for ddr sdram, you can also use any of the us er i/o pins in th e side i/o banks 1, 2, 5, or 6, regardless of whethe r you use the dqs phase-shift circuitry or not. other pins (parity, dm, ecc & qvld pins) you can use any of the dq pins fo r the parity pins in stratix and stratix gx devices. however, this may mean that you are using the next larger dqs/dq mode. for example, if you need a parity bit for each byte of data, you are actually going to ha ve nine dq pins per dqs pin. the quartus ii software then implements a 16 mode, with the seven unused dq pins available as user i/o pins. the data mask (dm) pins are only required when writing to ddr sdram and rldram ii devices. a low signal on the dm pins indicates that the write is valid. if the dm signal is high, the memory masks the dq signals. you can use any of the i/o pins in the same bank as the dq pins for the dm signals. each group of dqs and dq signals requires a dm pin. the ddr register , clocked by the ?90 shifted clock, creates the dm signals, similar to dq output signals. some ddr sdram devices support error correction coding (ecc), which is a method of detecting and automatically correc ting errors in data transmission. connect the ddr ecc pins to a stratix and stratix gx device dqs/dq group. in 72-bit ddr sdram, there are eight ecc pins in addition to the 64 data pins. the memory controller needs extra logic to encode and decode the ecc data. qvld pins are used in rldram ii interfacing to indicate the read data availability. there is one qvld pin per rldram ii device. a high on qvld indicates that the memory is outputting the data requested. similar to dq inputs, this signal is edge-aligned with the rldram ii read clocks, qk and qk#, and is sent half a clock cycle before data starts coming out of the memory. you can connect qvld pins to any of the i/o pins in the same bank as the dq pins for the qvld signals. dqs phase-shift circuitry two single phase-shifting reference circuits are located on the top and bottom of the stratix and stratix gx devices. each circuit is driven by a system reference clock that is of th e same frequency as the dqs signal. clock pins clk[15..12]p feed the phase-shift circuitry on the top of the device and clock pins clk[7..4]p feed the phase-shift circuitry on the 3?16 altera corporation stratix device handbook, volume 2 june 2006 ddr memory support overview bottom of the device. the phase-shift circuitry cannot be fed from other sources such as the le or the pll inte rnal output clocks . this phase-shift circuitry is used for ddr sdram and rldram ii interfaces. for best performance, turn off the input re ference clock to the dqs phase-shift circuitry when reading from the dd r sdram or rldram ii. this is to avoid any dll jitter incorrectly shif ting the dqs signal while the fpga is capturing data. 1 the i/o pins in i/o ba nks 1, 2, 5, and 6 can interface with the ddr sdram at up to 150 mhz. see an 342: interfacing ddr sdram with stratix & stratix gx devices . a compensated delay element on each dqs pin allows for either a 90 or a 72 phase shift, which au tomatically centers inpu t dqs signals with the data valid window of their corresponding dq data signals. the dqs signals drive a local dqs bus within the top and bottom i/o banks. this dqs bus is an additional resource to the i/o clocks and clocks dq input registers with the dqs signal. f refer to the dc & switching characteristics chapter in volume 1 of the stratix device handbook for frequency limits regarding the 72 and 90 phase shift for dqs. the phase-shifting reference circuit on the top of the device controls the compensated delay elements for all 10 dqs pins located at the top of the device. the phase-shifting reference circuit on the bottom of the device controls the compensated delay elements for all 10 dqs pins located on the bottom of the device. all 10 delay el ements (dqs signals) on either the top or bottom of the device shift by the same degree amount. for example, all 10 dqs pins on the top of the device can be shifted by 90 and all 10 dqs pins on the bottom of the device can be shifted by 72. the reference circuit requires a maximum of 256 system refere nce clock cycles to set the correct phase on the dqs delay elements. 1 this applies only to the initial phase calculation. altera recommends that you enable the dll during the refresh cycle of the ddr sdram. enabling the dll for the duration of the minimum refresh time is sufficient for recalculating the phase shift. figure 3?8 shows the phase-shift reference circuit control of each dqs delay shift on the top of the device. th is same circuit is duplicated on the bottom of the device. altera corporation 3?17 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices figure 3?8. dqs & dqsn pins & t he dqs phase-shift circuitry note (1) notes to figure 3?8 : (1) there are up to 10 dqs and dqsn pins available on the top or the bottom of the stra tix and stratix gx devices. (2) clock pins clk[15..12]p feed the phase-shift circuitry on the top of the device and clock pins clk[7..4]p feed the phase circuitry on the bottom of the device. the reference clock can also be used in the logic array. the phase-shift circuitry is only used during read transactions where the dqs pins are acting as in put clocks or strobes. the phase-shift circuitry can shift the incoming dqs signal by 0, 72, and 90. the shifted dqs signal is then inverted and used as a clock or a strobe at the dq ioe input registers. f refer to the dc & switching characteristics chapter in volume 1 of the stratix device handbook for frequency limits regarding the 72 and 90 phase shift for dqs. the dqs phase-shift circuitry is bypa ssed when 0 shift is chosen. the routing delay between the pins and the ioe registers is matched with high precision for both the dq and dqs signal when the 72 or 90 phase shift is used. with the 0 phase shif t, the skew between dq and the dqs signals at the ioe register has been minimized. see table 3?4 for the quartus ii software reported number on the dq and dqs path to the ioe when the dqs is set to 0 phase shift. dqs pin dqs pin dqs pin dqs pin dqs pin dqs pin dqs pin dqs pin dqs pin dqs pin phase shift reference circuit t t t t t t t t t t dqs bus c o mpe n sated de l a y el eme n t clk[15..12] ( 2 ) table 3?4. quartus ii reported number on the dqs path to the ioe note (1) speed grade dq2ioe dqs2ioe unit -5 0.908 1.008 ns -6 0.956 1.061 ns -7 1.098 1.281 ns 3?18 altera corporation stratix device handbook, volume 2 june 2006 ddr memory support overview to generate the correct phase shift, you must provide a clock signal of the same frequency as the dqs signal to the dqs phase-shift circuitry. any of the clk[15..12]p clock pins can feed the phase circuitry on the top of the device (i/o banks 3 and 4) and any of the clk[7..4]p clock pins can feed the phase circuitry on th e bottom of the device (i/o banks 7 and 8). both the top and bottom phase- shift circuits need unique clock pins for the reference clock. you cann ot use any internal clock sources to feed the phase-shift circ uitry, but you can route internal clock sources off-chip and then back into one of the allowable clock input pins. dll the dqs phase-shift circuitry uses a dll to dynamically measure the clock period needed by the dqs pin (see figure 3?9 ). the dqs phase-shift circuitry then uses the clock period to generate the correct phase shift. the dll in the stratix and stratix gx devices dqs phase- shift circuitry can operate between 100 and 200 mhz. the phase-shift circuitry needs a maximum of 256 clock cycles to calculate the correct phase shift. data sent during thes e clock cycles may not be properly captured. 1 you can still use the dqs phase-shift circuitry for ddr sdram interfaces that are less than 100 mhz. the dqs signal is shifted by about 2.5 ns. this shifted dqs si gnal is not in the center of the dq signals, but it is shifted enou gh to capture the correct data in this low-frequency application. -8 1.293 1.635 ns note to ta b l e 3 ? 4 : (1) these are reported by quartus ii versio n 4.0. check the latest version of the quartus ii software for the most current information. table 3?4. quartus ii reported number on the dqs path to the ioe note (1) speed grade dq2ioe dqs2ioe unit altera corporation 3?19 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices figure 3?9. simplified diagram of the dqs phase-shift circuitry the input reference clock goes into the dll to a chain of delay elements. the phase comparator compares the si gnal coming out of the end of the delay element chain to the input refe rence clock. the phase comparator then issues the upndn signal to the up/down counter. this signal increments or decrements a six-bit de lay setting (control signals to dqs pins) that increases or decreases the delay through the delay element chain to bring the input reference cloc k and the signals co ming out of the delay element chain in phase. the shifted dqs signal then goes to the dqs bus to clock the ioe input registers of the dq pins. it cannot go into the logic array for other purposes. for external memory interfaces that use a bidirectional read strobe like ddr sdram, the dqs signal is low before going to or coming from a high-impedance state (see figure 3?1 on page 3?3 ). the state where dqs is low just after a high-impedance st ate is called the preamble and the state where dqs is low just before it returns to high-impedance state is called the postamble. there are prea mble and postamble specifications for both read and write operations in ddr sdram. to ensure data is not lost when there is noise on the dqs line at the end of a read postamble time, you need to add soft postamble ci rcuitry to disable the clocks at the dq ioe registers. f for more information, the dqs postamble soft logic is described in an 342: interfacing ddr sdram with stratix & stratix gx devices . the altera ddr sdram controller megacore ? generates this logic as open-source code. phase comparator up/down counter delay chains input reference clock control signals to dqs pins 6 3?20 altera corporation stratix device handbook, volume 2 june 2006 ddr memory support overview ddr registers each stratix and stratix gx ioe contai ns six registers an d one latch. two registers and a latch are used for input, two registers are used for output, and two registers are used for output enable control. the second output enable register provides the write preamble for the dqs strobe in the ddr external memory interfaces. th is negative-edge output enable register extends the high-impedance state of the pin by a half clock cycle to provide the external memory's dqs preamble time specification. figure 3?10 shows the six registers and the latch in the stratix and stratix gx ioe and figure 3?11 shows how the second oe register extends the dqs high impedance state by half a clock cycle during a write operation. altera corporation 3?21 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices figure 3?10. bidirectional dd r i/o path in stratix & stratix gx devices note (1) notes to figure 3?10 : (1) all control signals can be inverted at the ioe. no programmable delay chains are shown in this diagram. (2) the oe signal is active low, but the qu artus ii software implements this as act ive high and automatically adds an inverter before input to the a oe register during compilation. (3) the a oe register generates the enable signal for general-purpose ddr i/o applications. (4) this select line is to choose whether the oe signal should be delayed by half-a-clock cycle. (5) the b oe register generates the delayed enable signal for th e write strobes and write cl ock for memory interfaces. (6) the tristate enable is active low by default. you can de sign it to be active high. th e combinational control path for the tristate is not shown in this diagram. (7) you can also have combinational output to th e i/o pin; this path is not shown in the diagram. d q dff d q ena d q dff input register b i input register a i latch c dq dff dq dff 0 1 output register a o output register b o dq dff dq dff or2 tri i/o pin (7) oe register b oe oe register a oe logic array dataout_l dataout_h outclock datain_h datain_l oe inclock neg_reg_out i 0 (5) (4) (6) (3) combout 1 (2) latch tchla 3?22 altera corporation stratix device handbook, volume 2 june 2006 ddr memory support overview figure 3?11. extending the oe disable by ha lf-a-clock cycle for a write transaction note (1) note to figure 3?11 : (1) the waveform reflects the so ftware simulation result. the oe signal is an active low on the device. however, the quartus ii software implements this signal as an active high and automatically adds an inverter before the a oe register d input. figures 3?12 and 3?13 summarize the ioe registers used for the dq and dqs signals. d0 d0 d2 d1 d1 d3 d2 d3 preamble postamble system clock (outclock for dqs) oe for dqs (from logic array) datain_h (from logic array) datain_l (from logic array) oe for dq (from logic array) write clock (outclock for dq, ? 90 phase shifted from system clock) dqs dq delay by half a clock cycle 9 0 ? altera corporation 3?23 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices figure 3?12. dq configur ation in stratix & stratix gx ioe note (1) notes to figure 3?12 : (1) you can use the altdq megafunction to generate the dq signals. (2) the oe signal is active low, but the qu artus ii software implements this as act ive high and automatically adds an inverter before the oe register a oe during compilation. (3) the outclock signal is phase shifted ?9 0 from the system clock. (4) the shifted dqs signal must be inve rted before going to the ioe. the in version is automatic if you use the altdq megafunction to generate the dq signals. d q dff d q la tch ena d q dff input register a i input register b i latch c dq dff dq dff 0 1 dq dff tri dq pin oe register a oe output register a o output register b o logic array latch dataout_l dataout_h outclock (3) datain_h datain_l oe inclock (from dqs bus) neg_reg_out i (4) (2) 3?24 altera corporation stratix device handbook, volume 2 june 2006 ddr memory support overview figure 3?13. dqs configuration in stratix & stratix gx ioe note (1) notes to figure 3?13 : (1) you can use the altdq s megafunction to generate the dqs signals. (2) the oe signal is active low, but the qu artus ii software implements this as act ive high and automatically adds an inverter before oe register a oe during compilation. (3) the select line can be chosen in the altdqs megawizard plug-in manager. (4) the datain_l and datain_h pins are usually connected to v cc and ground, respectively. (5) dqs postamble handling is not shown in this diagram. for more information, see an 342: interfacing ddr sdram with stratix & st ratix gx devices . (6) this undelayed dqs signal goes to th e le for the soft postamble circuitry. (7) you must invert this signal before it reaches the dq ioe. this signal is automatically inverted if you use the altdq megafunction to generate the dq signals. connect this port to the inclock port in the altdq megafunction. (8) dqs phase-shift circuitry is only available on dqs pins. dq dff dq dff 0 1 output register b o output register a o oe register b oe oe register a oe dq dff dq dff or2 tri dqs pin (5 ) logic array system clock datain_l (4) datain_h (3) oe (3) combout (7) (2) 0 1 dqs phase shift circuitry (8) undelayed dqs (6) altera corporation 3?25 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices the stratix and stratix gx ddr ioe st ructure requires you to invert the incoming dqs signal by using a not ga te to ensure proper data transfer. the altdq megafunction autom atically adds the inverter when it generates the dq signals. as shown in figure 3?10 , the inclock signal's rising edge clocks the a i register, inclock signal's falling edge clocks the b i register, and latch c i is opened when inclock is one. in a ddr memory read operation, the last data coincides with dqs being low. if you do not invert the dqs pin, you do not get this last data because the latch does not open until the next ri sing edge of the dqs signal. the not gate is inserted automatically if the altdg megafunction is used; otherwise you need to add the not gate manually. figure 3?14 shows waveforms of the circuit shown in figure 3?12 . the second set of waveforms in figure 3?14 shows what happens if the shifted dqs signal is not inverted; the last data, d n , does not get latched into the logic array as dqs goes to tristate after the read postamble time. the third set of waveforms in figure 3?14 shows a proper read operation with the dqs signal inverted after the 90 shift; the last data d n does get latched. in this case the outputs of register a i and latch c i , which correspond to dataout_h and dataout_l ports, are now switched because of the dqs inversion. 3?26 altera corporation stratix device handbook, volume 2 june 2006 ddr memory support overview figure 3?14. dq captures with non- inverted & inverted shifted dqs dq at the pin dqs shifted by 90? output of register a 1 (dataout_h) output of latch c 1 (dataout_l) output of register b 1 dqs inverted and shifted by 90? output of register a 1 (dataout_h) output of latch c 1 (dataout_l) output of register b 1 dqs at the pin shifted dqs signal is not inverted shifted dqs signal is inverted dq & dqs signals d n ? 1 d n ? 2 d n ? 2 d n ? 2 d n ? 1 d n d n d n ? 3 d n ? 1 d n ? 1 d n altera corporation 3?27 june 2006 stratix device handbook, volume 2 external memory interfaces in stratix & stratix gx devices pll when using the stratix and stratix gx top and bottom i/o banks (i/o banks 3, 4, 7, or 8) to interface with a ddr memory, at least one pll with two outputs is needed to generate the system clock and the write clock. the system clock generates the dqs write signals, commands, and addresses. the write clock is ?90 shifted from the system clock and generates the dq signals during writes. when using the stratix and stratix gx side i/o banks 1, 2, 5, or 6 to interface with ddr sdram devices, two plls may be needed per i/o bank for best performance. the side i/o banks do not have dedicated circuitry, so one pll captures data from the ddr sdram and another pll generates the write signals, commands, and addresses to the ddr sdram device. stratix and stratix gx devices side i/o banks can support ddr sdram up to 150 mhz. f for more information, see an 342: interfacing ddr sdram with stratix & stratix gx devices . conclusion stratix and stratix gx devices support sdr sdram, ddr sdram, rldram ii, qdr sdram, qdrii sra m, and zbt sram external memories. stratix and stratix gx devi ces feature high-speed interfaces that transfer data between exte rnal memory devices at up to 200 mhz/400 mbps. phase-shift circuitr y in the stratix and stratix gx devices allows you to ensure that clock edges are properly aligned. 3?28 altera corporation stratix device handbook, volume 2 june 2006 conclusion altera corporation section iii?1 section iii. i/o standards this section provides information on stratix ? single-ended, voltage- referenced, and differential i/o standards. it contains the fo llowing chapters: chapter 4, selectable i/o standards in stratix & stratix gx devices chapter 5, high-speed differential i/o interfaces in stratix devices revision history the table below shows th e revision history for chapters 4 and 5 . chapter date/version changes made comments 4 june 2006, v3.4 updated ?ac hot socketing specification? section. july 2005, v3.3 updated ?non-voltage-referenced standards? section. minor change to table 4?6 . january 2005, v3.2 updated content throughout. section iii?2 altera corporation i/o standards stratix device handbook, volume 2 september 2004, v3.1 table 4?1 on page 4?1 : renamed table, updated table, and added note 1. deleted figure named ?1.5-v di fferential hstl class ii termination.? updated text describing ?sstl-18 class i & ii - eia/jedec preliminary standard jc42.3? on page 4?11 . updated hypertransport data rates on page 4?17 . changed hypertransport device speed from 800 mhz to 400 mhz on page 4?17 . added four rows to table 4?2 on page 4?18 : 1.5- v hstl class i, 1.8-v hstl class i, 1.5-v hstl class ii, and 1.8-v hstl class ii. changed title of table 4?3 on page 4?21 . updated table 4?4 on page 4?22 . updated figure 4?20 on page 4?29 . added description of which clock pins support differential on-chip termination on page 4?30 . updated description of flip-chip packages on page 4?31 . changed title of figure 4?21 on page 4?31 . updated milliamps for non- thermally enhanced cavity up and non-thermally enhanced fineline bga packages on page 4?35 . updated equation for fineline bga package on page 4?35 . updated milliamps in non-t hermally enhanced cavity up and non-thermally enhanced fineline bga packages on page 4?37 . april 2004, v3.0 updated notes to figure 4?18 . new information added to the ?hot socketing? section. new information added to the ?differential pad placement guidelines? section. november 2003, v2.2 removed support for series and parallel on-chip termination. updated figure 4?22 . october 2003, v2.1 added the output enable group logic option in quartus ii and toggle rate logic option in quartus ii sections. updated notes to table 4?10 . july 2003, v2.0 renamed impedance matching to series termination throughout chapter. removed wide range specs for lvttl and lvcmos standards pages 4-3 to 4-5. relaxed restriction of input pins next to differential pins for flipchip packages (pages 4-20, 4-35, and 4-36). added drive strength section on page 4-26. removed text ?for 10 ns or less? from ac hot socketing specification on page 4-27. added series termination column to table 4-9. chapter date/version changes made comments altera corporation section iii?3 i/o standards 5 july 2005, v3.2 updated table 5?14 on page 5?58 . september 2004, v3.1 updated note 3 in table 5?10 on page 5?54 . updated table 5?7 on page 5?34 . updated table 5?8 on page 5?36 . updated description of ?r d differential termination? on page 5?46 . updated note 5 in table 5?14 on page 5?58 . updated notes 2, 5, and 7 in table 5?11 on page 5?56 through table 5?14 on page 5?58 . added new text about spanning two i/o banks on page 5?60 . april 2004, v3.0 updated notes for figure 5?17 . updated table 5?7 , 5?8 , and 5?10 . ?data alignment with clock? section, last sentence: change made from 90 degrees to 180 degrees. november 2003, v2.2 removed support for series and parallel on-chip termination. updated the number of channels per pll in tables 5-10 through 5-14. october 2003, v2.1 added -8 speed grade device information, including tables 5-7 and 5-8. july 2003, v2.0 format changes throughout chapter. relaxed restriction of input pins next to differential pins for flip chip packages in figure 5-1, note 5. wire bond package performance specification for ?high? speed channels was increased to 624 mbps from 462 mbps throughout chapter. updated high-speed i/o specificat ion for j=2 in tables 5-7 and 5-8. updated tables 5-10 to 5-14 to reflect pll cross-bank support for high-speed different ial channels at full speed. increased maximum output clock frequency to 462 to 500 mhz on page 5-66. chapter date/version changes made comments section iii?4 altera corporation i/o standards stratix device handbook, volume 2 altera corporation 4?1 june 2006 4. selectable i/o standards in stratix & stratix gx devices introduction the proliferation of i/o standards and the need for higher i/o performance have made it critical that devices have flexible i/o capabilities. stratix ? and stratix gx programmable logic devices (plds) feature programmable i/o pins that support a wide range of industry i/o standards, permitti ng increased design flexibility. these i/o capabilities enable fast time-to-mark et and high-perform ance solutions to meet the demands of complex system designs. additionally, stratix and stratix gx devices simplify system board design and make it easy to connect to microprocessors, periph erals, memories, gate arrays, programmable logic circuits, and standard logic functions. this chapter provides guidelines fo r using one or more industry i/o standards in stratix and stratix gx devices, including: stratix and stratix gx i/o standards high-speed interfaces stratix and stratix gx i/o banks programmable current drive strength hot socketing differential on-chip termination i/o pad placement guidelines quartus ? ii software support stratix & stratix gx i/o standards stratix and stratix gx devices support a wide range of industry i/o standards as shown in the stratix device family data sheet section in the stratix device handbook, volume 1 and the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 . several applications that use these i/o standards are listed in table 4?1 . table 4?1. i/o standard applications & performance (part 1 of 2) note (1) i/o standard application performance 3.3-v lvttl/lvcmos general purpose 350 mhz 2.5-v lvttl/lvcmos general purpose 350 mhz 1.8-v lvttl/lvcmos general purpose 250 mhz 1.5-v lvcmos general purpose 225 mhz pci/compactpci pc/embedded systems 66 mhz s52004-3.4 4?2 altera corporation stratix device handbook, volume 2 june 2006 stratix & stratix gx i/o standards 3.3-v low voltage transistor-transistor logic (lvttl) - eia/jedec standard jesd8-b the 3.3-v lvttl i/o standard is a general-purpose, single-ended standard used for 3.3-v applications . the lvttl standard defines the dc interface parameters for digital circuits operating from a 3.0-v or 3.3-v power supply and driving or being driven by lvttl-compatible devices. the lvttl input standard specifies a wider input voltage range of ?0.5 v v i 3.8 v. altera allows an in put voltage range of ?0.5 v v i 4.1 v. the lvttl standard does not require input reference voltages or board terminations. stratix and stratix gx devices support both input and output levels for 3.3-v lvttl operation. pci-x 1.0 pc/embedded systems 133 mhz agp 1 and 2 graphics processors 66 to 133 mhz sstl-3 class i and ii sdram 167 mhz sstl-2 class i and ii ddr i sdram 160 to 400 mbps hstl class i qdr sram/sram/csix 150 to 225 mhz hstl class ii qdr sram/sram/csix 150 to 250 mhz differential hstl clock interfaces 150 to 225 mhz gtl backplane driver 200 mhz gtl+ pentium processor interface 133 to 200 mhz lvds communications 840 mbps hypertransport technology motherboard interfaces 800 mbps lvpecl phy interface 840 mbps pcml communications 840 mbps differential sstl-2 ddr i sdram 160 to 400 mbps ctt back planes and bus interfaces 200 mhz note to ta b l e 4 ? 1 : (1) these performance values are dependent on device speed grade, package type (flip-chip or wirebond) and location of i/os (top/bottom or left/right). see the dc & switching characteristics chapter of the stratix device handbook, volume 1 . table 4?1. i/o standard applications & performance (part 2 of 2) note (1) i/o standard application performance altera corporation 4?3 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices 3.3-v lvcmos - eia/jedec standard jesd8-b the 3.3-v low voltage complement ary metal oxide semiconductor (lvcmos) i/o standard is a general-purpose, single-ended standard used for 3.3-v applications. the lvcmos standard defines the dc interface parameters for digital circuits operating from a 3.0-v or 3.3-v power supply and driving or being driven by lvcmos-compatible devices. the lvcmos standard specifies the sa me input voltage requirements as lvttl (?0.5 v v i 3.8 v). the output buffer drives to the rail to meet the minimum high-level output voltage requirements. the 3.3-v i/o standard does not require input refere nce voltages or board terminations. stratix and stratix gx devices support both input and output levels for 3.3-v lvcmos operation. 2.5-v lvttl normal voltage range - eia/jedec standard eia/jesd8-5 the 2.5-v i/o standard is used fo r 2.5-v lvttl applications. this standard defines the dc interfac e parameters for high-speed, low- voltage, non-terminated digital circuits driving or being driven by other 2.5-v devices. the input and output voltage ranges are: the 2.5-v normal range input stan dards specify an input voltage range of ? 0.3 v v i 3.0 v. the normal range minimum high-lev el output voltage requirement (v oh ) is 2.1 v. stratix and stratix gx devices support both input and output levels for 2.5-v lvttl operation. 2.5-v lvcmos normal voltage range - eia/jedec standard eia/jesd8-5 the 2.5-v i/o standard is used fo r 2.5-v lvcmos applications. this standard defines the dc interfac e parameters for high-speed, low- voltage, non-terminated digital circuits driving or being driven by other 2.5-v parts. the input and output voltage ranges are: the 2.5-v normal range input stan dards specify an input voltage range of ? 0.5 v v i 3.0 v. the normal range minimum v oh requirement is 2.1 v. 4?4 altera corporation stratix device handbook, volume 2 june 2006 stratix & stratix gx i/o standards stratix and stratix gx devices support both input and output levels for 2.5-v lvcmos operation. 1.8-v lvttl normal voltage range - eia/jedec standard eia/jesd8-7 the 1.8-v i/o standard is used fo r 1.8-v lvttl applications. this standard defines the dc interfac e parameters for high-speed, low- voltage, non-terminated digital circuits driving or being driven by other 1.8-v parts. the input and output voltage ranges are: the 1.8-v normal range input stan dards specify an input voltage range of ? 0.5 v v i 2.3 v. the normal range minimum v oh requirement is v ccio ?0.45 v. stratix and stratix gx devices support both input and output levels for 1.8-v lvttl operation. 1.8-v lvcmos normal voltage range - eia/jedec standard eia/jesd8-7 the 1.8-v i/o standard is used fo r 1.8-v lvcmos applications. this standard defines the dc interfac e parameters for high-speed, low- voltage, non-terminated digital circuits driving or being driven by other 1.8-v devices. the input and output voltage ranges are: the 1.8-v normal range input stan dards specify an input voltage range of ? 0.5 v v i 2.5 v. the normal range minimum v oh requirement is v ccio ?0.45 v. stratix and stratix gx devices support both input and output levels for 1.8-v lvcmos operation. 1.5-v lvcmos normal voltage range - eia/jedec standard jesd8-11 the 1.5-v i/o standard is used for 1.5-v applications . this standard defines the dc interface parameters for high-speed, low-voltage, non- terminated digital circuits driving or being driven by other 1.5-v devices. the input and output voltage ranges are: the 1.5-v normal range input stan dards specify an input voltage range of ? 0.5 v v i 2.0 v. the normal range minimum v oh requirement is 1.05 v. altera corporation 4?5 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices stratix and stratix gx devices support both input and output levels for 1.5-v lvcmos operation. 1.5-v hstl class i & ii - eia/jedec standard eia/jesd8-6 the high-speed transceiver logic (h stl) i/o standard is used for applications designed to operate in th e 0.0- to 1.5-v hstl logic switching range. this standard defines single ended input and output specifications for all hstl-compliant digital integrated circuits. the single ended input standard specifies an input voltage range of ? 0.3 v v i v ccio + 0.3 v. stratix and stratix gx devices suppo rt both input and output levels specified by the 1.5-v hstl i/o standard. the input clock is implemented using dedicated differen tial input buffers. two single- ended output buffers are automatically programmed to have opposite polarity so as to implement a differen tial output clock. additionally, the 1.5-v hstl i/o standard in stratix and stratix gx devices is compatible with the 1.8-v hstl i/o standard in apex tm 20ke and apex 20kc devices because the input and output voltage thresholds are compatible. see figures 4?1 and 4?2 . stratix and stratix gx devices support both input and output levels with v ref and v tt . figure 4?1. hstl class i termination figure 4?2. hstl class ii termination output buffer input buffer v tt = 0.75 v 50 z = 50 v ref = 0.75 v output buffer input buffer v tt = 0.75 v 50 v tt = 0.75 v 50 z = 50 v ref = 0.75 v 4?6 altera corporation stratix device handbook, volume 2 june 2006 stratix & stratix gx i/o standards 1.5-v differential hstl - eia/jedec standard eia/jesd8-6 the differential hstl i/o standard is used for applications designed to operate in the 0.0- to 1.5-v hstl logi c switching range such as quad data rate (qdr) memory clock interfaces. the differential hstl specification is the same as the single ended hstl specification. the standard specifies an input voltage range of ? 0.3 v v i v ccio + 0.3 v. differential hstl does not require an input reference voltage, however, it does require a 50 resistor termination resistor to v tt at the input buffer (see figure 4?3 ). stratix and stratix gx devices support both input and output clock levels for 1.5-v differential hstl. the input clock is implemented using dedicated differential input buffer. two single-ended output buffers are automatically pr ogrammed to have opposi te polarity so as to implement a differential output clock. figure 4?3. 1.5-v differential hstl class i termination 3.3-v pci local bus - pci specia l interest group pci local bus specification rev. 2.3 the pci local bus specification is used for applications that interface to the pci local bus, which provides a processor-independent data path between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. the conventional pci specification revision 2.3 define s the pci hardware environment including the protocol, electrical, mechanical, and configuration specifications for the pci devices an d expansion boards. this standard requires 3.3-v v ccio . stratix and stratix gx de vices are fully compliant with the 3.3-v pci local bus specification revision 2.3 and meet 64-bit/66-mhz operating frequency an d timing requirements. the 3.3-v pci standard does not require input reference voltages or board terminations. stratix and stratix gx devices support both input and output levels. differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.75 v v tt = 0.75 v altera corporation 4?7 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices 3.3-v pci-x 1.0 local bus - pci-sig pci-x local bus specification revision 1.0a the pci-x 1.0 standard is used for a pplications that interface to the pci local bus. the standard enables the design of systems and devices that operate at clock speeds up to 133 mhz, or 1 gigabit per second (gbps) for a 64-bit bus. the pci-x 1.0 protoco l enhancements enable devices to operate much more efficiently, providing more usable bandwidth at any clock frequency. by using the pci-x 1.0 standard, devices can be designed to meet pci-x 1.0 requirements an d operate as conventional 33- and 66-mhz pci devices when installed in those systems. this standard requires 3.3-v v ccio. stratix and stratix gx devices are fully compliant with the 3.3-v pci-x specification revision 1.0a and meet the 133-mhz operating frequency and timing requ irements. the 3.3-v pci standard does not require input reference volt ages or board terminations. stratix and stratix gx devices support both input and output levels. 3.3-v compact pci bus - pci sig pci local bus specification revision 2.3 the compact pci local bus specificatio n is used for applications that interface to the pci loca l bus. it follows the pci local bus specification revision 2.3 plus additional requirements in pci industrial computers manufacturing group (picmg) sp ecifications picmg 2.0 r3.0, compactpci specification, and the h ot swap requirements in picmg 2.1 r2.0, compactpci hot swap specification. this standard has similar electrical requirem ents as lvttl and requires 3.3-v v ccio. stratix and stratix gx devices are compliant with the compact pci electrical requirements. the 3.3-v pci standard does not require input reference voltages or board terminations. st ratix and stratix gx devices support both input and output levels. 3.3-v 1 agp - intel corporation accelerated graphics port interface specification 2.0 the agp interface is a platform bu s specification that enables high- performance graphics by providing a dedicated high-speed port for the movement of large blocks of 3-dime nsional texture data between a pc's graphics controller and system memory. the 1 agp i/o standard is a single-ended standard used for 3.3-v graphics appl ications. the 1 agp input standard specifies an input voltage range of ?0.5v v i v ccio + 0.5 v. the 1 agp standard does not require input reference voltages or board terminations. stratix and stratix gx devices support both input and output levels. 4?8 altera corporation stratix device handbook, volume 2 june 2006 stratix & stratix gx i/o standards 3.3-v 2 agp - intel corporation accelerated graphics port interface specification 2.0 the 2 agp i/o standard is a voltage-referenced, single-ended standard used for 3.3-v graphics applications. the 2 agp input standard specifies an input voltage range of ? 0.5v v i v ccio + 0.5v. the 2 agp standard does not require board terminations. stratix and stratix gx devices support both input and output levels. gtl - eia/jedec standard eia/jesd8-3 the gtl i/o standard is a low-level, high-speed back plane standard used for a wide range of applicat ions from asics and processors to interface logic devices. the gtl standard defines the dc interface parameters for digital circuits operat ing from power supplies of 2.5, 3.3, and 5.0 v. the gtl standard is an open-drain standard , and stratix and stratix gx devices support a 2.5- or 3.3-v v ccio to meet this standard. gtl requires a 0.8-v v ref and open-drain outputs with a 1.2-v v tt (see figure 4?4 ). stratix and stratix gx devices support both input and output levels. figure 4?4. gtl termination gtl+ the gtl+ i/o standard is used for high-speed back plane drivers and pentium processor interfaces. the gtl+ standard defines the dc interface parameters for digital circuits operating from power supplies of 2.5, 3.3, and 5.0 v. the gtl+ standa rd is an open-drain standard, and stratix and stratix gx devices support a 2.5- or 3.3-v v ccio to meet this standard. gtl+ requires a 1.0-v v ref and open-drain outputs with a 1.5-v v tt (see figure 4?5 ). stratix and stratix gx devices support both input and output levels. o u tp u t b u ffer in p u t b u ffe r v tt = 1.2 v 50 z = 50 v ref = 0.8 v v tt = 1.2 v 50 altera corporation 4?9 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices figure 4?5. gtl+ termination ctt - eia/jedec standard jesd8-4 the ctt i/o standard is used for ba ckplanes and memory bus interfaces. the ctt standard defines the dc interface parameters for digital circuits operating from 2.5- and 3.3-v power supplies. the ctt standard does not require special circuitry to interface with lvttl or lvcmos devices when the ctt driver is not terminated . the ctt standard requires a 1.5-v v ref and a 1.5-v v tt (see figure 4?6 ). stratix and stratix gx devices support both input and output levels. figure 4?6. ctt termination sstl-3 class i & ii - eia/jedec standard jesd8-8 the sstl-3 i/o standard is a 3.3-v memory bus standard used for applications such as high-speed sdram interfaces. this standard defines the input and output specificat ions for devices that operate in the sstl-3 logic switching range of 0.0 to 3.3 v. the sstl-3 standard specifies an input voltage range of ? 0.3 v v i v ccio + 0.3 v. sstl-3 requires a 1.5- v v ref and a 1.5-v v tt to which the series and termination resistors are connected (see figures 4?7 and 4?8 ). stratix and st ratix gx devices support both input and output levels. o u tp u t b u ffer in p u t b u ffe r v tt = 1.5 v 50 z = 50 v ref = 1.0 v v tt = 1.5 v 50 output buffer input buffer v tt = 1.5 v 50 z = 50 v ref = 1.5 v 4?10 altera corporation stratix device handbook, volume 2 june 2006 stratix & stratix gx i/o standards figure 4?7. sstl-3 class i termination figure 4?8. sstl-3 clas s ii termination sstl-2 class i & ii - eia/jedec standard jesd8-9a the sstl-2 i/o standard is a 2.5-v memory bus standard used for applications such as high-speed ddr sdram interfaces. this standard defines the input and output specificat ions for devices that operate in the sstl-2 logic switching range of 0.0 to 2.5 v. this standard improves operation in conditions where a bus must be isolated from large stubs. the sstl-2 standard specifies an input voltage range of ?0.3v v i v ccio + 0.3 v. sstl-2 requires a 1.25-v v ref and a 1.25-v v tt to which the series and terminat ion resistors are connected (see figures 4?9 and 4?10 ). stratix and stratix gx devices support both input and output levels. figure 4?9. sstl-2 class i termination output buffer input buffer v tt = 1.5 v 50 25 z = 50 v ref = 1.5 v output buffer input buffer v tt = 1.5 v 50 v tt = 1.5 v 50 25 z = 50 v ref = 1.5 v output buffer input buffer v tt = 1.25 v 50 25 z = 50 v ref = 1.25 v altera corporation 4?11 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices figure 4?10. sstl-2 clas s ii termination sstl-18 class i & ii - eia/jedec preliminary standard jc42.3 the sstl-18 i/o standard is a 1.8-v memory bus standard. this standard is similar to sstl-2 and defines input and output specifications for devices that are designed to operate in the sstl-18 logic switching range 0.0 to 1.8 v. sstl-18 requires a 0.9-v v ref and a 0.9-v v tt to which the series and termination resi stors are connected. see figures 4?11 and 4?12 for details on sstl-18 class i and ii termination. strati x and stratix gx devices support both input and output levels. figure 4?11. sstl-18 cl ass i termination figure 4?12. sstl-18 class ii termination differential sstl-2 - eia/jedec standard jesd8-9a the differential sstl-2 i/o standa rd is a 2.5-v standard used for applications such as high-speed ddr sdram clock interfaces. this standard supports differential signals in systems using the sstl-2 output buffer input buffer v tt = 1.25 v 50 v tt = 1.25 v 50 25 z = 50 v ref = 1.25 v output buffer input buffer v tt = 0.9 v 50 25 z = 50 v ref = 0.9 v output buffer input buffer v tt = 0.9 v 50 v tt = 0.9 v 50 25 z = 50 v ref = 0.9 v 4?12 altera corporation stratix device handbook, volume 2 june 2006 stratix & stratix gx i/o standards standard and supplements the sstl-2 standard for differential clocks. the differential sstl-2 standard specifies an input voltage range of ?0.3v v i v ccio + 0.3 v. the differential sstl-2 standard does not require an input reference voltage differential. see figure 4?13 for details on differential sstl-2 termination. st ratix and stratix gx devices support output clock levels for differential ss tl-2 class ii operation. the output clock is implemented using two sing le-ended output buffers which are programmed to have opposite polarity. figure 4?13. differential sstl- 2 class ii termination lvds - ansi/tia/eia st andard ansi/tia/eia-644 the lvds i/o standard is a differen tial high-speed, low-voltage swing, low-power, general-purpose i/o interface standard requiring a 3.3-v v ccio . this standard is used in applications requiring high-bandwidth data transfer, backplane driver s, and clock distribution. the ansi/tia/eia-644 standard specifies lvds transmitters and receivers capable of operating at recommended maximum data signaling rates of 655 mbps. however, devices can operate at slower speeds if needed, and there is a theoretical maximum of 1.923 gbps. stratix and stratix gx devices meet the ansi/tia/eia-644 standard. due to the low voltage swing of the lvds i/o standard, the electromagnetic interference (emi) ef fects are much smaller than cmos, ttl, and pecl. this low emi makes lvds ideal for applications with low emi requirements or noise immunity requirements. the lvds standard does not require an input re ference voltage, however, it does require a 100 termination resistor between the two signals at the input buffer. stratix and stratix gx device s include an optional differential lvds termination resistor within th e device using differential on-chip termination. stratix and stratix gx devices support both input and output levels. differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 1.25 v v tt = 1.25 v 50 50 v tt = 1.25 v v tt = 1.25 v 25 25 altera corporation 4?13 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices f for more information on the lvds i/o standard in stratix devices, see the high-speed differential i/o interfaces in stratix devices chapter. lvpecl the lvpecl i/o standard is a differen tial interface standard requiring a 3.3-v v ccio. the standard is used in applications involving video graphics, telecommunications, da ta communications, and clock distribution. the high-speed, low-voltage swing lvpecl i/o standard uses a positive power supply and is similar to lvds, however, lvpecl has a larger differential output voltage swing than lvds. the lvpecl standard does not require an input reference voltage, but it does require a 100- termination resistor between the two signals at the input buffer. see figures 4?14 and 4?15 for two alternate termination schemes for lvpecl. stratix and stratix gx devi ces support both input and output levels. figure 4?14. lvpecl dc coupled termination figure 4?15. lvpecl ac coupled termination pseudo current mode logic (pcml) the pcml i/o standard is a differ ential high-speed, low-power i/o interface standard used in applic ations such as networking and telecommunications. the standard requires a 3.3-v v ccio . the pcml i/o standard consumes less power than the lvpecl i/o standard. the output buffer input buffer 100 z = 50 z = 50 output buffer input buffe r 100 z = 50 z = 50 v ccio v ccio r2 r2 r1 r1 10 to 100 nf 10 to 100 nf 4?14 altera corporation stratix device handbook, volume 2 june 2006 stratix & stratix gx i/o standards pcml standard is similar to lvpecl, but pcml has a reduced voltage swing, which allows for a faster switching time and lower power consumption. the pcml standard uses open drain outputs and requires a differential output signal. see figure 4?16 for details on pcml termination. stratix and stratix gx devices support both input and output levels. additionally, stratix gx devices suppo rt 1.5-v pcml as described in the stratix gx device handbook, volume 1 . figure 4?16. pcml termination hypertransport technology - hypertransport consortium the hypertransport technology i/o standard is a differential high- speed, high-performance i/o interf ace standard requiring a 2.5-v v ccio . this standard is used in applications such as high-performance networking, telecommunications, embedded systems, consumer electronics, and internet connecti vity devices. the hypertransport technology i/o standard is a point-to-point standard in which each hypertransport technology bus co nsists of two point-to-point unidirectional links. each link is 2 to 32 bits. the hypertransport technology standard does not require an input reference voltage. however, it does require a 100- termination resistor between the two signals at the input buffer. see figure 4?17 for details on hypertransport technology termination. stratix an d stratix gx devices support both input and output levels. figure 4?17. hypertransport te chnology termination output buffer input buffe r 50 50 z = 50 z = 50 50 50 v tt output buffer input buffer 100 z = 50 z = 50 altera corporation 4?15 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices f see the stratix device family data sheet section in the stratix device handbook, volume 1 ; the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 ; and the high-speed differential i/o interfaces in stratix devices chapter for more information on differential i/o standards. high-speed interfaces in addition to current industry physical i/o standards, stratix and stratix gx devices also support a variety of emerging high-speed interfaces. this section provides an overview of these interfaces. oif-spi4.2 this implementation agreement is widely used in the industry for oc-192 and 10-gbps multi-service system interfaces. sonet and sdh are synchronous transmission systems over which data packets are transferred. pos-phy level 4 is a st andard interface for switches and routers, and defines the operation between a physical layer (phy) device and link layer devices (atm, internet protocol, and gigabit ethernet) for bandwidths of oc-192 atm, pos, an d 10-gigabit ethernet applications. some key pos-phy level 4 system features include: large selection of pos-phy level 4-based phys independent of data protocol wide industry support lvds i/o standard to improve signal integrity inband addressing/control out of band flow control scalable architecture over 622-mbps operation dynamic interface timing mode pos-phy level 4 operates at a wide range of frequencies. oif-sfi4.1 this implementation agreement is widely used in the industry for interfacing physical layer (phy) to the serializer-deserializer (serdes) devices in oc-192 and 10 gbps multi-service systems. the pos-phy level 4 interface standard defines the sfi-4 standard. pos-phy level 4: sfi-4 is a standardized 16-bit 622-mbps line-side interface for 10-gbps applications. internet lan and wan architectures use telecommunication sonet protocols for data transferring data over the phy layer. sfi-4 interfaces between oc-192 serdes and sonet framers. 4?16 altera corporation stratix device handbook, volume 2 june 2006 high-speed interfaces 10 gigabit ethernet sixteen bit interface (xsbi) - ieee draft standard p802.3ae/d2.0 10 gigabit ethernet xsbi is an interf ace standard for lans, metropolitan area networks (mans), storage area networks (sans), and wans. 10 gigabit ethernet xsbi provides many features for efficient, effective high-speed networking, including ea sy migration to higher performance levels without disruption, lower cost of ownership including acquisition and support versus other alternativ es, familiar management tools and common skills, ability to support new applications and data protocols, flexibility in network design, an d multiple vendor sourcing and interoperability. under the iso open systems interconnection (osi) model, ethernet is a layer 2 protocol. 10 gigabit ethernet xsbi uses the ieee 802.3 ethernet media access control (mac) protocol, ethernet frame format, and the minimum/maximum frame size. an ethernet phy corresponding to osi layer 1 connects the media to the mac layer that corresponds to osi layer 2. the phy is divided into a physical media dependent (pmd) element, such as optical transceive rs, and a physical coding sub-layer (pcs), which has coding and a serializer/multiplexor. this standard defines two phy types, including the lan phy and the wan phy, which are distinguished by the pcs. the 10 gigabit ethernet xsbi standard is a full-duplex technology standard that can increase the speed and distance of ethernet. rapidio interconnect spec ification revision 1.1 the rapidio interface is a communic ations standard used to connect devices on a circuit board and circuit boards on a backplane. rapidio is a packet-switched interconnect standa rd designed for embedded systems such as those used in networking and communications. the rapidio interface standard is a high-performan ce interconnect interface used for transferring data and control information between microprocessors, dsps, system memory, communications and network processors, and peripheral devices in a system. rapidio replaces existi ng peripheral bus and processor technologies such as pci. some features of rapidio include multiprocessing support, an open standard, flexible topologie s, higher bandwidth, low latency, error management support in hardwa re, small silicon footprint, widely available process and i/o technologi es, and transparency to existing applications and operating system software. the rapidio standard provides 10-gbps device bandwidth using 8-bit-wide input and output data ports. rapidio uses lvds technolo gy, has the capabili ty to be scaled to multi-ghz frequencies, an d features a 10-bit interface. altera corporation 4?17 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices hypertransport technology - hypertransport consortium the hypertransport technology i/o standard is a differential high-speed, high performance i/o interface standard developed for communications and networking chip-to-chip communications. hypertransport technology is used in applications such as high- performance networking , telecommunications, embedded systems, consumer electronics, and intern et connectivity devices. the hypertransport technology i/o standard is a point-to-point (one source connected to exactly one destination) standard that provides a high- performance interconnect be tween integrated circuits in a system, such as on a motherboard. stratix devices support hypertransport technology at data rates up to 800 mbps and 32 bits in each directio n. hypertransport technology uses an enhanced differential signaling technology to improve performance. hypertransport technology supports data widths of 2, 4, 8, 16, or 32 bits in each direction. hypertransport technology in stratix and stratix gx devices operates at multiple clock speeds up to 400 mhz. utopia level 4 ? atm forum te chnical committee standard af- phy-0144.001 the utopia level 4 frame-based interface standard allows device manufacturers and network developers to develop components that can operate at data rates up to 10 gbps. this standard increases interface speeds using lvds i/o and advanced si licon technologies for fast data transfers. utopia level 4 provides new control techniques and a 32-, 16-, or 8-bit lvds bus, a symmetric transmit/receive bus structure for easier application design and testability, nominal data rates of 10 gbps, in-band control of cell delimiters and flow co ntrol to minimize pin count, source- synchronous clocking, and supports variable length packet systems. utopia level 4 handles sustained data rates for oc-192 and supports atm cells. utopia level 4 also supports interconnections across motherboards, daughtercards, and backplane interfaces. stratix & stratix gx i/o banks stratix devices have eight i/o banks in addition to the four enhanced pll external clock output banks, as shown in table 4?2 and figure 4?18 . i/o banks 3, 4, 7, and 8 support all sing le-ended i/o standards. i/o banks 1, 2, 5, and 6 support differential hs tl (on input clocks), lvds, lvpecl, pcml, and hypertrans port technology, as well as all single-ended i/o standards except hstl class ii, gtl, sstl-18 class ii, pci/pci-x 1.0, and 1 /2 agp. the four enhanced pll external clock output banks (i/o banks 9, 10, 11, and 12) support clock outputs all single-ended i/o 4?18 altera corporation stratix device handbook, volume 2 june 2006 stratix & stratix gx i/o banks standards in addition to differential sstl-2 and hstl (both on the output clock only). since stratix devices su pport both non-voltage-referenced and voltage-referenced i/o standard s, there are different guidelines when working with either separate ly or when working with both. table 4?2. i/o standards supported in stratix i/o banks (part 1 of 2) i/o standard i/o bank enhanced pll external clock output banks 123456789101112 3.3-v lvttl/lvcmos vvvvvvvvvvvv 2.5-v lvttl/lvcmos vvvvvvvvvvvv 1.8-v lvttl/lvcmos vvvvvvvvvvvv 1.5-v lvcmos vvvvvvvvvvvv pci/pcix//compact pci vv vvvvvv agp 1 vv vvvvvv agp 2 vv vvvvvv sstl-3 class i vvvvvvvvvvvv sstl-3 class ii vvvvvvvvvvvv sstl-2 class i vvvvvvvvvvvv sstl-2 class ii vvvvvvvvvvvv sstl-18 class i vvvvvvvvvvvv sstl-18 class ii vv vvvvvv differential sstl-2 (output clocks) vvvv hstl class i vvvvvvvvvvvv 1.5-v hstl class i vvvvvvvvvvvv 1.8-v hstl class i vvvvvvvvvvvv hstl class ii vv vvvvvv 1.5-v hstl class ii vv vvvvvv 1.8-v hstl class ii vv vvvvvv differential hstl (input clocks) vvvvvvvv differential hstl (output clocks) vvvv gtl vv vvvvvv altera corporation 4?19 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices gtl+ vvvvvvvvvvvv ctt vvvvvvvvvvvv lv d s vv (1) (1) vv (1) (1) (2) (2) (2) (2) hypertransport technology vv (1) (1) vv (1) (1) (2) (2) (2) (2) lvpecl vv (1) (1) vv (1) (1) (2) (2) (2) (2) pcml vv (1) (1) vv (1) (1) (2) (2) (2) (2) notes to ta b l e 4 ? 2 : (1) this i/o standard is only supported on input clocks in this i/o bank. (2) this i/o standard is only supported on output clocks in this i/o bank. table 4?2. i/o standards supported in stratix i/o banks (part 2 of 2) i/o standard i/o bank enhanced pll external clock output banks 123456789101112 4?20 altera corporation stratix device handbook, volume 2 june 2006 stratix & stratix gx i/o banks figure 4?18. strati x i/o banks notes (1) , (2) , (3) notes to figure 4?18 : (1) figure 4?18 is a top view of the silicon die. this corresponds to a top-down view for non- flip-chip packages, but is a reverse view for flip-chip packages. (2) figure 4?18 is a graphic representation only. see the pin li st and the quartus ii software for exact locations. (3) banks 9 through 12 are enhanced pll external clock output banks. (4) if the high-speed differential i/o pins are not used for high-speed differential signaling, they can support all of the i/o standards except hs tl class ii, gtl, sstl-18 class ii, pci, pci-x 1.0, and agp 1/2. (5) for guidelines on placing single-ended i/ o pads next to differential i/o pads, see ?i/o pad placement guidelines? on page 4?30 . lv ds , lv p e c l, 3 . 3 -v pc ml, a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) lv ds , lv p e c l, 3 . 3 -v pc ml, a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) i/ o ba nk s 3 , 4, 9 & 10 s u pp o rt all s in g l e -en ded i/ o sta n dards i/ o ba nk s 7, 8 , 11 & 1 2 s u pp o rt all s in g l e -en ded i/ o sta n dards i/ o ba nk s 1, 2 , 5, a n d 6 s u pp o rt all s in g l e -en ded i/ o sta n dards ex cept d i ffere n t i a l h s tl o u tp u t c lo c k s , d i ffere n t i a l ss tl- 2 o u tp u t c lo c k s , h s tl c l ass ii, g tl, ss tl-1 8 c l ass ii, pc i, pc i-x 1.0, a n d a gp 1 / 2 dqs9t dqs8t dqs7t dqs6t dqs5t dqs4t dqs3t dqs2t dqs1t dqs0t pll5 vref1b3 vref2b3 vref3b3 vref4b3 vref5b3 vref1b4 vref2b4 vref3b4 vref4b4 vref5b4 vref5b8 vref4b8 vref3b8 vref2b8 vref1b8 vref5b7 vref4b7 vref3b7 vref2b7 vref1b7 pll6 dqs9b dqs8b dqs7b dqs6b dqs5b dqs4b dqs3b dqs2b dqs1b dqs0b 910 vref1b2 vref2b2 vref3b2 vref4b2 vref1b1 vref2b1 vref3b1 vref4b1 vref4b6 vref3b6 vref2b6 vref1b6 vref4b5 vref3b5 vref2b5 vref1b5 bank 5 bank 6 pll3 pll4 pll1 pll2 bank 1 bank 2 bank 3 bank 4 11 12 bank 8 bank 7 lv ds , lv p e c l, 3 . 3 -v pc ml, a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) lv ds , lv p e c l, 3 . 3 -v pc ml, a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) pll7 pll10 pll8 pll9 pll12 pll11 (5) (5) (5) (5) altera corporation 4?21 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices tables 4?3 and 4?4 list the i/o standards that stratix gx enhanced and fast pll pins support. figure 4?19 shows the i/o standards that each stratix gx i/o bank supports. table 4?3. i/o standards supported in stratix & stratix gx enhanced pll pins i/o standard input output inclk fbin pllenable extclk lv t t l vvvv lv c m o s vvvv 2.5 v vv v 1.8 v vv v 1.5 v vv v 3.3-v pci vv v 3.3-v pci-x 1.0 vv v lvpecl vv v 3.3-v pcml vv v lv d s vv v hypertransport technology vv v differential hstl vv differential sstl v 3.3-v gtl vv v 3.3-v gtl+ vv v 1.5-v hstl class i vv v 1.5-v hstl class ii vv v sstl-18 class i vv v sstl-18 class ii vv v sstl-2 class i vv v sstl-2 class ii vv v sstl-3 class i vv v sstl-3 class ii vv v agp (1 and 2 ) vv v ctt vv v 4?22 altera corporation stratix device handbook, volume 2 june 2006 stratix & stratix gx i/o banks table 4?4. i/o standards supported in stratix & stratix gx fast pll pins i/o standard input inclk pllenable lv t t l vv lv c m o s vv 2.5 v v 1.8 v v 1.5 v v 3.3-v pci 3.3-v pci-x 1.0 lvpecl v 3.3-v pcml v lv d s v hypertransport technology v differential hstl v differential sstl 3.3-v gtl 3.3-v gtl+ 1.5v hstl class i v 1.5v hstl class ii sstl-18 class i v sstl-18 class ii sstl-2 class i v sstl-2 class ii v sstl-3 class i v sstl-3 class ii v agp (1 and 2 ) ctt v altera corporation 4?23 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices figure 4?19. stratix gx i/o banks there is some flexibility with the number of i/o standards each stratix i/o bank can simultaneously support. the following sections provide guidelines for mixing non-voltage-referenced and voltage-referenced i/o standards in stratix devices. i/ o ba nk s 3 , 4, 6 & 7 s u pp o rt : 3 . 3 -, 2 .5-, 1. 8 -v lvttl 3 . 3 -v pc i, pc i-x 1.0 g tl g tl+ a gp c tt ss tl-1 8 c l ass i a n d ii ss tl- 2 c l ass i a n d ii ss tl- 3 c l ass i a n d ii h s tl c l ass i a n d ii in d ivi d u a l p ow er b u s i/o bank 3 i/o bank 1 i/o bank 2 i/ o ba nk s 1 & 2 s u pp o rt : d i ffere n t i a l i/ o sta n dards - t r u e lv ds - lv p e c l - 3 . 3 -v pc ml - hy per t ra n sp o rt t ec hnolo g y s in g l e -en ded i/ o sta n dard - 3 . 3 -, 2 .5 -, 1. 8 -v lvttl - g tl+ - c tt - ss tl-1 8 c l ass i - ss tl- 2 c l ass i a n d ii - ss tl- 3 c l ass i a n d ii - 1.5 -, 1. 8 -v h s tl c l ass i i/o bank 5 i/ o ba nk 5 c on ta in s t ra n sce iv er b lo c k s i/o bank 4 i/o bank 7 i/o bank 6 4?24 altera corporation stratix device handbook, volume 2 june 2006 stratix & stratix gx i/o banks non-voltage-referenced standards each stratix i/o bank has its own vccio pins and supports only one v ccio , either 1.5, 1.8, 2.5 or 3.3 v. a stratix i/o bank can simultaneously support any number of input sign als with different i/o standard assignments, as shown in table 4?5 . for output signals, a single i/o bank can only support non-voltage- referenced output signals driving at the same voltage as v ccio . a stratix i/o bank can only have one v ccio value, so it can only drive out that one value for non-voltage referenced signal s. for example, an i/o bank with a 2.5-v v ccio setting can support 2.5-v lvttl inputs and outputs, hypertransport technology inputs and outputs, and 3.3-v lvcmos inputs (not output or bidirectional pins). 1 if the output buffer overdrives the input buffer, you must turn on the allow voltage overdrive for lvttl/lvcmos option in the quartus ii software. to see this opti on, click the device & pin options button in the device page of the settings dialog box (assignments menu ). then click the pin placement tab in the device & pin options dialog box. voltage-referenced standards to accommodate voltage-referenced i/o standards, each stratix i/o bank supports multiple vref pins feeding a common vref bus. the number of available vref pins increases as device density increases. if these pins are not used as vref pins, they can not be used as generic i/o pins. table 4?5. acceptable input levels for lvttl/lvcmos bank v ccio acceptable input levels 3.3 v 2.5 v 1.8 v 1.5 v 3.3 v vv 2.5 v vv 1.8 v v (2) v (2) v v (1) 1.5 v v (2) v (2) vv notes to ta b l e 4 ? 5 : (1) because the input signal will not drive to the rail, the input buffer does not completely shut off, and the i/o current will be slightly higher than the default value. (2) these input values overdrive the input buffer, so the pin leakage current will be slightly higher than the default value. altera corporation 4?25 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices an i/o bank featuring single-ended or differential standards can support voltage-referenced standards as long as all voltage-referenced standards use the same v ref setting. for example, al though one i/o bank can implement both sstl-3 and sstl-2 i /o standards, i/o pins using these standards must be in different banks since they require different v ref values for voltage-referenced inputs, the receiver compares the input voltage to the voltage reference and does not take into account the v ccio setting. therefore, the v ccio setting is irrelevant for voltage referenced inputs. voltage-referenced bidirectional and output signals must be the same as the i/o bank?s v ccio voltage. for example, although you can place an sstl-2 input pin in any i/o bank with a 1.25-v v ref level, you can only place sstl-2 output pins in an i/o bank with a 2.5-v v ccio . mixing voltage referenced & non-voltage referenced standards non-voltage referenced and voltage referenced pins can safely be mixed in a bank by applying each of the rule-sets individually. for example, on i/o bank can support sstl-3 inpu ts and 1.8-v lvcmos inputs and outputs with a 1.8-v v ccio and a 1.5-v v ref . similarly, an i/o bank can support 1.5-v lvcmos, 3.3-v lvttl (inputs, but not outputs), and hstl i/o standards with a 1.5-v v ccio and 0.75-v v ref . for the voltage-referenced examples, see the ?i/o pad placement guidelines? section. for details on how the quartus ii software supports i/o standards, see the ?quartus ii software support? section. 4?26 altera corporation stratix device handbook, volume 2 june 2006 drive strength drive strength each i/o standard supported by stratix and stratix gx devices drives out a minimum drive strength. when an i/o is configured as lvttl or lvcmos i/o standards, you can spec ify the current drive strength, as summarized in table 4?7 . standard current drive strength each i/o standard supported by stratix and stratix gx devices drives out a minimum drive strength. table 4?6 summarizes the minimum drive strength of each i/o standard. when the sstl-2 class i and ii i/o standards are implemented on top or bottom i/o pins, the drive strength is designed to be higher than the drive strength of the buffer when implemented on side i/o pins. this allows the top or bottom i/o pins to support 200-mhz operation with the standard 35-pf load. at the same time, the current consumption when using top or bottom i/o pins is higher than the side i/o pins. the high current strength may not be necessar y for certain applications where the value of the load is less than the st andard test load (e.g., ddr interface). the quartus ii software allows you to reduce the drive strength when the i/o pins are used for the sstl-2 cl ass i or class ii i/o standard and being implemented on the top or bottom i/o through the current strength setting. select the minimum strength for lower drive strength. table 4?6. minimum current drive strength of each i/o standard i/o standard current strength, i ol /i oh (ma) gtl 40 (1) gtl+ 34 (1) sstl-3 class i 8 sstl-3 class ii 16 sstl-2 class i 8.1 sstl-2 class ii 16.4 sstl-18 class i 6.7 sstl-18 class ii 13.4 1.5-v hstl class i 8 1.5-v hstl class ii 16 ctt 8 agp 1 i ol = 1.5, i oh = ?0.5 note to ta b l e 4 ? 6 : (1) because this i/o standard uses an open drain buffer, this value refers to i ol . altera corporation 4?27 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices programmable current drive strength the stratix and stratix gx device i/o pins support various output current drive settings as shown in table 4?7 . these programmable drive strength settings help decrease the effects of simultaneously switching outputs (sso) in conjunction with reducing system noise. the supported settings ensure that the device driver meets the i oh and i ol specifications for the corresponding i/o standard. these drive-strength settings are programmable on a per-pin basis (for output and bidirectional pins only) using the quartus ii software. to modify the current strength of a particular pin, see ?programmable drive strength settings? on page 4?40 . hot socketing stratix devices support hot socketin g without any external components. in a hot socketing situation, a device?s output buffers are turned off during system power-up or power-do wn. stratix and stratix gx devices support any power-up or power-down sequence (v ccio and v ccint ) to simplify designs. for mixed-voltage environments, you can drive signals into the device before or during power-up or power-down without damaging the device. stratix and strati x gx devices do not drive out until the device is configured and has attained proper operating conditions. even though you can power up or down the v ccio and v ccint power supplies in any sequence you should not power down any i/o bank(s) that contains the configuration pi ns while leaving other i/o banks powered on. for power up and power down, all supplies (v ccint and all v ccio power planes) must be powered up and down within 100 ms of one another. this prevents i /o pins from driving out. table 4?7. programmable drive strength i/o standard i oh / i ol current strength setting (ma) 3.3-v lvttl 24 (1) , 16, 12, 8, 4 3.3-v lvcmos 24 (2) , 12 (1) , 8, 4, 2 2.5-v lvttl/lvcmos 16 (1) , 12, 8, 2 1.8-v lvttl/lvcmos 12 (1) , 8, 2 1.5-v lvcmos 8 (1) , 4, 2 notes to ta b l e 4 ? 7 : (1) this is the quartus ii soft ware default current setting. (2) i/o banks 1, 2, 5, and 6 do not support this setting. 4?28 altera corporation stratix device handbook, volume 2 june 2006 i/o termination you can power up or power down the v ccio and v ccint pins in any sequence. the power supply ramp rates can range from 100 ns to 100 ms. during hot socketing, the i/o pin capa citance is less than 15 pf and the clock pin capacitance is less than 20 pf. dc hot socketing specification the hot socketing dc specification is | i iopin | < 300 a. ac hot socketing specification the hot socketing ac specification is | i iopin | < 8 ma for 10 ns or less. this specification takes into account the pin capacitance, but not board trace and external loading capacitance. additional capacitance for trace, connector, and loading must be considered separately. i iopin is the current at any user i/o pin on the device. the dc specification applies when all vcc supplies to the device are stable in the powered-up or powered-down conditio ns. for the ac specification, the peak current duration because of power- up transients is 10 ns or less. for more information, refer to the hot-socketing & power-sequencing feature & testing for altera devices white paper. i/o termination although single-ended, non-voltage- referenced i/o standards do not require termination, altera recomm ends using external termination to improve signal integrity where required. the following i/o standards do not require termination: lvttl lvcmos 2.5 v 1.8 v 1.5 v 3.3-v pci/compact pci 3.3-v pci-x 1.0 3.3-v agp 1 voltage-referenced i/o standards voltage-referenced i/o standards require both an input reference voltage, v ref, and a termination voltage, v tt . off-chip termination on the board should be used for series and parallel termination. altera corporation 4?29 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices for more information on terminat ion for voltage-referenced i/o standards, see the selectable i/o standards in stratix & stratix gx devices chapter in the stratix device handbook, volume 2 ; or the stratix gx device handbook, volume 2 . differential i/o standards differential i/o standards typically require a termination resistor between the two signals at the receiver. the termination resistor must match the differential load impedance of the bus. stratix and stratix gx devices provide an optional differen tial termination on-chip resistor when using lvds. see the high-speed differential i/o in terfaces in stratix devices chapter for more information on differential i/o standards and their interfaces. for differential i/o standards, i/o banks support differential termination when v ccio equals 3.3 v. differential termination (r d ) stratix devices support differential on-chip termination for source- synchronous lvds signaling. the differential termination resistors are adjacent to the differential input bu ffers on the device. this placement eliminates stub effects, improving the signal integrity of the serial link. using differential on-chip termination resistors also saves board space. figure 4?20 shows the differential terminat ion connections for stratix and stratix gx devices. figure 4?20. differential termination z 0 z 0 stratix lvds receiver buffer with differential on-chip termination r d differential transmitter 4?30 altera corporation stratix device handbook, volume 2 june 2006 i/o pad placement guidelines differential termination for stratix devices is su pported for the left and right i/o banks. differential term ination for stratix gx devices is supported for the left, so urce-synchronous i/o bank. some of the clock input pins are in the top and bottom i/o banks, which do not support differential termination. clock pins clk[1,3,8,10] support differential on-chip termination. clock pins clk[ 0,2,9,11], clk[4-7], and clk[12-15] do not support differential on-chip termination. transceiver termination stratix gx devices feature built-in on-chip termination within the transceiver at both the transmit an d receive buffers. this termination improves signal integrity and provides support for the 1.5-v pcml i/o standard. i/o pad placement guidelines this section provides pad placement guidelines for the programmable i/o standards supported by stratix and stratix gx devices and includes essential information for designing systems using the devices' selectable i/o capabilities. these guidelines will reduce noise problems so that fpga devices can maintain an acceptable noise level on the line from the v ccio supply. since altera fpgas require that a separate v ccio power each bank, these noise issues do not have any effect when crossing bank boundaries and thes e guidelines do not apply. although pad placement rules need not be considered between i/o banks, some rules must be considered if you are using a vref signal in a pllout bank. note that the signals in the pllout banks share the v ref supply with neighboring i/o banks and, therefore, must adhere to the v ref rules discussed in ?vref pad placement guidelines? . differential pad placement guidelines to avoid cross coupling and maintain an acceptable noise level on the v ccio supply, there are restrictions on the placement of single-ended i/o pads in relation to differential pads. use the following guidelines for placing single-ended pads with resp ect to differential pads in stratix devices. these guidelines apply fo r lvds, hypertransport technology, lvpecl, and pcml i/o standards. the differential pad placement guidelines do not apply for differential hstl and differential sstl output clocks since each differen tial output clock is essentially implemented using two single-ended ou tput buffers. these rules do not apply to differential hstl input clocks either even though the dedicated input buffers are used. however, both differential hstl and differential sstl output standards must ad here to the single-ended ( vref ) pad placement restrictions discussed in ?vref pad placement guidelines? . altera corporation 4?31 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices for flip-chip packages, there are no restrictions for placement of single-ended input signals with resp ect to differential signals (see figure 4?21 ). for wire-bond packages, single ended input pads may only be placed four or more pa ds away from a differential pad. single-ended outputs and bidirectional pads may only be placed five or more pads away from a differential pad (see figure 4?21 ), regardless of package type. figure 4?21. legal pin placement note (1) note to figure 4?21 : (1) input pads on a flip-chip packages have no restrictions. vref pad placement guidelines restrictions on the placement of si ngle-ended voltage-referenced i/o pads with respect to vref pads help maintain an acceptable noise level on the v ccio supply and to prevent output switching noise from shifting the vref rail. the following guidelines ar e for placing single-ended pads in stratix devices. input pins each vref pad supports a maximum of 40 in put pads with up to 20 on each side of the vref pad. output pins when a voltage referenced input or bidirectional pad does not exist in a bank, there is no limit to the number of output pads that can be implemented in that bank. when a vo ltage referenced input exists, each vref pad supports 20 outputs for ther mally enhanced fineline bga ? and thermally enhanced bga cavity up packages or 15 outputs for non- thermally enhanced cavity up and non-thermally enhanced fineline bga packages. d i ffere n t i a l p in wi reb on d in p u t in p u t , o u tp u t , b i d i rect ion a l in p u t , o u tp u t , b i d i rect ion a l in p u t fli pc hi p in p u t 4?32 altera corporation stratix device handbook, volume 2 june 2006 i/o pad placement guidelines bidirectional pins bidirectional pads must satisfy input and output guidelines simultaneously. if the bidirectional pads are all controlled by the same oe and there are no other outputs or volt age referenced inpu ts in the bank, then there is no case where there is a voltage referenced input active at the same time as an output. therefore, th e output limitation does not apply. however, since the bidirectional pads are linked to the same oe, the bidirectional pads act as inputs at the same time. therefore, the input limitation of 40 input pads (20 on each side of the vref pad) applies. if any of the bidirectional pads are controlled by different output enables (oe) and there are no other outputs or voltage referenced inputs in the bank, then there may be a case where one group of bidirectional pads is acting as inputs while another group is acting as outputs. in such cases, apply the formulas shown in table 4?8 . consider a thermally enhanced fi neline bga package with eight bidirectional pads controlled by oe1, eight bidirectional pads controlled by oe2, and six bidirectio nal pads controlled by oe3. while this totals 22 bidirectional pads, it is safely allowable because there would be a maximum of 16 outputs per vref pad possible assuming the worst case where oe1 and oe2 are active and oe3 is inactive. this is particularly relevant in ddr sdram applications. when at least one additional volt age referenced input and no other outputs exist in the same vref bank, then the bidire ctional pad limitation must simultaneously adhere to the inpu t and output limitations. see the following equation. < total number of bidirectional pads > + < total number of input pads > 40 (20 on each side of the vref pad) table 4?8. input-only bidirecti onal pin limitation formulas package type formula thermally enhanced fineline bga and thermally enhanced bga cavity up < total number of bidirectional pads > ? < total number of pads from the smallest group of pads controlled by an oe > 20 (per vref pad) non-thermally enhanced cavity up and non-thermally enhanced fineline bga < total number of bidirectional pads > ? < total number of pads from the smallest group of pads controlled by an oe > 15 (per vref pad). altera corporation 4?33 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices the previous equation accounts for the input limitation s, but you must apply the appropriate equation from table 4?9 to determine the output limitations. when at least one additional output exists but no voltage referenced inputs exist, apply the appropriate formula from table 4?10 . when additional voltage referenced in puts and other outputs exist in the same vref bank, then the bidirectional pad limitation must again simultaneously adhere to the inpu t and output limitations. see the following equation. < total number of bidirectional pads > + < total number of input pads > 40 (20 on each side of the vref pad) table 4?9. bidirectional pad limitati on formulas (where vref inputs exist) package type formula thermally enhanced fineline bga and thermally enhanced bga cavity up < total number of bidirectional pads > 20 (per vref pad) non-thermally enhanced cavity up and non-thermally enhanced fineline bga < total number of bidirectional pads > 15 (per vref pad) table 4?10. bidirectional p ad limitation formulas (where vref outputs exist) package type formula thermally enhanced fineline bga and thermally enhanced bga cavity up < total number of bidirectional pads > + < total number of additional output pads > ? < total number of pads from the smallest group of pads controlled by an oe > 20 (per vref pad) non-thermally enhanced cavity up and non-thermally enhanced fineline bga < total number of bidirectional pads > + < total number of additional output pads > ? < total number of pads from the smallest group of pads controlled by an oe > 15 (per vref pad) 4?34 altera corporation stratix device handbook, volume 2 june 2006 i/o pad placement guidelines the previous equation accounts for the input limitation s, but you must apply the appropriate equation from table 4?9 to determine the output limitations. in addition to the pad placement guid elines, use the following guidelines when working with v ref standards: each bank can only have a single v ccio voltage level and a single v ref voltage level at a given time. pins of different i/o standards can share the bank if they have compatible v ccio values (see table 4?12 for more details). in all cases listed above, the quartus ii software generates an error message for illegally placed pads. output enable group logic option in quartus ii the quartus ii software can check a design to make sure that the pad placement does not violate the rules mentioned above. when the software checks the design, if the design contains more bidirectional pins than what is allowed, the quartus ii software returns a fitting error. when all the bidirectional pins are either input or output but not both (for example, in a ddr memory interface), you can use the output enable group logic option. turning on this option directs the quartus ii fitter to view the specified nodes as an output enable group. this way, the fitter does not violate the requirements for the maximum number of pins driving out of a v ref bank when a voltaged-referenced input pin or bidirectional pin is present. in a design that implements ddr me mory interface with dq, dqs and dm pins utilized, there are two ways to enable the above logic options. you can enable the logic options through th e assignment editor or by adding the following assignments to your project?s esf file: options_for_individual_nodes_only { dq : output_enable_group 1; dqs : output_enable_group 1; table 4?11. bidirectional pad limitation formulas (multi ple vref inputs & outputs) package type formula thermally enhanced fineline bga and thermally enhanced bga cavity up < total number of bidirectional pads > + < total number of additional output pads > 20 (per vref pad) non-thermally enhanced cavity up and non-thermally enhanced fineline bga < total number of bidirectional pads > + < total number of additional output pads > 15 (per vref pad) altera corporation 4?35 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices dm : output_enable_group 1; } as a result, the quartus ii fitter do es not count the bidirectional pin potential outputs, and the number of v ref bank outputs remains in the legal range. toggle rate logic option in quartus ii you should specify the pin?s output toggling rate in order to perform a stricter pad placement check in the quartus ii software. specify the frequency at which a pin toggles in the quartus ii assignment editor. this option is useful for adjusting the pin toggle rate in order to place them closer to differential pins. the option directs the quartus ii fitter toggle-rate checking while allowing you to place a single-ended pin closer to a differential pin. dc guidelines variables affecting the dc current dr aw include package type and desired termination methods. this section pr ovides information on each of these variables and also shows how to calculate the dc current for pin placement. 1 the quartus ii software automatically takes these variables into account during compilation. for any 10 consecutive output pads in an i/o bank, altera recommends a maximum current of 200 ma for ther mally enhanced fineline bga and thermally enhanced bga cavity up packages and 164 ma for non-thermally enhanced cavity up an d non-thermally enhanced fineline bga packages. the following equa tion shows the current density limitation equation for thermally e nhanced fineline bga and thermally enhanced bga cavity up packages: the following equation shows the curr ent density limitation equation for non-thermally enhanced cavity up and non-thermally enhanced fineline bga packages: pin + 9 pin i pin < 200 ma 4?36 altera corporation stratix device handbook, volume 2 june 2006 i/o pad placement guidelines table 4?12 shows the dc current specification per pin for each i/o standard. i/o standards not shown in the table do not exceed these current limitations. f for more information on altera device packaging, see the package information for stratix devices chapter in the stratix device handbook, volume 2 . table 4?12. i/o standard dc specification note (1) pin i/o standard i pin (ma) 3.3-v v ccio 2.5-v v ccio 1.5-v v ccio gtl 40 40 - gtl+ 34 34 - sstl-3 class i 8 - - sstl-3 class ii 16 - - ctt 8 - - sstl-2 class i - 8.1 - sstl-2 class ii - 16.4 - hstl class i - - 8 hstl class ii - - 16 note to table 4?12 : (1) the current rating on a v ref pin is less than 10 a. pin + 9 pin i pin < 164 ma altera corporation 4?37 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices figure 4?22. current draw limitation guidelines any 10 consecutive i/o pads cann ot exceed 200 ma in thermally enhanced fineline bga and ther mally enhanced bga cavity up packages or 164 ma in non-therma lly enhanced cavity up and non- thermally enhanced fineline bga packages. for example, consider a case where a group of 10 consecutive pads are configured as follows for a ther mally enhanced fineline bga and thermally enhanced bga cavity up package: number of sstl-3 class i output pads = 3 number of gtl+ output pads = 4 the rest of the surrounding i/o pa ds in the consecutive group of 10 are unused in this case, the total current draw for these 10 consecutive i/o pads would be: (# of sstl-3 class i pads 8 ma) + (# of gtl+ output pads 34 ma) = (3 8 ma) + (4 34 ma) = 160 ma in the above example, the total curr ent draw for all 10 consecutive i/o pads is less than 200 ma. gnd vcc i/o pin sequence of an i/o bank any 10 consecutive i/o pins, 4?38 altera corporation stratix device handbook, volume 2 june 2006 power source of various i/o standards power source of various i/o standards for stratix and stratix gx devices, the i/o standards are powered by different power sources. to determ ine which source powers the input buffers, see table 4?13 . all output buffers are powered by v ccio . quartus ii software support you specify which programmable i/o standards to use for stratix and stratix gx devices with the quartus i i software. this section describes quartus ii implementati on, placement, and as signment guidelines, including compiler settings device & pin options assign pins programmable drive strength settings i/o banks in the floorplan view auto placement & verification compiler settings you make compiler settings in the compiler settings dialog box (processing menu). click the chips & devices tab to specify the device family, specific device, package, pi n count, and speed grade to use for your design. table 4?13. the relationships between various i/o st andards and the power sources i/o standard power source 2.5v/3.3v lvttl v ccio pci/pci-x 1.0 v ccio agp v ccio 1.5v/1.8v v ccio gtl v ccint gtl+ v ccint sstl v ccint hstl v ccint ctt v ccint lv d s v ccint lvpecl v ccint pcml v ccint hypertransport v ccint altera corporation 4?39 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices device & pin options click device & pin options in the compiler settings dialog box to access the i/o pin setting s. for example, in the voltage tab you can select a default i/o standard for all pins for the targeted device. i/o pins that do not have a specific i/o standard assignment default this standard. click ok when you are done setting i/ o pin options to return to the compiler settings dialog box. assign pins click assign pins in the compiler settings dialog box to view the device?s pin settings and pin assignments (see figure 4?23 ). you can view the pin settings under available pins & existing assignments . the listing does not include v ref pins because they are dedicated pins. the information for ea ch pin includes: number name i/o bank i/o standard type (e.g., row or column i /o and differential or control) signalprobe source name enabled (that is, whether signalprobe routing is enabled or disabled status figure 4?23. assign pins 4?40 altera corporation stratix device handbook, volume 2 june 2006 quartus ii software support when you assign an i/o standard that requires a reference voltage to an i/o pin, the quartus ii softwa re automatically assigns v ref pins. see the quartus ii help for instructions on how to use an i/o standard for a pin. programmable drive strength settings to make programmable drive streng th settings, perform the following steps: 1. in the tools menu, choose assignment organizer . 2. choose the edit specific entity & node settings for: setting, then select the output or bidirectional pin to specify the current strength for. 3. in the assignment categories dialog box, select options for individual nodes only . 4. select click here to add a new assignment . 5. in the assignment dialog box, set the name field to current strength and set the setting field to the desired, allowable value. 6. click add . 7. click apply , then ok . i/o banks in the floorplan view you can view the arrangement of the device i/o banks in the floorplan view (view menu) as shown in figure 4?24 . you can assign multiple i/o standards to the i/o pins in any given i/o bank as long as the v ccio of the standards is the same. pins that be long to the same i/o bank must use the same v ccio signal. each device i/o pin belongs to a specific, numbered i/o bank. the quartus ii software color codes the i/o bank to which each i/o pin and v ccio pin belong. turn on the show i/o banks option to display the i/o bank color and the bank numbers for each pin. altera corporation 4?41 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices figure 4?24. floorplan view window auto placement & verification of selectable i/o standards the quartus ii software automatically verifies the placement for all i/o and v ref pins and performs the following actions. automatically places i/o pins of different v ref standards without pin assignments in separate i/o banks and enables the v ref pins of these i/o banks. verifies that voltage-referenced i/o pins requiring different v ref levels are not placed in the same bank. reports an error message if the current limit is exceeded for a stratix or stratix gx power bank, as determined by the equation documented in ?dc guidelines? on page 4?35 . reserves the unused high-speed differential i/o channels and regular user i/o pins in the high-s peed differential i/o banks when any of the high-speed differential i/o channels are being used. automatically assigns v ref pins and i/o pins such that the current requirements are met and i/o standards are placed properly. 4?42 altera corporation stratix device handbook, volume 2 june 2006 conclusion conclusion stratix and stratix gx devices provide the i/o capabilities to allow you to work with current and emerging i/o standards and requirements. today?s complex designs demand increased flexibility to work with the wide variety of available i/o stan dards and to simplify board design. with stratix and stratix gx device features, such as hot socketing and differential on-chip termination, you can reduce board design interface costs and increase your development flexibility. more information for more information, see the following sources: the stratix device family data sheet section in the stratix device handbook, volume 1 the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 the high-speed differential i/o interfaces in stratix devices chapter an 224: high-speed board layout guidelines references for more information, see the following references: stub series terminated logic for 2.5-v (sstl-2), jesd8-9b, electronic industries as sociation, december 2000. high-speed transceiver logic (hstl) ? a 1.5-v output buffer supply voltage based interface st andard for digital integrated circuits, eia/jesd8-6, electronic industries association, august 1995. 1.5-v +/- 0.1 v (normal range) and 0.9 v ? 1.6 v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuits, jesd8-11, electronic industries association, october 2000. 1.8-v +/- 0.15 v (normal range) and 1.2 v ? 1.95 v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuits, je sd8-7, electronic industries association, february 1997. center-tap-terminated (ctt) low-level, high-speed interface standard for digital integrated circuits, jesd8-9a, electronic industries association, november 1993. 2.5-v +/- 0.2v (normal range) and 1.8-v to 2.7v (wide range) power supply voltage and interface standard for non-terminated digital integrated circuits, je sd8-5, electronic industries association, october 1995. interface standard for nominal 3v/ 3.3-v supply digital integrated circuits, jesd8-b, electronic indu stries association, september 1999. gunning transceiver logic (gtl) lo w-level, high-speed interface standard for digital integrated circuits, jesd8-3, electronic industries association, november 1993. altera corporation 4?43 june 2006 stratix device handbook, volume 2 selectable i/o standards in stratix & stratix gx devices accelerated graphics port inte rface specification 2.0, intel corporation. stub series terminated logic for 1.8-v (sstl-18), preliminary jc42.3, electronic industries association. pci local bus specification, revision 2.2, pci special interest group, december 1998. pci-x local bus specification, revision 1.0a, pci special interest group. utopia level 4, af-phy-0144.00 1, atm technical committee. pos-phy level 4: spi-4, oif-spi4 -02.0, optical internetworking forum. pos-phy level 4: sfi-4, oif-sfi4 -01.0, optical internetworking forum. electrical characterist ics of low voltage differential signaling (lvds) interface circuits, ansi/t ia/eia-644, american national standards institute/telecommunications industry/electronic industries association, october 1995. 4?44 altera corporation stratix device handbook, volume 2 june 2006 references altera corporation 5?1 july 2005 5. high-speed differential i/o interfaces in stratix devices introduction to achieve high data transfer rates, stratix ? devices support true- lvds tm differential i/o interfac es which have dedicated serializer/deserializer (serdes) circuitry for each differential i/o pair. stratix serdes circuitry transmits and receives up to 840 megabits per second (mbps) per channel. the differential i/o interfaces in stratix devices support many high-speed i/o standards, such as lvds, lvpecl, pcml, and hypertransport tm technology. stratix device high- speed modules are designed to provide solutions for many leading protocols such as spi-4 phase 2, sf i-4, 10g ethernet xsbi, rapidio, hypertransport technology, and utopia-4. the serdes transmitter is designed to serialize 4-, 7-, 8-, or 10-bit wide words and transmit them across either a cable or printed circuit board (pcb). the serdes receiver takes the serialized data and reconstructs the bits into a 4-, 7-, 8-, or 10-bit-wide pa rallel word. the serdes contains the necessary high-frequency circuitry, multiplexer, demultiplexer, clock, and data manipulation circuitry. you can use double data rate i/o (ddrio) circuitry to transm it or receive differential data in by-one ( 1) or by-two ( 2) modes. 1 contact altera applications for more information on other b values that the stratix devices support and using 7-mode in the quartus ? ii software. stratix devices currently only support b = 1 and b = 7 in 7 mode. this chapter describes the high-speed differential i/o capabilities of stratix programmable logic devices (plds) and provides guidelines for their optimal use. you should use this document in conjunction with the stratix device family data sheet section of the stratix device handbook, volume 1 . consideration of the critical issues of controlled impedance of traces and connectors, differential routing, termination techniques, and dc balance gets the best performance from the device. therefore, an elementary knowledge of high-speed cl ock-forwarding techniques is also helpful. stratix i/o banks stratix devices contain eight i/o banks, as shown in figure 5?1 . the two i/o banks on each side contain circuitry to support high-speed lvds, lvpecl, pcml, hstl class i and i i, sstl-2 class i and ii, and hypertransport inputs and outputs. s52005-3.2 5?2 altera corporation stratix device handbook, volume 2 july 2005 stratix i/o banks figure 5?1. strati x i/o banks notes (1) , (2) , (3) notes to figure 5?1 : (1) figure 5?1 is a top view of the stratix silicon die, which corres ponds to a top-down view of non-flip-chip packages and a bottom-up view of flip-chip packages. (2) figure 5?1 is a graphic representation only. see the pin li st and the quartus ii software for exact locations. (3) banks 9 through 12 are enhanced pll external clock output banks. (4) if the high-speed differential i/o pins are not used for high-speed differential signaling, they can support all of the i/o standards except hs tl class i and ii, gtl, sstl-18 cl ass ii, pci, pci-x 1.0, and agp 1 /2 . (5) see ?differential pad placement guidelines? on page 4?30 . you can only place single-e nded output/bidirectional pads five or more pads away fr om a differential pad. use the show pads view in the quartus ii floorplan editor to locate these pads. the quartus ii software gives an error message for illegal output or bidirectional pin placement next to a high-speed differential i/o pin. stratix differential i/o standards stratix devices provide a multi-protocol interface that allows communication between a variety of i/o standards, including lvds, hypertransport technology, lvpecl , pcml, hstl clas s i and ii, and lv ds , lv p e c l, 3 . 3 -v pc ml, a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) lv ds , lv p e c l, 3 . 3 -v pc ml, a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) i/ o ba nk s 3 , 4, 9 & 10 s u pp o rt all s in g l e -en ded i/ o sta n dards i/ o ba nk s 7, 8 , 11 & 1 2 s u pp o rt all s in g l e -en ded i/ o sta n dards i/ o ba nk s 1, 2 , 5, a n d 6 s u pp o rt all s in g l e -en ded i/ o sta n dards ex cept d i ffere n t i a l h s tl o u tp u t c lo c k s , d i ffere n t i a l ss tl- 2 o u tp u t c lo c k s , h s tl c l ass ii, g tl, ss tl-1 8 c l ass ii, pc i, pc i-x 1.0, a n d a gp 1 / 2 dqs9t dqs8t dqs7t dqs6t dqs5t dqs4t dqs3t dqs2t dqs1t dqs0t pll5 vref1b3 vref2b3 vref3b3 vref4b3 vref5b3 vref1b4 vref2b4 vref3b4 vref4b4 vref5b4 vref5b8 vref4b8 vref3b8 vref2b8 vref1b8 vref5b7 vref4b7 vref3b7 vref2b7 vref1b7 pll6 dqs9b dqs8b dqs7b dqs6b dqs5b dqs4b dqs3b dqs2b dqs1b dqs0b 910 vref1b2 vref2b2 vref3b2 vref4b2 vref1b1 vref2b1 vref3b1 vref4b1 vref4b6 vref3b6 vref2b6 vref1b6 vref4b5 vref3b5 vref2b5 vref1b5 bank 5 bank 6 pll3 pll4 pll1 pll2 bank 1 bank 2 bank 3 bank 4 11 12 bank 8 bank 7 lv ds , lv p e c l, 3 . 3 -v pc ml, a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) lv ds , lv p e c l, 3 . 3 -v pc ml, a n d hy per t ra n sp o rt i/ o b lo c k a n d reg ul ar i/ o p in s (4) pll7 pll10 pll8 pll9 pll12 pll11 (5) (5) (5) (5) altera corporation 5?3 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices sstl-2 class i and ii. this feature ma kes the stratix device family ideal for applications that require multiple i/o standards, such as a protocol translator. f for more information on terminatio n for stratix i/o standards, see ?differential i/o termination? on page 5?46 . figure 5?2 compares the voltage levels between differential i/o standards supported in all the stratix devices. figure 5?2. differential i/o standards supported by stratix devices pcml 3.3 v 3.0 v 2.1 v 1.4 v 1.0 v 0.9 v 0.3 v 1.7 v 0.0 1.0 2.0 3.0 4.0 lvpecl lvds hyper- transport technology voltage (v) 5?4 altera corporation stratix device handbook, volume 2 july 2005 stratix i/o banks lvds the lvds i/o standard is a differen tial high-speed, low-voltage swing, low-power, general-purpose i/o interface standard requiring a 3.3-v v ccio . this standard is used in applications requiring high-bandwidth data transfer, backplane driver s, and clock distribution. the ansi/tia/eia-644 standard specifies lvds transmitters and receivers capable of operating at recommended maximum data signaling rates of 655 mbps. however, devices can operate at slower speeds if needed, and there is a theoretical maximum of 1. 923 gbps. stratix devices meet the ansi/tia/eia-644 standard. due to the low voltage swing of the lvds i/o standard, the electromagnetic interference (emi) ef fects are much smaller than cmos, transistor-to-transistor logic (ttl), and pecl. this low emi makes lvds ideal for applications with low emi requirements or noise immunity requirements. the lvds standard specifies a differential output voltage range of 0.25 v v od 0.45 v. the lvds standard does not require an input reference voltage, however, it does require a 100- termination resistor between the two signals at the input buffer. stratix devices include an optional differ ential termination resistor within the device. see section i, stratix device family data sheet of the stratix device handbook, volume 1 for the lvds parameters. hypertransport technology the hypertransport technology i/o standard is a differential high- speed, high-performance i/o interf ace standard requiring a 2.5-v vccio. this standard is used in a pplications such as high-performance networking, telecommunications, embedded systems, consumer electronics, and internet connecti vity devices. the hypertransport technology i/o standard is a point-to-point standard in which each hypertransport technology bus co nsists of two point-to-point unidirectional links. each link is 2 to 32 bits. see the stratix device family data sheet section of the stratix device handbook, volume 1 for the hypertransport parameters. lvpecl the lvpecl i/o standard is a differen tial interface standard requiring a 3.3-v v ccio. the standard is used in applications involving video graphics, telecommunications, da ta communications, and clock distribution. the high-speed, low-voltage swing lvpecl i/o standard uses a positive power supply and is similar to lvds, however, lvpecl has a larger differential output voltage swing than lvds. see the stratix device family data sheet section of the stratix device handbook, volume 1 for the lvpecl signaling characteristics. altera corporation 5?5 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices pcml the pcml i/o standard is a differ ential high-speed, low-power i/o interface standard used in applic ations such as networking and telecommunications. the standard requires a 3.3-v v ccio . the pcml i/o standard achieves better performanc e and consumes less power than the lvpecl i/o standard. the pcml standard is similar to lvpecl, but pcml has a reduced voltage swing, which allows for a faster switching time and lower power consumption.see the stratix device family data sheet section of the stratix device handbook, volume 1 for the pcml signaling characteristics. differential hstl (class i & ii) the differential hstl i/o standard is used for applications designed to operate in the 0.0- to 1.5-v hstl logi c switching range such as quad data rate (qdr) memory clock interfaces. the differential hstl specification is the same as the single ended hstl specification. the standard specifies an input voltage range of ? 0.3 v v i v ccio + 0.3 v. the differential hstl i/o standard is only available on the input and ou tput clocks. see the stratix device family data sheet section of the stratix device handbook, volume 1 for the hstl signaling characteristics differential sstl-2 (class i & ii) the differential sstl-2 i/o standard is a 2.5-v memory bus standard used for applications such as high-speed double data rate (ddr) sdram interfaces. this standard defines the input and output specifications for devices that operate in the sstl-2 lo gic switching range of 0.0 to 2.5 v. this standard improves operation in conditions where a bus must be isolated from large stubs. the sstl-2 standard specifies an input voltage range of ? 0.3 v v i v ccio + 0.3 v. stratix devices support both input and output levels. the differential sstl-2 i/o standard is only available on output clocks. see the stratix device family data sheet section of the stratix device handbook, volume 1 for the sstl-2 signaling characteristics. stratix differential i/o pin location the differential i/o pins are locate d on the i/o banks on the right and left side of the stratix device. table 5?1 shows the location of the stratix device high-speed differential i/o bu ffers. when the i /o pins in the i/o banks that support differential i/o st andards are not used for high-speed 5?6 altera corporation stratix device handbook, volume 2 july 2005 principles of serdes operation signaling, you can configure them as any of the other supported i/o standards. ddrio capabilities are detailed in ?serdes bypass ddr differential signaling? on page 5?42 . principles of serdes operation stratix devices support source-synchronous differential signaling up to 840 mbps. serial data is transmitte d and received along with a low- frequency clock. the pll can multipl y the incoming low-frequency clock by a factor of 1 to 10. the serdes factor j can be 4, 7, 8, or 10 and does not have to equal the clock multiplication value. 1 and 2 operation is also possible by bypassing the serdes; it is explained in ?serdes bypass ddr differential interface review? on page 5?42 . on the receiver side, the high-frequenc y clock generated by the pll shifts the serial data through a shift register (also called deserializer). the parallel data is clocked out to the logic array synchron ized with the low- frequency clock. on the transmitter si de, the parallel data from the logic array is first clocked into a parallel-in, serial-out shift register synchronized with the low-frequency clock and then tr ansmitted out by the output buffers. there are four dedicated fast plls in ep1s10 to ep1s25 devices, and eight in ep1s30 to ep1s80 devices. thes e plls are used for the serdes operations as well as general-purpose use. the differential channels and the high-speed pll layout in stratix devices are described in the ?differential i/o interface & fast plls? section on page 5?16 . table 5?1. i/o pin locations on each side of stratix devices device side (1) differential input diff erential output ddrio left vvv right vvv to p v bottom v note to ta b l e 5 ? 1 : (1) device sides are relative to pin a1 in the upper left corner of the device (top view of the package). altera corporation 5?7 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices stratix differential i/o receiver operation you can configure any of the stratix differential input channels as a receiver channel (see figure 5?3 ). the differential receiver deserializes the incoming high-speed data. the input shift register continuously clocks the incoming data on the nega tive transition of the high-frequency clock generated by the pll clock ( w ). the data in the serial shift register is shifted into a parallel register by the rxloaden signal generated by the fast pll counter circuitry on the third falling edge of the high-frequency cl ock. however, you can select which falling edge of the high frequency clock loads the data into the parallel register, using the data-realignment ci rcuit. for more information on the data-realignment circuit, see ?data realignment princi ples of operation? on page 5?25 . in normal mode, the enable signal rxloaden loads the parallel data into the next parallel register on the second rising edge of the low-frequency clock. you can also load data to the parallel register through the txloaden signal when using the data-realignment circuit. figure 5?3 shows the block diagram of a single serdes receiver channel. figure 5?4 shows the timing relationship between the data and clocks in stratix devices in 10 mode. w is the low-frequency multiplier and j is data parallelization division factor. 5?8 altera corporation stratix device handbook, volume 2 july 2005 principles of serdes operation figure 5?3. stratix high-speed in terface deserialized in 10 mode notes to figure 5?3 : (1) w = 1, 2, 4, 7, 8, or 10. j = 4, 7, 8, or 10. w does not have to equal j . when j = 1 or 2, the deserializer is bypassed. when j = 2, the device uses ddrio registers. (2) this figure does not show additional circuitry for clock or data manipulation. figure 5?4. receiver timing diagram pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 stratix logic array receiver circuit serial shift registers parallel registers parallel registers fast pll (2) rxin+ rxin ? rxclkin+ rxclkin ? w w / j (1) rxloaden txloaden rxloaden internal 1 clock internal 10 clock receiver data input n ? 1 n ? 0 9 8 7 6 5 4 3 2 1 0 rxloaden internal 1 clock internal 10 clock receiver data input n ? 1 n ? 0 9 8 7 6 5 4 3 2 1 0 altera corporation 5?9 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices stratix differential i/o transmitter operation you can configure any of the stratix differential output channels as a transmitter channel. the differential transmitter is used to serialize outbound parallel data. the logic array sends parallel data to the serdes tr ansmitter circuit when the txloaden signal is asserted. this signal is generated by the high-speed counter circuitry of th e logic array low-frequency clock?s rising edge. the data is then transferre d from the parallel register into the serial shift register by the txloaden signal on the third rising edge of the high-frequency clock. figure 5?5 shows the block diagram of a single serdes transmitter channel and figure 5?6 shows the timing relationship between the data and clocks in stratix devices in 10 mode. w is the low-frequency multiplier and j is the data parallelization division factor. figure 5?5. stratix high-speed interface serialized in 10 mode pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 stratix logic array transmitter circuit parallel register serial register fast pll txout+ txout ? w txloaden 5?10 altera corporation stratix device handbook, volume 2 july 2005 principles of serdes operation figure 5?6. transmitter timing diagram transmitter clock output different applications and protocols ca ll for various cl ocking schemes. some applications require you to center-align the rising or falling clock edge with the data. other applicatio ns require a divide version of the transmitted clock, or the clock and da ta to be at the same high-speed frequency. the stratix device transm itter clock output is versatile and easily programmed for all such applications. stratix devices transmit data usin g the source-synchronous scheme, where the clock is transmitted along with the serialized data to the receiving device. unlike apex tm 20ke and apex ii devices, stratix devices do not have a fixed transm itter clock output pin. the altera ? quartus ii software generates the transm itter clock output by using a fast clock to drive a transmitter dataout channel. therefore, you can place the transmitter clock pair close to th e data channels, reducing clock-to- data skew and increasing system margins. this approach is more flexible, as any channel can drive a clock, not just specially designated clock pins. divided-down transmitter clock output you can divide down the high-frequency clock by 2, 4, 8, or 10, depending on the system requirements. the vari ous options allow stratix devices to accommodate many different types of protocols. the divided-down clock is generated by an additional transmitting data channel. txloaden internal 1 clock internal 10 clock receiver data input n ? 1 n ? 0 9 8 7 6 5 4 3 2 1 0 altera corporation 5?11 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices table 5?2 shows the divided-down versio n of the high-frequency clock and the selected serialization factor j (described in pervious sections). the quartus ii software automatically generates the data input to the additional transmitter data channel. center-aligned transmitter clock output a negative-edge-triggered d flipflop (dff) register is located between the serial register of each data cha nnel and its output buffer, as show in figure 5?7 . the negative-edge-triggered dff register is used when center-aligned data is required. for ce nter alignment, the dff only shifts the output from the channel used as the transmitter clock out. the transmitter data channels bypass th e negative-edge dff. when you use the dff register, the data is transm itted at the negative edge of the multiplied clock. this delays the tran smitted clock output relative to the data channels by half the multiplie d clock cycle. this is used for hypertransport technology, but can also be used for any interface requiring center alignment. table 5?2. differential transmitt er output clock division j data input output clock divided by (1) 4 1010 2 4 0011 4 8 10101010 2 8 00110011 4 8 11000011 8 10 1010101010 2 10 1110000011 10 note to ta b l e 5 ? 2 : (1) this value is usually referred to as b . 5?12 altera corporation stratix device handbook, volume 2 july 2005 principles of serdes operation figure 5?7. stratix programm able transmitter clock sdr transmitter clock output you can route the high-frequency cloc k internally generated by the pll out as a transmitter clock output on any of the differential channels. the high-frequency clock output allo ws stratix devices to support applications that require a 1-to-1 re lationship between the clock and data. the path of the high-sp eed clock is shown in figure 5?8 . a programmable inverter allows you to drive the signal out on either the negative edge of the clock or 180o out of ph ase with the streaming data. pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 stratix logic array transmitter circuit parallel register serial register fast pll txout+ txout ? w txloaden altera corporation 5?13 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?8. high-speed 1-to-1 transmitter clock output note to figure 5?8 : (1) this figure does not show additional circuitry for clock or data manipulation. using serdes to implement ddr some designs require a 2-to-1 data- to-clock ratio. these systems are usually based on rapid i/o, spi- 4 phase 2 (pos_phy level 4), or hypertransport interfaces, and suppo rt various data rates. stratix devices meet this requirement for such applications by providing a variable clock division fa ctor. the serdes clock division factor is set to 2 for double data rate (ddr). an additional differential channel (as described in ?transmitter clock output? on page 5?10 ) is automatically configured to produce the transmitter clock output signal with half the frequency of the data. for example, when a system is requ ired to transmit 6.4 gbps with a 2-to-1 clock-to-data ratio, program the serdes with eight high-speed channels running at 800 mbps each. when you set the output clock division factor (2 for this example) , the quartus ii software automatically assigns a ninth channel as the transmitter clock output. you can edge- or center-align the transmitter clock by selecting the default pll phase or selecting the negative-edge transmitter clock output. on the receiver side, the clock signal is connected to the receiver pll's clock. the multiplication factor w is also calculated automatically. the data rate divides by the input clock frequency to calculate the w factor. the deserialization factor ( j ) may be 4, 7, 8, or 10. pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 stratix logic array transmitter circuit parallel register serial register fast pll (1) txout+ txout ? w txloaden inverter 5?14 altera corporation stratix device handbook, volume 2 july 2005 using serdes to implement sdr figure 5?9 shows a ddr clock-to-data timing relationship with the clock center-aligned with respect to data. figure 5?10 shows the connection between the receiver an d transmitter circuits. figure 5?9. ddr clock-to -data relationship figure 5?10. ddr receiver & tran smitter circuit connection using serdes to implement sdr stratix devices support systems based on single data rate (sdr) operations applications by allowing you to directly transmit out the multiplied clock (as described in ?sdr transmitter clock output? on page 5?12 ). these systems are usually based on utopia-4, sfi-4, or xsbi interfaces, and support various data rates. an additional differential channel is automatically conf igured to produce the transmitter clock output signal an d is transmitted al ong with the data. for example, when a system is requir ed to transmit 10 gbps with a 1-to- 1 clock-to-data ratio, program the serdes with sixteen high-speed channels running at 624 mbps each. the quartus ii software xx b0 a0 b1 a1 b2 a2 b3 a3 inclock ddr serial-to-parallel register parallel register rx_d[0] channel 0 8 parallel-to-serial register parallel register tx_d[0] channel 0 8 serial-to-parallel register parallel register rx_d[15] channel 15 8 parallel-to-serial register parallel register channel 15 txclk_out 8 parallel-to-serial register parallel register 8 lvds pll lvds pll txloaden rxloadena input clock w input clock w txclk_in 100 mhz 800 mbps channel 16 txclk_out 400 mhz stratix logic array stratix serdes ddr transmitter stratix serdes ddr receiver data rate = 800 mbps data rate = 800 mbps rxclk 400 mhz 2 altera corporation 5?15 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices automatically assigns a seventeenth channel as the transmitter clock output. you can edge- or center-align the transmitter clock output by selecting the default pll phase or selecting the 90 phase of the pll output. on the receiver side, the cloc k signal is connected to the receiver pll's clock input, and you can assign identical clock-to-data alignment. the multiplication factor w is calculated automatically. the data rate is dividing by the input cloc k frequency to calculate the w factor. the deserialization factor j may be 4, 7, 8, or 10. figure 5?11 shows an sdr clock-to-data ti ming relationship, with clock center aligned with respect to data. figure 5?12 shows the connection between the receiver an d transmitter circuits. figure 5?11. sdr clock-to-data relationship figure 5?12. sdr receiver & tr ansmitter circuit connection xx b0 b1 b2 b3 inclock sdr serial-to-parallel register parallel register rx_d[0] channel 0 8 parallel-to-serial register parallel register tx_d[0] channel 0 8 serial-to-parallel register parallel register rx_d[15] channel 15 8 parallel-to-serial register parallel register tx_d[15] channel 15 txclk_out channel 16 8 lvds pll lvds pll txloaden rxloaden input clock w input clock w txclk_in 624 mhz 624 mhz stratix logic array stratix serdes sdr transmitter stratix serdes sdr receiver data rate = 624 mbps data rate = 624 mbps rxclk 624 mhz 5?16 altera corporation stratix device handbook, volume 2 july 2005 differential i/o interface & fast plls differential i/o interface & fast plls stratix devices provide 16 dedicated global clocks, 8 dedicated fast regional i/o pins, and up to 16 regional clocks (fo ur per device quadrant) that are fed from the dedicated global clock pins or pll outputs. the 16 dedicated global clocks are driven eith er by global cloc k input pins that support all i/o standards or from enhanced and fast pll outputs. stratix devices use the fast plls to implement clock multiplication and division to support the serdes circ uitry. the input clock is either multiplied by the w feedback factor and/or divided by the j factor. the resulting clocks are distributed to serdes, local, or global clock lines. fast plls are placed in the center of the left and right sides for ep1s10 to ep1s25 devices. for ep1s30 to ep1s80 devi ces, fast plls are placed in the center of the left and right sides, as well as the device corners (see figure 5?13 ). these fast plls drive a dedicated clock network to the serdes in the rows above and below or top and bottom of the device as shown in figure 5?13 . altera corporation 5?17 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?13. stratix fast pll positi ons & clock naming convention note (1) notes to figure 5?13 : (1) dedicated clock input pins on the right and left sides do not support pci or pci-x 1.0. (2) plls 7, 8, 9, and 10 are not available on the ep1s30 device in the 780-pin fineline bga ? package. fpllclk0 fpllclk3 fpllclk2 clk[11..8] fpllclk1 clk[3..0] 7 1 2 8 10 4 3 9 11 5 12 6 clk[7..4] clk[15..12] plls 5?18 altera corporation stratix device handbook, volume 2 july 2005 differential i/o interface & fast plls clock input & fast pll output relationship table 5?3 summarizes the pll in terface to the input clocks and the enable signal ( ena ). table 5?4 summarizes the clock networks each fast pll can connect to across all stratix family devices. table 5?3. fast pll clock inputs (inc luding feedback clocks) & enables note (1) input pin all stratix devices ep1s30 to ep1s80 devices only pll 1 pll 2 pll 3 pll 4 pll 7 pll 8 pll 9 pll 10 clk0 (2) v v (3) clk1 v clk2 (2) v v (3) clk3 v clk4 clk5 clk6 clk7 clk8 v v (3) clk9 (2) v clk10 v v (3) clk11 (2) v clk12 clk13 clk14 clk15 ena vvvvvvvv fpll7clk v fpll8clk v fpll9clk v fpll10clk v notes to ta b l e 5 ? 3 : (1) plls 5, 6, 11, and 12 are not fast plls. (2) clock pins clk0 , clk2 , clk9 , clk11 , and pins fpll[7..10]clk do not support differential on-chip termination. (3) either a fpllclk pin or a clk pin can drive the corner fast plls (pll7 , pll8, pll9, and pll10) when used for general purpose. clk pins cannot drive these fast plls in high-speed differential i/o mode. altera corporation 5?19 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices table 5?4. fast pll relationship with st ratix clock networks (part 1 of 2) notes (1) , (2) output signal all stratix devices ep1s30 to ep1s80 devices only pll 1 pll 2 pll 3 pll 4 pll 7 pll 8 pll 9 pll 10 gclk0 v gclk1 v gclk2 v gclk3 v gclk4 v gclk9 v gclk10 v gclk11 v rclk1 vv v rclk2 vv v rclk3 vv v rclk4 vv v rclk9 vv v rclk10 vv v rclk11 vv v rclk12 vv v diffioclk1 v diffioclk2 v diffioclk3 v diffioclk4 v diffioclk5 v diffioclk6 v diffioclk7 v diffioclk8 v diffioclk9 v diffioclk10 v diffioclk11 v diffioclk12 v diffioclk13 v 5?20 altera corporation stratix device handbook, volume 2 july 2005 differential i/o interface & fast plls fast pll specifications you can drive the fast plls by an exte rnal pin or any one of the sectional clocks [21..0]. you can connect the cl ock input directly to local or global clock lines, as shown in figure 5?14 . you cannot use the sectional-clock inputs to the fast pll?s input multip lexer for the receiver pll. you can only use the sectional clock inputs in the transmitter only mode or as a general purpose pll. diffioclk14 v diffioclk15 v diffioclk16 v notes to ta b l e 5 ? 4 : (1) plls 5, 6, 11, and 12 are not fast plls. (2) the input clock for plls used to clock receiver the rx_inclock port on the altlvds_rx megafunction must be driven by a dedicated clock pin ( clk[3..0] and clk[8..11] ) or the corner pins that clock the corner plls ( fpll[10..7]clk ). table 5?4. fast pll relationship with st ratix clock networks (part 2 of 2) notes (1) , (2) output signal all stratix devices ep1s30 to ep1s80 devices only pll 1 pll 2 pll 3 pll 4 pll 7 pll 8 pll 9 pll 10 altera corporation 5?21 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?14. fast pll block diagram notes to figure 5?14 : (1) in high-speed differential i/o mode, the high-speed p ll clock feeds the serdes. stra tix devices only support one rate of data transfer per fast pll in high-speed differential i/o mode. (2) control signal for high-speed differential i/o serdes. you can multiply the input clock by a factor of 1 to 16. the multiplied clock is used for high-speed serialization or deserialization operations. fast pll specifications are shown in the stratix device family data sheet section of the stratix device handbook, volume 1 . the voltage controlled oscillators (vcos) are designed to op erate within the frequency range of 300 to 840 mhz, to provide data rates of up to 840 mbps. high-speed phase adjust there are eight phases of the multipl ied clock at the pll output, each delayed by 45 from the previous clock and synchron ized with the original clock. the thre e multiplexers (shown in figure 5?14 ) select one of the delayed, multiplied clocks. the pll output drives the three counters k , v , and l . you can program the three indi vidual post scale counters ( k , v , and l ) independently for division ratio or phase. the selected pll output is used for the serialization or deserialization process in serdes. charge pump vco l 8 clock input phase frequency detector v k m loop filter vco phase selection selectable at each pll output port post-scale counters global or regional clock regional clock regional clock diffioclk2 (1 ) diffioclk1 (1 ) txloaden (2) rxloaden (2) global or regional clock rxclkin 5?22 altera corporation stratix device handbook, volume 2 july 2005 differential i/o interface & fast plls counter circuitry the multiplied clocks by pass the counter taps k and v to directly feed the serdes serial registers. these two ta ps also feed to the quadrant local clock network and the dedicated rxloadena or txloadena pins, as shown in figure 5?15 . both k and v are utilized simultaneously during the data-realignment procedure. when the design does not use the data realignment, both txloaden and rxloaden pins use a single counter. figure 5?15. fast pll connection to logic array the stratix device fa st pll has another gclk connection for general- purpose applications. the third tap l feeds the quadrant local clock as well as the global clock network. you can use the l counter's multiplexer for applications requiring the devi ce to connect the incoming clock directly to the local or global clocks . you can program the multiplexer to connect the rxclkin signal directly to the loca l or global clock lines. figure 5?15 shows the connection betwee n the incoming clock, the l tap, and the local or global clock lines. the differential clock selection is made per differential bank. since the length of the clock tree limits the perf ormance, each fast pll should drive only one differential bank. l 8 v k vco phase selection selectable at each pll output port regional clock 1 clk2 to logic array or local clocks 1 clk1 to logic array or local clocks clk1 serdes circuitry clk2 serdes circuitry txloaden rxloaden clkin pll output clock distribution circuitry counter circuitry post-scale counters altera corporation 5?23 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices fast pll serdes channel support the quartus ii megawizard plug-i n manager only allows you to implement up to 20 receiver or 20 transmitter channels for each fast pll. these channels operate at up to 840 mbps. for more information on implementing more th an 20 channels, see ?fast plls? on page 5?52 . the receiver and transmitter channels are interleaved such that each i/o bank on the left and right side of the de vice has one receiver channel and one transmitter channel per row. figure 5?16 shows the fast pll and channel layout in ep1s10, ep1s 20, and ep1s25 devices. figure 5?17 shows the fast pll and channel layout in ep1s30 to ep1s80 devices. f for more the number of channels in each device, see tables 5?10 through 5?14 . figure 5?16. fast pll & channel layout in ep1s10, ep1s20 & ep1s25 devices note (1) notes to figure 5?16 : (1) wire-bond packages only support up to 624 mbps until characterization shows otherwise. (2) see tables 5?10 through 5?14 for the exact number of channels ea ch package and device density supports. (3) there is a multiplexer here to select the pll clock source. if a pll uses this multiplexer to clock channels outside of its bank quadrant (e.g., if pll 2 clocks pll 1?s channel region), those clocked channels support up to 840 mbps. transmitter receiver transmitter receiver clkin clkin transmitter receiver transmitter receiver clkin clkin fast pll 1 fast pll 2 (3) fast pll 4 fast pll 3 (3) up to 2 0 receiver and transmitter channels (2) up to 2 0 receiver and transmitter channels (2) up to 2 0 receiver and transmitter channels (2) up to 2 0 receiver and transmitter channels (2) 5?24 altera corporation stratix device handbook, volume 2 july 2005 differential i/o interface & fast plls figure 5?17. fast pll & channel layout in ep1s30 to ep1s80 devices note (1) notes to figure 5?17 : (1) wire-bond packages only support up to 624 -mbps until characterization shows otherwise. (2) see tables 5?10 through 5?14 for the exact number of channels ea ch package and device density supports. (3) there is a multiplexer here to select the pll clock source. if a pll uses this multiplexer to clock channels outside of its bank quadrant (e.g., if pll 2 clocks pll 1?s channel region), those clocked channels support up to 840 mbps. transmitter receiver transmitter receiver clkin fpll7clk transmitter receiver transmitter receiver clkin fpll10clk transmitter receiver transmitter receiver fpll9clk clkin fast pll 7 fast pll 1 up to 20 receiver and 20 transmitter channels in 20 rows (2) transmitter receiver transmitter receiver fpll8clk clkin fast pll 2 fast pll 8 up to 20 receiver and 20 transmitter channels in 20 rows (2) up to 20 receiver and 20 transmitter channels in 20 rows (2) up to 20 receiver and 20 transmitter channels in 20 rows (2) (3) (3) fast pll 10 fast pll 4 fast pll 3 fast pll 9 altera corporation 5?25 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices advanced clear & enable control there are several control signals for cl earing and enabling plls and their outputs. you can use these signals to control pll resynchronization and to gate pll output clocks for low-power applications. the pllenable pin is a dedicated pin that enables and disables stratix device enhanced and fast plls. when the pllenable pin is low, the clock output ports are driven by gnd and all the plls go out of lock. when the pllenable pin goes high again, the plls relock and resynchronize to the input clocks. the reset signals are reset/resynchro nization inputs for each enhanced pll. stratix devices can drive these input signals from an input pin or from les. when driven high, the pl l counters reset, clearing the pll output and placing the pll out of lock. when driven low again, the pll resynchronizes to its input as it relocks. receiver data realignment most systems using serial differential i/o data transmission require a certain data-realignment circuit. stratix devices contain embedded data- realignment circuitry. while normal i/o operation guarantees that data is captured, it does not guarantee the parallelization boundary, as this point is randomly determined based on the power-up of both communicating devices. the data-reali gnment circuitry corrects for bit misalignments by shifting, or delaying, data bits. data realignment principles of operation stratix devices use a realignment and clock distribution circuitry (described in ?counter circuitry? on page 5?22 ) for data realignment. set the internal rx_data_align node end high to assert the data- realignment circuitry. when this node is switched from a low to a high state, the realignment circuitry is acti vated and the data is delayed by one bit. to ensure the rising edge of the rx_data_align node end is latched into the pll, the rx_data_align node end should stay high for at least two low-frequency clock cycles. an external circuit or an internal custom-made state machine using les can generate the signal to pull the rx_data_align node end to a high state. when the data realignment circuitry is activated, it generates an internal pulse sync s1 or sync s2 that disables one of the two counters used for the serdes operation (described in ?counter circuitry? on page 5?22 ). one counter is disabled for one high-freq uency clock cycle, delaying the 5?26 altera corporation stratix device handbook, volume 2 july 2005 receiver data realignment rxloaden signal and dropping the first in coming bit of the serial input data stream located in the first seri al register of the serdes circuitry (shown in figure 5?3 on page 5?8 ). figure 5?18 shows the function-timing diag ram of a stratix serdes in normal 8 mode, and figure 5?19 shows the function -timing diagrams of a stratix serdes when data realignment is used. figure 5?18. serdes function timing di agram in normal operation 8 clock 1 clock d7 d0 d1 d2 d2 d2 d2 d3 d4 d5 d6 d7 d0 d1 d2 d7 d0 d1 d2 d3 d4 d5 d6 d3 d3 d3 d4 d4 d4 d5 d5 d5 d6 d6 d6 d7 d7 d7 d0 d0 d0 d1 pd7 serial data pd6 pd5 pd4 pd3 pd2 pd1 pd0 d1 d1 altera corporation 5?27 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?19. serdes function timing diagram with data-realignment operation generating the txloaden signal the txloaden signal controls the transfer of data between the serdes circuitry and the logic array when da ta realignment is used. to prevent the interruption of the txloaden signal during data realignment, both k and v counter are used. in normal operation the txloaden signal is generated by the k counter. however, during the data-realignment operation this signal is generated by either counter. when the k counter is used fo r realignment, the 8 clock 1 clock d7 d0 d1 d2 d2 d2 d2 d3 d4 d5 d6 d7 d0 d1 d2 d7 d0 d1 d2 d3 d4 d5 d6 d3 d3 d3 d4 d4 d4 d5 d5 d5 d6 d6 d6 d7 d7 d7 d0 d0 d0 d1 pd7 serial data pd6 pd5 pd4 pd3 pd2 pd1 pd0 d1 d1 5?28 altera corporation stratix device handbook, volume 2 july 2005 receiver data realignment txloaden signal is generated by the v counter, and when the v counter is used for realignment, the txloaden signal is generated by the k counter, as shown in figure 5?20 . figure 5?20. realignment circu it txloaden signal control note (1) note to figure 5?20 : (1) this figure does not show additional realignment circuitry. realignment implementation the realignment signal ( sync ) is used for data realignment and reframing. an external pin ( rx_data_align ) or an internal signal controls the rx_data_align node end. when the rx_data_align node end is asserted high for at le ast two low-frequency clock cycles, the rxloaden signal is delayed by one high-frequency clock period and the parallel bits shift by one bit. figure 5?21 shows the timing relationship between the high-frequency clock, the rxloaden signal, and the parallel data. 8 v k 1 clk2 to logic array 1 clk1 to logic array clk1 lvds circuitry clk2 lvds circuitry gclk/lclk txloaden rxloaden l pll output clock distribution circuitry counter circuitry sync s1 realignment clk sync s2 realignment clk sync data realignment circuit data realignment circuit altera corporation 5?29 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?21. realignment by rx_data_align node end a state machine can generate the realignment signal to control the alignment procedure. figure 5?22 shows the connection between the realignment signal and the rx_data_align node end. figure 5?22. sync signal path to realignment circuit to guarantee that the rx_data_align signal generated by a user state machine is latched correctly by the counters, the user circuit must meet certain requirements. the design must include an input synchronizing register to ensure that data is synchronized to the 1 clock. 10 clock 1 clock sync rxloaden datain receiver a receiver b 67890123456789012345678901234 6 5 7890123456789012345678901234 0123456789 0123456789 1234567890 1234567890 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 stratix logic array receiver circuit parallel register register array w/j 1 txloaden hold register sync realignment circuit sync out 10 pattern detection state machine 5?30 altera corporation stratix device handbook, volume 2 july 2005 source-synchronous timing budget after the pattern detection state ma chine, use another synchronizing register to capture the generated sync signal and synchronize it to the 1 clock. since the skew in the path from the output of this synchronizing register to the pll is undefined, the state machine must generate a pulse that is high for two 1 clock periods. since the sync generator circuitry only generates a single fast clock period pulse for each sync pulse, you cannot generate additional sync pulses until the comparator signal is reset low. to guarantee the pattern detection state machine does not incorrectly generate multiple sync pulses to shift a single bit, the state machine must hold the sync signal low for at least three 1 clock periods between pulses. source- synchronous timing budget this section discusses the timing budget, waveforms, and specifications for source-synchronous signaling in stratix devices. lvds, lvpecl, pcml, and hypertransport i/o standards enable high-speed data transmission. this high data-transmission rate results in better overall system performance. to take advantag e of fast system performance, you must understand how to analyze timing for these high-speed signals. timing analysis fo r the differential block is different from traditional synchronous ti ming analysis techniques. rather than focusing on clock-to-output and setup times, source- synchronous timi ng analysis is based on the skew between the data and the clock signals. high-speed differen tial data transmission requires you to use timing parameters provided by ic vendors and to consider board skew, cable skew, and clock jitter. this section defines the source- synchronous differential data orient ation timing parameters, and timing budget definitions for stratix device s, and explains how to use these timing parameters to determin e a design's maximum performance. differential data orientation there is a set relationship between an external clock and the incoming data. for operation at 840 mbps and w = 10, the exte rnal clock is multiplied by 10 and phase-aligned by the pll to coincide with the sampling window of each data bit. the third falling edge of high- frequency clock is used to strobe the incoming high-speed data. therefore, the first two bits belong to the previous cycle. figure 5?23 shows the data bit orientation of the 10 mode as defined in the quartus ii software. altera corporation 5?31 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?23. bit orientation in the quartus ii software differential i/o bit position data synchronization is necessary fo r successful data transmission at high frequencies. figure 5?24 shows the data bit orientation for a receiver channel operating in 8 mode. similar positioning exists for the most significant bits (msbs) and leas t significant bits (lsbs) after deserialization, as listed in table 5?5 . figure 5?24. bit order for one channel of differential data n-1 n-0 9 8 7 6 5 4 3 2 1 0 10 lvds bits msb lsb inclock/outclock data in high-frequency clock inclock/outclock data in/ data out d7 d6 d5 d4 d3 d2 d1 d0 current cycle previous cycle next cycle data in/ data out 1001 0110 current cycle previous cycle next cycle example: sending the data 10010110 msb lsb msb lsb 5?32 altera corporation stratix device handbook, volume 2 july 2005 source-synchronous timing budget table 5?5 shows the conventions for differential bit naming for 18 differential channels. however, the msb and lsb are increased with the number of channels used in a system. timing definition the specifications used to define high-speed timing are described in table 5?6 . table 5?5. lvds bit naming receiver data channel number internal 8-bit parallel data msb position lsb position 170 2158 32316 43124 53932 64740 75548 86356 97164 10 79 72 11 87 80 12 95 88 13 103 96 14 111 104 15 119 112 16 127 120 17 135 128 18 143 136 table 5?6. high-speed timing specifica tions & terminology (part 1 of 2) high-speed timing spec ification terminology t c high-speed receiver/transmitter input and output clock period. f hsclk high-speed receiver/transmitter input and output clock frequency. t rise low-to-high transmission time. altera corporation 5?33 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices t fall high-to-low transmission time. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ). f hsdr maximum lvds data transfer rate (f hsdr = 1/tui). channel-to-channel skew (tccs) the timing differenc e between the fastest and slowest output edges, including t co variation and clock skew. the clock is included in the tccs measurement. sampling window (sw) the period of time during which the data must be valid in order for you to capture it correctly. the setup a nd hold times determine the ideal strobe position within the sampling window. sw = t sw (max) ? t sw (min). input jitter (peak-to-peak) peak-to-p eak input jitter on high-speed plls. output jitter (peak-to-peak) peak-to-p eak output jitter on high-speed plls. t duty duty cycle on high-speed transmitter output clock. t lock lock time for high-speed transmitter and receiver plls. table 5?6. high-speed timing specifica tions & terminology (part 2 of 2) high-speed timing spec ification terminology altera corporation 5?34 july 2005 stratix device handbook, volume 2 source-synchronous timing budget tables 5?7 and 5?8 show the high-speed i/o timing for stratix devices table 5?7. high-speed i/o specifications for flip-chip packages (part 1 of 3) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max min typ max f hsclk (clock frequency) (lvds, lvpecl, hypertransport technology) f hsclk = f hsdr / w w = 4 to 30 10 210 10 210 10 156 10 115.5 mhz w = 2 (serdes bypass) 50 231 50 231 50 231 50 231 mhz w = 2 (serdes used) 150 420 150 420 150 312 150 231 mhz w = 1 (serdes bypass) 100 462 100 462 100 462 100 462 mhz w = 1 (serdes used) 300 717 300 717 300 624 300 462 mhz f hsdr device operation (lvds, lvpecl, hypertransport technology) j = 10 300 840 300 840 300 640 300 462 mbps j = 8 300 840 300 840 300 640 300 462 mbps j = 7 300 840 300 840 300 640 300 462 mbps j = 4 300 840 300 840 300 640 300 462 mbps j = 2 100 462 100 462 100 640 100 462 mbps j = 1 (lvds and lvpecl only) 100 462 100 462 100 640 100 462 mbps f hsclk (clock frequency) (pcml) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 100 10 100 10 77.75 10 77.75 mhz w = 2 (serdes bypass) 50 200 50 200 50 150 50 150 mhz w = 2 (serdes used) 150 200 150 200 150 155.5 150 155.5 mhz w = 1 (serdes bypass) 100 250 100 250 100 200 100 200 mhz w = 1 (serdes used) 300 400 300 400 300 311 300 311 mhz altera corporation 5?35 july 2005 stratix device handbook, volume 2 source-synchronous timing budget f hsdr device operation (pcml) j = 10 300 400 300 400 300 311 300 311 mbps j = 8 300 400 300 400 300 311 300 311 mbps j = 7 300 400 300 400 300 311 300 311 mbps j = 4 300 400 300 400 300 311 300 311 mbps j = 2 100 400 100 400 100 300 100 300 mbps j = 1 100 250 100 250 100 200 100 200 mbps tccs all 200 200 300 300 ps sw pcml ( j = 4, 7, 8, 10) 750 750 800 800 ps pcml ( j = 2) 900 900 1,200 1,200 ps pcml ( j = 1) 1,500 1,500 1,700 1,700 ps lvds and lvpecl ( j =1) 500 500 550 550 ps lv d s, lvp e c l , hypertransport technology ( j =2 through 10) 440 440 500 500 ps input jitter tolerance (peak-to-peak) all 250 250 250 250 ps output jitter (peak- to-peak) all 160 160 200 200 ps output t rise lvds 80 110 120 80 110 120 80 110 120 80 110 120 ps hypertransport technology 110 170 200 110 170 200 120 170 200 120 170 200 ps lvpecl 90 130 150 90 130 150 100 135 150 100 135 150 ps pcml 80 110 135 80 110 135 80 110 135 80 110 135 ps table 5?7. high-speed i/o specifications for flip-chip packages (part 2 of 3) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max min typ max 5?36 altera corporation stratix device handbook, volume 2 july 2005 source-synchronous timing budget output t fall lvds 80 110 120 80 110 120 80 110 120 80 110 120 ps hypertransport technology 110 170 200 110 170 200 110 170 200 110 170 200 ps lvpecl 90 130 160 90 130 160 100 135 160 100 135 160 ps pcml 105 140 175 105 140 175 110 145 175 110 145 175 ps t duty lv d s ( j = 2 through 10) 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % lv d s ( j =1) and lvpecl, pcml, hypertransport technology 45 50 55 45 50 55 45 50 55 45 50 55 % t lock all 100 100 100 100 s notes to ta b l e 5 ? 7 : (1) when j = 4, 7, 8, and 10, the serdes block is used. (2) when j = 2 or j = 1, the serdes is bypassed. table 5?8. high-speed i/o specifications for wire-bond packages (part 1 of 3) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max f hsclk (clock frequency) (lvds,lvpecl, hypertransport technology) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 156 10 115.5 10 115.5 mhz w = 2 (serdes bypass) 50 231 50 231 50 231 mhz w = 2 (serdes used) 150 312 150 231 150 231 mhz w = 1 (serdes bypass) 100 311 100 270 100 270 mhz w = 1 (serdes used) 300 624 300 462 300 462 mhz table 5?7. high-speed i/o specifications for flip-chip packages (part 3 of 3) notes (1) , (2) symbol conditions -5 speed grade -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max min typ max altera corporation 5?37 july 2005 stratix device handbook, volume 2 source-synchronous timing budget f hsdr device operation, (lvds,lvpecl, hypertransport technology) j = 10 300 624 300 462 300 462 mbps j = 8 300 624 300 462 300 462 mbps j = 7 300 624 300 462 300 462 mbps j = 4 300 624 300 462 300 462 mbps j = 2 100 462 100 462 100 462 mbps j = 1 (lvds and lvpecl only) 100 311 100 270 100 270 mbps f hsclk (clock frequency) (pcml) f hsclk = f hsdr / w w = 4 to 30 (serdes used) 10 77.75 mhz w = 2 (serdes bypass) 50 150 50 77.5 50 77.5 mhz w = 2 (serdes used) 150 155.5 mhz w = 1 (serdes bypass) 100 200 100 155 100 155 mhz w = 1 (serdes used) 300 311 mhz device operation, f hsdr (pcml) j = 10 300 311 mbps j = 8 300 311 mbps j = 7 300 311 mbps j = 4 300 311 mbps j = 2 100 300 100 155 100 155 mbps j = 1 100 200 100 155 100 155 mbps tccs all 400 400 400 ps sw pcml (j = 4, 7, 8, 10) only 800 800 800 ps pcml (j = 2) only 1,200 1,200 1,200 ps pcml (j = 1) only 1,700 1,700 1,700 ps lvds and lvpecl (j = 1) only 550 550 550 ps lvds, lvpecl, hypertransport technology (j = 2 through 10) only 500 500 500 ps table 5?8. high-speed i/o specifications for wire-bond packages (part 2 of 3) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max altera corporation 5?38 july 2005 stratix device handbook, volume 2 source-synchronous timing budget input jitter tolerance (peak-to- peak) all 250 250 250 ps output jitter (peak-to-peak) all 200 200 200 ps output t rise lvds 80 110 120 80 110 120 80 110 120 ps hypertransport technology 120 170 200 120 170 200 120 170 200 ps lvpecl 100 135 150 100 135 150 100 135 150 ps pcml 80 110 135 80 110 135 80 110 135 ps output t fall lvds 80 110 120 80 110 120 80 110 120 ps hypertransport 110 170 200 110 170 200 110 170 200 ps lvpecl 100 135 160 100 135 160 100 135 160 ps pcml 110 145 175 110 145 175 110 145 175 ps t duty lvds (j =2..10) only 47.5 50 52.5 47.5 50 52.5 47.5 50 52.5 % lvds (j =1) and lvpecl, pcml, hypertransport technology 45 50 55 45 50 55 45 50 55 % t lock all 100 100 100 s table 5?8. high-speed i/o specifications for wire-bond packages (part 3 of 3) symbol conditions -6 speed grade -7 speed grade -8 speed grade unit min typ max min typ max min typ max altera corporation 5?39 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices input timing waveform figure 5?25 illustrates the essential operations and the timing relationship between the clock cycle and the incoming serial data. for a functional descriptio n of the serdes, see ?principles of serdes operation? on page 5?6 . figure 5?25. input timing waveform note (1) note to figure 5?25 : (1) the timing specifications are referenced at a 100-mv differential voltage. input clock (differential signal) input data previous cycle current cycle next cycle bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 m sb lsb t sw0 (min) t sw1 (min) t sw0 (max) t sw2 (min) t sw1 (max) t sw3 (min) t sw2 (max) t sw4 (min) t sw3 (max) t sw5 (min) t sw4 (max) t sw6 (min) t sw5 (max) t sw6 (max) t sw7 (min) t sw7 (max) 5?40 altera corporation stratix device handbook, volume 2 july 2005 source-synchronous timing budget output timing the output timing waveform in figure 5?26 illustrates the relationship between the output clock and the serial output data stream. figure 5?26. output timing waveform note (1) note to figure 5?26 : (1) the timing specifications are referenced at a 250-mv differential voltage. receiver skew margin change in system environment, su ch as temperature, media (cable, connector, or pcb) loading effect, a receiver's inherent setup and hold, and internal skew, reduces the sampling window for the receiver. the timing margin between receiver?s clock input and the data input sampling window is known as rskm. figure 5?27 illustrates the relationship between the parameter an d the receiver?s sampling window. output clock (differential signal) output data previous cycle current cycle next cycle bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 m sb lsb tppos0 (min) tppos1 (min) tppos0 (max) tppos2 (min) tppos1 (max) tppos3 (min) tppos2 (max) tppos4 (min) tppos3 (max) tppos5 (min) tppos4 (max) tppos6 (min) tppos5 (max) tppos6 (max) tppos7 (min) tppos7 (max) altera corporation 5?41 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?27. differential high-speed timing diagram & timing budget rskm tui time unit interval (tui) rskm tccs tppos (min) bit n internal clock falling edge t sw (min) bit n t sw (max) bit n tppos (max) bit n rskm tccs t swbegin t swend sampling window tccs 2 receiver input data transmitter output data internal clock synchronization external clock receiver input clock internal clock external input clock timing budget timing diagram clock placement sampling window (sw) rskm tccs tppos (min) bit n + 1 tppos (max) bit n + 1 5?42 altera corporation stratix device handbook, volume 2 july 2005 serdes bypass ddr differential signaling switching characteristics timing specifications for stratix devices are listed in tables 5?7 and 5?8 . you can also find stratix devi ce timing information in the stratix device family data sheet section of the stratix device handbook, volume 1 . timing analysis differential timing analysis is base d on skew between data and the clock signals. for static timi ng analysis, the timing characteristics of the differential i/o standards are guaran teed by design and depend on the frequency at which they are operated. use the values in the stratix device family data sheet section of the stratix device handbook, volume 1 to calculate system ti ming margins for various i/o protocols. for detailed descriptions and implementations of these protocols, see the altera web site at www.altera.com . serdes bypass ddr differential signaling each stratix device high-speed differential i/o channel can transmit or receive data in by-two ( 2) mode at up to 624 mbps using plls. these pins do not require dedicated serdes circuitry and they implement serialization and deserialization with minimal logic. serdes bypass ddr differe ntial interface review stratix devices use dedicated ddr circuitry to implement 2 differential signaling. although sdr ci rcuitry samples data only at the positive edge of the clock, ddr captures data on both the rising and falling edges for twice the transfer rate of sdr. stratix device shift registers, internal global plls, and i/o cells can perform serial-to-parallel conversions on incoming data and parallel-to-seria l conversion on outgoing data. serdes clock domains the serdes bypass differential signaling can use any of the many clock domains available in stratix devices. these clock domains fall into four categories: global, regi onal, fast regional, an d internally generated. general-purpose plls generate the gl obal clock domains. the fast plls can generate additional gl obal clocks domains. each pll features two taps that directly drive two unique global clock networks. a dedicated clock pin drives each general-purpose pll. these clock lines are utilized when designing for speeds up to 420 mbps. tables 5?3 and 5?4 on page 5?19 , respectively, show the available clocks in stratix devices. altera corporation 5?43 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices serdes bypass ddr differential signaling receiver operation the serdes bypass differential signaling receiver uses the stratix device ddr input circuitry to receive high-s peed serial data. the ddr input circuitry consists of a pair of shift re gisters used to capture the high-speed serial data, and a latch. one register captures the data on the positive edge of the clock (generated by pll) and the other register captures the data on the negative edge of the clock. because the data captured on the negative edge is delayed by one-half of the clock cycle, it is latche d before it interfac es with the system logic. figure 5?28 shows the ddr timing relati onship between the incoming serial data and the clock. in this example, the inclock signal is running at half the speed of the incoming data. however, other combinations are also possible. figure 5?29 shows the ddr input and the other modules used in a flexible-lvds receiver design to interface with the system logic. figure 5?28. 2 timing relation between incoming serial data & clock clock datain neg_reg_out dataout_l dataout_h b0 a0 b1 a1 b2 a2 b3 a3 xx b0 b1 b2 xx b0 b1 b2 xx a0 a1 a2 b3 5?44 altera corporation stratix device handbook, volume 2 july 2005 serdes bypass ddr differential signaling figure 5?29. 2 data rate receiver channel with deserialization factor of 8 serdes bypass ddr differen tial signaling transmitter operation the 2 differential signaling transmi tter uses the stratix device ddr output circuitry to transmit high-s peed serial data. the ddr output circuitry consists of a pair of shift registers and a multiplexer. the shift registers capture the parallel data on the clock?s rising ed ge (generated by the pll), and a multiplexer transmits the data in sync with the clock. figure 5?30 shows the ddr timing relation between the parallel data and the clock. in th is example, the inclock signal is running at half the speed of the data. however, other combinations are possible. figure 5?31 shows the ddr output and the other modules used in a 2 transmitter design to interface with the system logic. pll dff dff shift register shift register stratix logic array inclock datain latch register 4 1 clock ddr ioe d0, d2, d4, d6 d1, d3, d5, d7 altera corporation 5?45 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?30. 2 timing relation between parallel data & clock figure 5?31. 2 data rate transmitter channel wi th serialization factor of 8 high-speed interface pin locations stratix high-speed interface pins are lo cated at the edge of the package to limit the possible mismatch between a pair of high-speed signals. stratix devices have eight programmable i/o banks. figure 5?32 shows the i/o pins and their location relative to the package. outclock dataout datain_l datain_h xx xx xx a0 b0 a1 b1 a2 b2 a3 b0 b1 b2 b3 a0 a1 a2 a3 pll stratix logic array shift register shift register dff dff ddr ioe inclock dataout d0, d2, d4, d6 d1, d3, d5, d7 4 1 1 5?46 altera corporation stratix device handbook, volume 2 july 2005 differential i/o termination figure 5?32. differential i/o pin locations differential i/o termination stratix devices implement differenti al on-chip termination to reduce reflections and maintain signal integrity. on-chip termination also minimizes the number of external resistors required. this simplifies board design and places the resistors closer to the package, eliminating small stubs that can still lead to reflections. r d differential termination stratix devices support differential on-chip termination for the lvds i/o standard. external termination is re quired on output pins for pcml transmitters. hypertransport, lvpe cl, and lvds receivers require 100 ohm termination at the input pins. figure 5?33 shows the device with differential termination for the lvds i/o standard. f for more information on differential on-chip termination technology, see the selectable i/o standards in stratix & stratix gx devices chapter. u t r p n m l k j h g f e d c b a v w y aa 21 20 19 1 8 17 16 15 14 13 9 10 11 12 8 6 75 4 3 2 1 differential i/o pins (lvds , lvpecl , pc m l , hypertransport ) differential i/o pins (lvds , lvpecl , pc m l , hypertransport) regular i/o pins regular i/o pins altera corporation 5?47 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?33. lvds differentia l on-chip termination hypertransport & lvpecl differential termination hypertransport and lvpecl i/o standards are terminated by an external 100- resistor on the input pin. figure 5?34 shows the device with differential termination for the hypertransport or lvpecl i/o standard. figure 5?34. hypertransport & lvpecl differential termination pcml differential termination the pcml i/o technology is an alternative to the lvds i/o technology, and use an external voltage source (v tt ), a pair of 100- resistors on the input side and a pair of 50- resistors on the output side. figure 5?35 shows the device with differential termination for pcml i/o standard. r d lvds transmitter lvds receiver with on-chi p 100 - termination z 0 = 50 r d differential transmitter differential receiver z 0 = 50 z 0 = 50 5?48 altera corporation stratix device handbook, volume 2 july 2005 differential i/o termination figure 5?35. pcml differ ential termination differential hstl termination the hstl class i and ii i/o standards require a 0.75-v v ref and a 0.75- v v tt . figures 5?36 and 5?37 show the device with differential termination for hstl class i and ii i/o standard. figure 5?36. differential hstl class i termination differential transmitter differential receiver z 0 = 50 50 50 50 50 z 0 = 50 v tt differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.75 v v tt = 0.75 v altera corporation 5?49 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?37. differential hstl class ii termination differential sstl-2 termination the sstl-2 class i and ii i /o standards require a 1.25-v v ref and a 1.25-v v tt . figures 5?37 and 5?38 show the device with differential termination for sstl-2 class i and ii i/o standard. figure 5?38. differential sstl-2 class i termination differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 0.75 v v tt = 0.75 v 50 50 v tt = 0.75 v v tt = 0.75 v differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 1.25 v v tt = 1.25 v 25 25 5?50 altera corporation stratix device handbook, volume 2 july 2005 board design consideration figure 5?39. differential sstl- 2 class ii termination board design consideration this section is a brief explanation of how to get the optimal performance from the stratix high-sp eed i/o block and ensure first-time success in implementing a functional design with optimal signal quality. for more information on detailed board layout recommendation and i/o pin terminations see an 224: high-speed boar d layout guidelines . you must consider the critical issues of controlled impedance of traces and connectors, differential routing, and termination techniques to get the best performance from the ic. for more information, use this chapter and the stratix device family data sheet section of the stratix device handbook, volume 1 . the stratix high-speed module genera tes signals that travel over the media at frequencies as high as 840 mbps. board designers should use the following general guidelines: baseboard designs on controlled differential impedance. calculate and compare all parameters such as trace width, trac e thickness, and the distance between two differential traces. place external reference resistors as close to receiver input pins as possible. use surface mount components. avoid 90 or 45 corners. use high-performance connectors such as hs-3 connectors for backplane designs. high-performan ce connectors are provided by teradyne corp (www.teradyne.com ) or tyco international ltd. ( www.tyco.com ). design backplane and card traces so that trace impedance matches the connector?s and/or th e termination?s impedance. keep equal number of vias for both signal traces. differential transmitter differential receiver z 0 = 50 50 50 z 0 = 50 v tt = 1.25 v v tt = 1.25 v 50 50 v tt = 1.25 v v tt = 1.25 v 25 25 altera corporation 5?51 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices create equal trace lengths to avoi d skew between signals. unequal trace lengths also result in misplaced crossing points and system margins as the tccs value increases. limit vias because they cause discontinuities. use the common bypass capacitor va lues such as 0.001 f, 0.01 f, and 0.1 f to decouple the fast pll power and ground planes. keep switching ttl signals away fr om differential signals to avoid possible noise coupling. do not route ttl clock signals to areas under or above the differential signals. software support this section provides information on using the quartus ii software to create stratix designs with lvds tran smitters or receivers. you can use the altlvds megafunction in the quartu s ii software to implement the serdes circuitry. you must bypass the serdes circuitry in 1 and 2 mode designs and use the altddio megafunction to implement the deserialization instead. you can use either the logic array or the m512 ram blocks closest to the differential pins for deserialization in serdes bypass mode. differential pins in stratix stratix device differential pins are loca ted in i/o banks 1, 2, 5, and 6 (see figure 5?1 on page 5?2 ). each bank has differential transmitter and differential receiver pin pairs. you can use each differential transmitter pin pair as either a differential data pin pair or a differential clock pin pair because stratix devices do not have dedicated lvds tx_outclock pin pairs. the differential receiver pin pairs can only function as differential data pin pairs. you can use these differ ential pins as regular user i/o pins when not used as differential pins. when using differen tial signaling in an i/o bank, you cannot place non-differential output or bidirectional pads within five i/o pads of either side of the di fferential pins to avoid a decrease in performance on the lvds signals. you only need to make assignments to the positive pin of the pin-pair. the quartus ii software automatical ly reserves and makes the same assignment to the negative pin. if yo u do not assign any differential i/o standard to the differential pins, the quartus ii software sets them as lvds differential pins during fitti ng, if the design uses the serdes circuitry. additionally, if you bypass the serdes circuitry, you can still use the differential pins by assignin g a differential i/o standard to the pins in the quartus ii software. howe ver, when you bypass the serdes circuitry in the 1 and 2 mode, you must assign the correct differential i/o standard to the associated pins in the assignment organizer. for more information on how to use the assignment organizer, see the quartus ii on-line help. 5?52 altera corporation stratix device handbook, volume 2 july 2005 software support stratix devices can drive the pll_lock signal to both output pins and internal logic. as a result, you do not need a dedicated lock pin for your plls. in addition, there is only one pll_enable pin that enables all the plls on the device, including the fa st plls. you must use either the lvttl or lvcmos i/o standard with this pin. table 5?9 displays the lvds pins in stratix devices. fast plls each fast pll features a multiplexed in put path from a global or regional clock net. a clock pin or an output from another pll in the device can drive the input path. the input clock fo r plls used to clock receiver the rx_inclock port on the altlvds_rx megafunction must be driven by a dedicated clock pin (clk [3..0,8..11]) or the corner pins that clock the corner plls (fpll[10..7]clk). ep1s 10, ep1s20, and ep1s25 devices have a total of four fast plls located in the center of both sides of the device (see figure 5?16 on page 5?23 ). ep1s30 and larger devices have two additional fast plls per side at the top and bottom corners of the device. as shown in figure 5?17 on page 5?24 , the corner fast pll shares an i/o bank with the closest center fast pl l (e.g., plls 1 and 7 share an i/o bank). the maximum input clock fr equency for enhanced plls is 684 mhz and 717 mhz for fast plls. f for more information on stratix plls, see the general-purpose plls in stratix & stratix gx devices chapter. table 5?9. lvds pin names pin names functions diffio_tx#p transmitter positive data or output clock pin diffio_tx#n transmitter negative data or output clock pin diffio_rx#p receiver positive data pin diffio_rx#n receiver negative data pin fpllclk#p positive input clock pin to the corner fast plls (1) , (2) fpllclk#n negative input clock pin to the corner fast plls (1) , (2) clk#p positive input clock pin (2) clk#n negative input clock pin (2) notes to ta b l e 5 ? 9 : (1) the fpllclk pin-pair is only available in ep1s30, ep1s40, ep1s60, ep1s80 devices. (2) either a fpllclk pin or a clk pin can drive the corner fast plls (pll7, pll8, pll9, and pll10) when used for general purpose. clk pins cannot drive these fast plls in high-speed differential i/o mode. altera corporation 5?53 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices one fast pll can drive the 20 tran smitter channels and 20 receiver channels closest to it with data rates of up to 840 mbps. wire-bond packages support a data rate of 624 mb ps. the corner fast plls in ep1s80 devices support data rates of up to 840 mbps. see tables 5?10 through 5?14 for the number of high-speed diff erential channels in a particular stratix device density and package. since the fast pll drives the 20 clos est differential channels, there are coverage overlaps in the ep1s30 and larger devices that have two fast plls per i/o bank. in these devices, either the center fast pll or the corner fast pll can drive the differential channels in the middle of the i/o bank. fast plls can drive more than 20 transmitter and 20 receiver channels (see tables 5?10 through 5?14 and figures 5?16 , and 5?17 for the number of channels each pll can drive). in addition, the center fast plls can drive either one i/o bank or both i/ o banks on the same side (left or right) of the device, while the corn er fast plls can only drive the differential channels in its i/o bank. neither fast pll can drive the differential channels in the opposite side of the device. the center fast plls can only driv e two i/o at 840 mbps. for example, ep1s20 device fast pll 1 can drive all 33 differential channels on its side (17 channels from i/o bank 2 and 16 channels from i/o bank 1) running at 840 mbps in 4 mode. when a center fast pll drives the opposite bank on the same side of the device, the other center fast pll cannot drive any differential channels on the device. see tables 5?10 through 5?14 for the maximum number of channels that one fast pll can drive. the number of channels is also listed in the quartus ii software. the quartus ii software gives an error message if you try to compile a design exceedin g the maximum number of channels. f additional high-speed diffio pin information for stratix devices is available in volume 3 of the stratix device handbook . 5?54 altera corporation stratix device handbook, volume 2 july 2005 software support table 5?10 shows the number of channels and fast plls in ep1s10, ep1s20, and ep1s25 devices. tables 5?11 through 5?14 show this information for ep1s30, ep1s40 , ep1s60, and ep1s80 devices. table 5?10. ep1s10, ep1s20 & ep1s25 device differential channels (part 1 of 2) note (1) device package transmitter/ receiver total channels maximum speed (mbps) center fast plls pll 1 pll 2 pll 3 pll 4 ep1s10 484-pin fineline bga transmitter (2) 20 840 5 5 5 5 840 (3) 10 10 10 10 receiver 20 840 5 5 5 5 840 (3) 10 10 10 10 672-pin fineline bga 672-pin bga transmitter (2) 36 624 (4) 9999 624 (3) 18 18 18 18 receiver 36 624 (4) 9999 624 (3) 18 18 18 18 780-pin fineline bga transmitter (2) 44 840 11 11 11 11 840 (3) 22 22 22 22 receiver 44 840 11 11 11 11 840 (3) 22 22 22 22 ep1s20 484-pin fineline bga transmitter (2) 24 840 6 6 6 6 840 (3) 12 12 12 12 receiver 20 840 5 5 5 5 840 (3) 10 10 10 10 672-pin fineline bga 672-pin bga transmitter (2) 48 624 (4) 12 12 12 12 624 (3) 24 24 24 24 receiver 50 624 (4) 13 12 12 13 624 (3) 25 25 25 25 780-pin fineline bga transmitter (2) 66 840 17 16 16 17 840 (3) 33 33 33 33 receiver 66 840 17 16 16 17 840 (3) 33 33 33 33 altera corporation 5?55 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices ep1s25 672-pin fineline bga 672-pin bga transmitter (2) 56 624 (4) 14 14 14 14 624 (3) 28 28 28 28 receiver 58 624 (4) 14 15 15 14 624 (3) 29 29 29 29 780-pin fineline bga transmitter (2) 70 840 18 17 17 18 840 (3) 35 35 35 35 receiver 66 840 17 16 16 17 840 (3) 33 33 33 33 1,020-pin fineline bga transmitter (2) 78 840 19 20 20 19 840 (3) 39 39 39 39 receiver 78 840 19 20 20 19 840 (3) 39 39 39 39 notes to table 5?10 : (1) the first row for each transmitter or receiver reports the number of channels driven directly by the pll. the second row below it shows the maximum channels a pll can drive if cross bank channels are us ed from the adjacent center pll. for example, in the 484-pin fineline bga ep1s10 device, pll 1 can drive a maximum of five channels at 840 mbps or a maximum of 10 channels at 840 mbps. th e quartus ii software may also merge receiver and transmitter plls when a receiver is dri ving a transmitter. in this case, on e fast pll can drive both the maximum numbers of receiver and transmitter channels. (2) the number of channe ls listed includes the tr ansmitter clock output ( tx_outclock ) channel. if the design requires a ddr clock, it can use an extra data channel. (3) these channels span across two i/o banks per side of the device. when a center pll clocks channels in the opposite bank on the same side of the device it is called cross-bank pll su pport. both center plls can clock cross- bank channels simultaneously if, for example, pll_1 is clocking all rx channels and pll_2 is clocking all tx channels. you cannot have two adjacent plls simultaneously clocking cross-bank rx channels or two adjacent plls simultaneously clocking tx channels. cross-bank allows for all receiver channels on one side of the device to be clocked on one clock while all trans mitter channels on the device are clocke d on the other center pll. crossbank plls are supported at full-speed , 840 mbps. for wire-bond devices, the full-speed is 624 mbps. (4) these values show the channels available for each pll without crossing another bank. table 5?10. ep1s10, ep1s20 & ep1s25 device differential channels (part 2 of 2) note (1) device package transmitter/ receiver total channels maximum speed (mbps) center fast plls pll 1 pll 2 pll 3 pll 4 5?56 altera corporation stratix device handbook, volume 2 july 2005 software support table 5?11. ep1s30 differential channels note (1) package transmitter /receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 780-pin fineline bga transmitter (4) 70 840 18 17 17 18 (6) (6) (6) (6) 840 (5) 35 35 35 35 (6) (6) (6) (6) receiver 66 840 17 16 16 17 (6) (6) (6) (6) 840 (5) 33 33 33 33 (6) (6) (6) (6) 956-pin fineline bga transmitter (4) 80 (7) 840 19 20 20 19 20 20 20 20 840 (5) 39 39 39 39 20 20 20 20 receiver 80 (7) 840 20 20 20 20 19 20 20 19 840 (5) 40 40 40 40 19 20 20 19 1,020-pin fineline bga transmitter (4) 80 (2) (7) 840 19 (1) 20 20 19 (1) 20 20 20 20 840 (5) , (8) 39 (1) 39 (1) 39 (1) 39 (1) 20 20 20 20 receiver 80 (2) (7) 840 20 20 20 20 19 (1) 20 20 19 (1) 840 (5) , (8) 40 40 40 40 19 (1) 20 20 19 (1) table 5?12. ep1s40 differential channels (part 1 of 2) note (1) package transmitter /receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 780-pin fineline bga transmitter (4) 68 840 18 16 16 18 (6) (6) (6) (6) 840 (5) 34 34 34 34 (6) (6) (6) (6) receiver 66 840 17 16 16 17 (6) (6) (6) (6) 840 (5) 33 33 33 33 (6) (6) (6) (6) 956-pin fineline bga transmitter (4) 80 840 18 17 17 18 20 20 20 20 840 (5) 35 35 35 35 20 20 20 20 receiver 80 840 20 20 20 20 18 17 17 18 840 (5) 40 40 40 40 18 17 17 18 altera corporation 5?57 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices 1,020-pin fineline bga transmitter (4) 80 (10) (7) 840 18 (2) 17 (3) 17 (3) 18 (2) 20 20 20 20 840 (5) , (8) 35 (5) 35 (5) 35 (5) 35 (5) 20 20 20 20 receiver 80 (10) (7) 840 20 20 20 20 18 (2) 17 (3) 17 (3) 18 (2) 840 (5) , (8) 40 40 40 40 18 (2) 17 (3) 17 (3) 18 (2) 1,508-pin fineline bga transmitter (4) 80 (10) (7) 840 18 (2) 17 (3) 17 (3) 18 (2) 20 20 20 20 840 (5) , (8) 35 (5) 35 (5) 35 (5) 35 (5) 20 20 20 20 receiver 80 (10) (7) 840 20 20 20 20 18 (2) 17 (3) 17 (3) 18 (2) 840 (5) , (8) 40 40 40 40 18 (2) 17 (3) 17 (3) 18 (2) table 5?13. ep1s60 differential channels (part 1 of 2) note (1) package transmitter /receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 956-pin fineline bga transmitter (4) 80 840 12 10 10 12 20 20 20 20 840 (5) , (8) 22 22 22 22 20 20 20 20 receiver 80 840 20 20 20 20 12 10 10 12 840 (5) , (8) 40 40 40 40 12 10 10 12 1,020-pin fineline bga transmitter (4) 80 (12) (7) 840 12 (2) 10 (4) 10 (4) 12 (2) 20 20 20 20 840 (5) , (8) 22 (6) 22 (6) 22 (6) 22 (6) 20 20 20 20 receiver 80 (10) (7) 840 20 20 20 20 12 (8) 10 (10) 10 (10) 12 (8) 840 (5) , (8) 40 40 40 40 12 (8) 10 (10) 10 (10) 12 (8) table 5?12. ep1s40 differential channels (part 2 of 2) note (1) package transmitter /receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 5?58 altera corporation stratix device handbook, volume 2 july 2005 software support 1,508-pin fineline bga transmitter (4) 80 (36) (7) 840 12 (8) 10 (10) 10 (10) 12 (8) 20 20 20 20 840 (5) , (8) 22 (18) 22 (18) 22 (18) 22 (18) 20 20 20 20 receiver 80 (36) (7) 840 20 20 20 20 12 (8) 10 (10) 10 (10) 12 (8) 840 (5) , (8) 40 40 40 40 12 (8) 10 (10) 10 (10) 12 (8) table 5?14. ep1s80 differential channels (part 1 of 2) note (1) package transmitter /receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 956-pin fineline bga transmitter (4) 80 (40) (7) 840 10 10 10 10 20 20 20 20 840 (5) , (8) 20 20 20 20 20 20 20 20 receiver 80 840 20 20 20 20 10 10 10 10 840 (5) , (8) 40 40 40 40 10 10 10 10 1,020-pin fineline bga transmitter (4) 80 (12) (7) 840 10 (2) 10 (4) 10 (4) 10 (2) 20 20 20 20 840 (5) , (8) 20 (6) 20 (6) 20 (6) 20 (6) 20 20 20 20 receiver 80 (10) (7) 840 20 20 20 20 10 (2) 10 (3) 10 (3) 10 (2) 840 (5) , (8) 40 40 40 40 10 (2) 10 (3) 10 (3) 10 (2) table 5?13. ep1s60 differential channels (part 2 of 2) note (1) package transmitter /receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) , (3) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 altera corporation 5?59 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices the quartus ii software may also me rge transmitter and receiver plls when a receiver block is driving a transmitter block if the use common plls for rx and tx option is set for both modules. the quartus ii software does not merge the plls in multiple transm itter-only or multiple receiver-only modules fed by the same clock. 1,508-pin fineline bga transmitter (4) 80 (72) (7) 840 10 (10) 10 (10) 10 (10) 10 (10) 20 (8) 20 (8) 20 (8) 20 (8) 840 (5) , (8) 20 (20) 20 (20) 20 (20) 20 (20) 20 (8) 20 (8) 20 (8) 20 (8) receiver 80 (56) (7) 840 20 20 20 20 10 (14) 10 (14) 10 (14) 10 (14) 840 (5) , (8) 40 40 40 40 10 (14) 10 (14) 10 (14) 10 (14) notes to ta b l e s 5 ? 11 through 5?14 . (1) the first row for each transmitter or receiver reports the number of channels driven directly by the pll. the second row below it shows the maximum channels a pll can drive if cross bank channels are used from the adjacent center pll. for example, in the 780-pin fineline bga ep1s 30 device, pll 1 can drive a maximum of 18 transmitter channels at 840 mbps or a maximum of 35 transmitter channels at 840 mbps. the quartus ii software may also merge transmitter and receiver plls wh en a receiver is driving a transmitter. in this case, on e fast pll can drive both the maximum numbers of rece iver and trans mitter channels. (2) some of the channels accessible by the center fast pll an d the channels accessible by th e corner fast pll overlap. therefore, the total number of channels is not the addition of the n umber of channels accessible by plls 1, 2, 3, and 4 with the number of channels accessible by plls 7, 8, 9, and 10. for more information on which channels overlap, see the fast pll to high-speed i/o connections section in the relevant device pin table available on the web ( www.altera.com ). (3) the corner fast plls in this device support a data rate of 840 mbps for channels labeled ?high? speed in the device pin tables. (4) the numbers of channels listed in clude the transmitter clock output ( tx_outclock ) channel. you can use an extra data channel if you need a ddr clock. (5) these channels span across two i/o banks per side of the device. when a center pll clocks channels in the opposite bank on the same side of the device it is called cro ss-bank pll support. both center plls can clock cross-bank channels simultaneously if, for example, pll_1 is clocking all receiver channels and pll_2 is clocking all transmitter channels. you cannot have two adjacent plls simultaneously clocking cross-bank receiver channels or two adjacent plls simultaneously clocki ng transmitter channels. cross-bank allo ws for all receiver channels on one side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the other center pll. crossbank plls are supported at full-speed, 840 mbps. for wire-bond devices, the full-speed is 624 mbps. (6) plls 7, 8, 9, and 10 are not available in this device. (7) the number in parentheses is the n umber of slow-speed channels, guaranteed to operate at up to 462 mbps. these channels are independent of the high-speed differential channels. for the location of these channels, see the fast pll to high-speed i/o connections section in the relevant device pin table available on the web ( www.altera.com ). (8) see device pin-outs channels marked ?high? speed are 840 mbps and ?low? speed channels are 462 mbps. table 5?14. ep1s80 differential channels (part 2 of 2) note (1) package transmitter /receiver total channels maximum speed (mbps) center fast plls corner fast plls (2) pll1 pll2 pll3 pll4 pll7 pll8 pll9 pll10 5?60 altera corporation stratix device handbook, volume 2 july 2005 software support when you span two i/o banks using cross-bank support, you can route only two load enable signals total between the plls. when you enable rx_data_align , you use both rxloadena and txloadena of a pll. that leaves no loadena for the second pll. the only way you can use the rx_data_align is if one of the following is true: the rx pll is only clocking rx channels (no resources for tx) if all channels can fit in one i/o bank lvds receiver block you only need to enter the input cloc k frequency, deserialization factor, and the input data rate to implemen t an lvds receiver block. the quartus ii software then automat ically sets the clock boost ( w ) factor for the receiver. in addition, you can also indicate the clock and data alignment for the receiver or add the pll_enable , rx_data_align , and rx_locked output ports. table 5?15 explains the function of the available ports in the lvds receiver block. table 5?15. lvds receiver ports port name direction function input port source/output port destination rx_in[number_of_channels - 1..0] input input data channel pin rx_inclock input reference input clock pin or output from a pll rx_pll_enable input enables fast pll pin (1) , (2) , (3) rx_data_align input control for the data realignment circuitry pin or logic array (1) , (3) , (4) rx_locked output fast pll locked pin pin or logic array (1) , (3) rx_out[deserialization_factor * number_of_channels -1..0] output de-serialized data logic array rx_outclock output internal reference clock logic array notes to table 5?15 : (1) this is an optional port. (2) only one rx_pll_enable pin is necessary to enable all the plls in the device. (3) this is a non-differential pin. (4) see ?realignment implementation? on page 5?28 for more information. for guaranteed performance and data alignment, you must synchronize rx_data_align with rx_outclock . altera corporation 5?61 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices use the altlvds megawizard plug-in manager to create an lvds receiver block. the following sections explain the parameters available in the plug-in manager when creating an lvds receiver block. page 3 of the altlvds_rx megawizard plug-in manager on page 3 of the altlvds megawizard plug-in manager, you can choose to create either an lvds tr ansmitter or receiver. depending on what you select, the megawizard plug-in manager provides you with different options. figure 5?40 shows page 3 of the altlvds megawizard plug-in manager with options fo r creating an lvds receiver. figure 5?40. page 3 of the altlvds _rx megawizard plug-in manager number of channels the what is the number of channels? parameter specifies the number of receiver channels required and the width of rx_out port. to set a fast pll to drive over 20 channels, type th e required number in the quartus ii window instead of choos ing a number from the drop-down menu, which only has selections of up to 20 channels. 5?62 altera corporation stratix device handbook, volume 2 july 2005 software support deserialization factor use the what is the deserialization factor? parameter to specify the number of bits per channe l. the stratix lvds rece iver supports 4, 7, 8, and 10 for deserialization factor ( j ) values. based on the factor specified, the quartus ii software determines th e multiplication and/or division factor for the lvds pll to deserialize the data. see table 5?5 for the differential bit naming convention. the parallel data for the n th channel spans from the msb ( rx_out bit [( j n ) ? 1]) to the lsb ( rx_out bit [ j ( n ? 1)]), where j is the deserialization factor. the total width of the receiver rx_out port is equal to the number of channels multiplied by your deserialization factor. input data rate the what is the inclock boost(w)? parameter sets the data rate coming into the receiver and is usually the deserialization factor ( j ) multiplied by the inclock frequency. this parameter?s value must be larger than the input clock frequency and has a maxi mum input data rate of 840 mbps for stratix devices. you do not have to provide a value for the inclock boost ( w ) when designing with stratix devices because the quartus ii software can calculate it automatically from this parameter and the clock frequency or clock period. the rx_outclock frequency is ( w / j ) input frequency. the parallel data coming out of the receiver has the same frequency as the rx_outclock port. the clock-to-data alig nment of the parallel data output from the receiver depends on the what is the alignment of data with respect to rx_inclock? parameter. data alignment with clock the what is the alignment of data with respect to rx_inclock? parameter adjusts the clock-to-data skew. for most applications, the data is source synchronous to the clock. however, there are applications where you must center-align the data with respect to the clock. you can use the what is the alignment of data w ith respect to rx_inclock? parameter to align the input data with respect to the rx_inclock port. the megawizard plug-in automatically calculates the phase for the fast pll outputs from the what is the alignment of data with respect to rx_inclock? parameter. this parameter?s default value is edge_aligned , and other values available from the pull-down menu are edge_aligned , center_aligned , 45_degrees , 135_degrees , 180_degrees , 225_degrees , 270_degrees , and 315_degrees . center_aligned is the same as 90 degrees aligned and is useful for applications like hypertransport technology. altera corporation 5?63 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices clock frequency or clock period the fields in the specify the input clock rate by box specify the input frequency or the period of the input clock going into the fast pll. when using the same input clock to fe ed a transmitter and receiver simultaneously, the quartus ii software can use one fast pll for both the transmitter and receiver. page 4 of the altlvds_rx megawizard plug-in manager this section describes the parameters found on page 4 of the altlvds_rx megawizard plug-in manager (see figure 5?41 ). figure 5?41. page 4 of the altlvds_rx megawizard plug-in manager 5?64 altera corporation stratix device handbook, volume 2 july 2005 software support data realignment check the use the ?rx_data_align? input port box within the input ports box to add the rx_data_align output port and enable the data realignment circuitry in stratix serdes. see ?receiver data realignment? on page 5?25 for more information. if necessary, you can create a state machine to send a pulse to the rx_data_align port to realign the data coming in the lvds receiver. you need to assert the port for at least two clock cycles to enable the data realignment circuitry. go to the altera web site at www.altera.com for a sample design written in verilog hdl. for guaranteed performance when us ing data realignment, check the add extra registers for rx_data_align input box when using the rx_data_align port. the quartus ii software places one synchronization register in the le closest to the rx_data_align port. register outputs check the register outputs box to register the receiver?s output data. the register acts as the modu le?s register boundary. if the module fed by the receiver does not have a register boun dary for the data, turn this option on. the number of registers used is proportional to the deserialization factor ( j ). the quartus ii software places the synchronization registers in the les closest to th e serdes circuitry. use common pll for both transmitter & receiver check the use common plls for rx and tx box to place both the lvds transmitter and the lvds receiver in the same stratix device i/o bank. the quartus ii software allows the tr ansmitter and receiver to share the same fast pll when they use the sa me input clock. although you must separate the transmitter and receiv er modules in your design, the quartus ii software merges the fast plls when appropriate and give you the following message: receiver fast pll < lvds_rx pll name > and transmitter fast pll < lvds_tx pll name > are merged together the quartus ii software provides th e following message when it cannot merge the fast plls for the lvds transmitter and receiver pair in the design: can't merge transmitter-only fast pll < lvds_tx pll name > and receiver- only fast pll < lvds_rx pll name > rx_outclock resource you can use either the global or regional clock for the rx_outclock signal. if you select auto in the quartus ii software, the tool uses any available lines. altera corporation 5?65 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices lvds transmitter module the quartus ii software calculates the inclock boost ( w ) factor for the lvds transmitter based on input data rate, input clock frequency, and the deserialization factor. in addi tion to setting the data and clock alignment, you can also set the outclock divide factor ( b ) for the transmitter output clock and add the pll_enable , tx_locked , and tx_coreclock ports. table 5?16 explains the functi on of the available ports in the lvds transmitter block. you can also use the altlvds megawizard plug-in manager to create an lvds transmitter block. the followin g sections explain the parameters available in the plug-in manager when creating an lvds transmitter block. page 3 of the altlvds_tx megawizard plug-in manager this section describes the parameters found on page 3 of the altlvds_tx megawizard plug-in manager (see figure 5?42 ). table 5?16. lvds transmitter ports port name direction function input port source/output port destination tx_in[deserialization_factor * number_of_channels - 1..0] input input data logic array tx_inclock input reference input clock pin or output clock from a pll tx_pll_enable input fast pll enable pin (1) , (2) , (3) tx_out[number_of_channels - 1..0] output serialized lvds data signal pin tx_outclock output external reference clock pin tx_coreclock output internal reference clock pin, logic array, or input clock to a fast pll (1) tx_locked output fast pll locked pin pin or logic array (1) , (2) , (3) notes to table 5?16 : (1) this is an optional port. (2) only one tx_pll_enable pin is necessary to enable all the plls in the device. (3) this is a non-differential pin. 5?66 altera corporation stratix device handbook, volume 2 july 2005 software support figure 5?42. page 3 of the transmitter altlvds megawizard plug-in manager number of channels the what is the number of channels? parameter specifies the number of transmitter channels requir ed and the width of the tx_in port. you can have more than 20 channels in a transm itter or receiver module by typing in the required number instead of choosing a number from the drop down menu, which only has sele ctions of up to 20 channels. deserialization factor the what is the deserialization factor? parameter specifies the number of bits per channel. the transmitter block supports deserialization factors of 4, 7, 8, and 10. based on the fact or specified, the quartus ii software determines the multiplication and/or division factor for the lvds pll in order to serialize the data. table 5?5 on page 5?32 lists the differential bi t naming convention. the parallel data for the n th channel spans from the msb ( rx_out bit [( j n ) ? 1]) to the lsb ( rx_out bit [ j ( n ? 1)]), where j is the altera corporation 5?67 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices deserialization factor. the total width of the tx_in port of the transmitter is equal to the number of channels multiplied by the deserialization factor. outclock divide factor the what is the output data rate? parameter specifies the ratio of the tx_outclock frequency compared to the data rate. the default value for this parameter is the value of the deserialization factor parameter. the tx_outclock frequency is equal to [ w / b ] x input clock frequency. there is also an optional tx_coreclock port which has the same frequency as the [ w / j ] input frequency. the outclock divide factor is useful for applications that do not require the data rate to be the same as the clock frequency. for example, hypertransport technology uses a half-clock data rate scheme where the clock frequency is half the data rate. table 5?17 shows the supported outclock divide factor for a given deserialization factor. output data rate the what is the output data rate parameter specifies the data rate out of the fast pll and determines the inpu t clock boost/multiplication factor needed for the transmitter. this parameter must be larger than the input clock frequency and has a maximum rate of 840 mbps for stratix devices. the input clock boost factor ( w ) is the output data rate divided by the input clock frequency. the stratix se rdes circuitry supports input clock boost factors of 4, 7, 8, or 10. the maximum output data rate is 840 mbps, while the clock has a maximum output of 500 mhz. data alignment with clock use the what is the alignment of data with respect to tx_inclock? parameter and the what is the alignm ent of tx_outclock? to align the input and output data, respectively, wi th the clock. for most applications, the data is edge-aligned with the cloc k. however, there are applications where the data must be center-aligned with respect to the clock. with table 5?17. deserialization factor (j ) vs. outclock divide factor (b) deserialization factor ( j ) outclock divide factor ( b ) 4 1, 2, 4 71, 7 (1) 8 1, 2, 4, 8 10 1, 2, 10 note to table 5?17 : (1) the clock does not have a 50% duty cycle when b=7 in x7 mode. 5?68 altera corporation stratix device handbook, volume 2 july 2005 software support stratix devices, you can align th e input data with respect to the tx_inclock port and align the output data with respect to the tx_outclock port. the megawizard pl ug-in manager uses the alignment of input and output data to automatically calculate the phase for the fast pll outputs. both of these parameters default to edge_aligned , and other values are center_aligned , 45_degrees , 135_degrees , 180_degrees , 225_degrees , 270_degrees , and 315_degrees . center_aligned is the same as 180 degrees aligned and is required for the hypertra nsport technology i/o standard. clock frequency & clock period the fields in the specify the input clock rate by box specify either the frequency or the period of the inpu t clock going into the fast pll. however, you cannot specify both. if your design uses the same input clock to feed a transmitter and a re ceiver module simultaneously, the quartus ii software can merge the fast plls for both the transmitter and receiver when the use common plls for tx & rx option is turned on. page 4 of the altlvds_tx megawizard plug-in manager this section describes the parameters found on page 4 of the altlvds_tx megawizard plug-in manager (see figure 5?43 ). altera corporation 5?69 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?43. page 4 of the transmitter altlvds megawiz ard plug-in manager registered inputs check the register inputs box if the input data to the transmitter is not registered just before it feeds th e transmitter module. you can choose either tx_clkin or tx_coreclk to clock the transmitter data ( tx_in[] ) signal. this se rves as the register boundary. the number of registers used is proportional to the deserialization factor ( j ). the quartus ii software places the synchr onization registers with the les in the same row and closest to the serdes circuitry. use common pll for transmitter & receiver check the use common plls for rx and tx box to place both the lvds transmitter and receiver in the same i/o bank in stratix devices. the quartus ii software also allows the transmitter and receiver to share the pll when the same input clock is used for both. although you must 5?70 altera corporation stratix device handbook, volume 2 july 2005 software support separate the transmitter and receiv er in your design, the quartus ii software merges the fast plls when appropriate and gives you the following message: receiver fast pll altera corporation 5?71 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?44. lvds x2 mode schema tic using ddr i/o circuitry the transmitter output clock requires extra ddr output circuitry that has the input high and input low connected to v cc and gnd respectively. the output clock frequency is the same as the input frequency of the ddr output circuitry. other modes for other modes, you can still to use the ddr circuitry for better frequency performance. you can use either the les or the m512 ram block for the deserialization. m512 ram block as serializer/deserializer interface in addition to using the ddr circui try and the m512 ram block, you need two extra counters per memory block to provide the address for the memory: a fast counter powering up at 0 and a slow counter powering up at 2. the m512 ram block is config ured as a simple dual-port memory block, where the read enable and the write enable signal s are always tied high. figures 5?45 and 5?46 show the block diagram for the serdes bypass receiver and serdes bypass transmitter, respectively. datain[0] inclock dataout_h[0] dataout_l[0] ddio in datain_h[0] datain_l[0] outclock dataout[0] ddio out datain_h[0] datain_l[0] outclock dataout[0] ddio out inclock /1 clock1 /2 clock0 rx_pll custom logic v cc gnd rxp rxn rx_inclk txp txn tx_outclk 5?72 altera corporation stratix device handbook, volume 2 july 2005 software support figure 5?45. serdes bypass lvds receiver us ing m512 ram block as the deserializer figure 5?46. serdes bypass lvds transmitter using m512 ram block as deserializer datain[0] inclock dataout_h[0] dataout_l[0] ddio in datain[1..0] waddr[7..0] wclock rclock raddr[5..0] dataout[7..0] simple dual port rx_sesb 512 bits inclock 1 clock1 2 clock0 rx_pll rxp rxn rx_inclk w-upcounter clock q[4..0] r-upcounter clock q[2..0] waddr[7..5] core data core clock raddr[5..3] datain[7..0] waddr[5..0] wclock rclock raddr[7..0] dataout[7..0] simple dual port 2 8 tx_sesb 512 bits inclock 1 clock1 2 clock0 rx_pll datain_h[0] datain_l[0] outclock datain_h[0] datain_l[0] outclock dataout_h[0] dataout_l[0] ddio out /1 clock1 /2 clock0 rx_pll core_clk core_data w-upcounter clock q[2..0] r-upcounter clock q[5..0] waddr[7..5] raddr[5..3] v cc gnd txp txn tx_outclk altera corporation 5?73 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices for the transmitter, the read counte r is the fast counter and the write counter is the slow counter. for the receiver, the write counter is the fast counter and the read counter is the slow counter. tables 5?18 and 5?19 provide the address counter configur ations for the transmitter and the receiver, respectively. in different m512 memory configurat ions, the counter width is smaller than the address width, so you must ground some of the most significant address bits. table 5?20 summarizes the address width, the counter width, and the number of bits to be grounded. table 5?18. address counters for se rdes bypass lvds receiver m512 mode deserialization factor write up-counter (fast counter) read up-counter (slow counter) invalid initial cycles width starts at widt h starts at write read 24 4 4032126 28 8 5032246 416 8 5032246 216 16 6032486 table 5?19. address counters for se rdes bypass lvds transmitter m512 mode deserialization factor write up-counter (fast counter) read up-counter (slow counter) invalid initial cycles width starts at widt h starts at write read 24 4 403224 28 8 503228 416 8 503228 216 16 6032216 table 5?20. address & counter width m512 mode write counter width read counter width write address width read address width number of grounded bits write address read address 24 438744 28 538633 416637512 216538532 5?74 altera corporation stratix device handbook, volume 2 july 2005 software support logic array as serializer /deserializer interface the design can use the lpm_shift_reg megafunction instead of a simple dual port memory block to serialize/deserialize data. the receiver requires an extra flip-flop clocked by the slow clock to latch on to the deserialized data. the transmitter requires a counter to generate the enable signal for the shift register to indicate the times to load and serialize the data. figures 5?47 and 5?48 show the schematic of the 8 lvds receiver and 8 lvds transmitter, resp ectively, with the logic array performing th e deserialization. this scheme can also be used for ap ex ii and mercury device flexible lvds solutions. figure 5?47. serdes bypass lvds receiver with logic array as deserializer pll ddr input shift register shift register dff[7..0] clock serial data in 2 clock1 4 clock0 data_l data[0, 2, 4, 6] data[1, 3, 5, 7] data_h clock clock data data data[7..0] data to logic array rx_clk d q clk altera corporation 5?75 july 2005 stratix device handbook, volume 2 high-speed differential i/o interfaces in stratix devices figure 5?48. serdes bypass lvds transmitter with logic array as deserializer summary the stratix device family of flexib le, high-performance, high-density plds delivers the performance an d bandwidth necessary for complex system-on-a-programmable-chip (sop c) solutions. stratix devices support multiple i/o protocols to interf ace with other devices within the system. stratix devices can easily im plement processing -intensive data- path functions that are received an d transmitted at high speeds. the stratix family of devices combines a high-performance enhanced pld architecture with dedicated i/o circuitry in orde r to provide i/o standard performances of up to 840 mbps. pll counter shift register shift register ddr output clock 1 clock 4 clock data_h data_l data[7..0] clock clock data data load load serial data out tx_clk 5?76 altera corporation stratix device handbook, volume 2 july 2005 summary altera corporation section iv?1 section iv. digital signal processing (dsp) this section provides information for design and optimization of digital signal processing (dsp) functions an d arithmetic operations in the on- chip dsp blocks. it contains the fo llowing chapters: chapter 6, dsp blocks in stratix & stratix gx devices chapter 7, implementing high performance dsp functions in stratix & stratix gx devices revision history the table below shows th e revision history for chapters 6 and 7 . chapter date/version changes made 6 july 2005, v2.2 changed stratix gx fpga family data sheet reference to stratix gx device handbook, volume 1 . september 2004, v2.1 updated ?software support? on page 6?28 . deleted ?quartus ii dsp megafunctions? section. it was replaced by the updated ?software support? on page 6?28 replaced references to an 193 and an 194 with a new reference on page 6?28 . july 2003, v2.0 minor content change. april 2003, v1.0 no new changes in stratix device handbook v2.0. 7 september 2004, v1.1 corrected spelling error. april 2003, v1.0 no new changes in stratix device handbook v2.0. section iv?2 altera corporation digital signal processing (dsp) stratix device handbook, volume 2 altera corporation 6?1 july 2005 6. dsp blocks in stratix & stratix gx devices introduction traditionally, designers had to make a trade-off between th e flexibility of off-the-shelf digital signal processo rs and the performance of custom- built devices. altera ? stratix ? and stratix gx devices eliminate the need for this trade-off by providing exce ptional performance combined with the flexibility of programmable logic devices (plds). stratix and stratix gx devices have dedicated digital signal processing (dsp) blocks, which have high-speed parallel pr ocessing capabilities, that are optimized for dsp applications. dsp blocks are ideal for implementing dsp applications that need high data throughput. the most commonly used dsp function s are finite impuls e response (fir) filters, complex fir filter s, infinite impulse response (iir) filters, fast fourier transform (fft) functions, discrete co sine transform (dct) functions, and correlators. these fu nctions are the building blocks for more complex systems such as wideband code division multiple access (w-cdma) basestations, voice over in ternet protocol (voip), and high- definition television (hdtv). although these functions are comple x, they all use similar building blocks such as multiply- adders and multiply-accumulators. stratix and stratix gx dsp blocks combine five arithmetic operations? multiplication, addition, subtractio n, accumulation, and summation?to meet the requirements of complex functions and to provide improved performance. this chapter describes the strati x and stratix gx dsp blocks, and explains how you can use them to implement high-performance dsp functions. it addresse s the following topics: architecture operational modes software support f see the stratix device family data sheet section of the stratix device handbook, volume 1 and the stratix gx device fa mily data sheet section of the stratix gx device handbook, volume 1 for more information on stratix and stratix gx devices, respectively. s52006-2.2 6?2 altera corporation stratix device handbook, volume 2 july 2005 dsp block overview dsp block overview each stratix and stratix gx device has two columns of dsp blocks that efficiently implement multiplication , multiply accumulate (mac), and filtering functions. figure 6?1 shows one of the columns with surrounding lab rows. you can conf igure each dsp block to support: eight 9 9 bit multipliers four 18 18 bit multipliers one 36 36 bit multiplier figure 6?1. dsp blocks arranged in columns the multipliers can then feed an adder or an accumulator block, depending on the dsp block operational mode. additionally, you can use the dsp block input registers as shift registers to implement applications such as fir filters efficiently. the number of dsp blocks per column dsp block column 8 lab rows dsp block altera corporation 6?3 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices increases with device density. tables 6?1 and 6?2 describe the number of dsp blocks in each stratix and stra tix gx device, respectively, and the multipliers that you can implement. table 6?1. number of dsp blocks in stratix devices note (1) device dsp blocks 9 9 multipliers 18 18 multipliers 36 36 multipliers ep1s10 6 48 24 6 ep1s20 10 80 40 10 ep1s25 10 80 40 10 ep1s30 12 96 48 12 ep1s40 14 112 56 14 ep1s60 18 144 72 18 ep1s80 22 176 88 22 table 6?2. number of dsp blocks in stratix gx devices note (1) device dsp blocks 9 9 multipliers 18 18 multipliers 36 36 multipliers ep1sgx10c 6 48 24 6 ep1sgx10d 6 48 24 6 ep1sgx25c 10 80 40 10 ep1sgx25d 10 80 40 10 ep1sgx25f 10 80 40 10 ep1sgx40d 14 112 56 14 ep1sgx40g 14 112 56 14 note to ta b l e s 6 ? 1 and 6?2 : (1) each device has either the number of 9 9-, 18 18-, or 36 36-bit multipliers shown.the total number of multipliers for each device is no t the sum of all the multipliers. 6?4 altera corporation stratix device handbook, volume 2 july 2005 dsp block overview figure 6?2 shows the dsp block operating as an 18 18 multiplier. figure 6?2. dsp block in 18 18 mode adder/ subtractor/ accumulator adder/ subtractor/ accumulator adder multiplier block output register prn clrn d q ena prn clrn d q ena prn clrn d q ena prn clrn d q ena prn clrn d q ena prn clrn d q ena prn clrn d q ena prn clrn d q ena prn clrn d q ena prn clrn d q ena prn clrn d q ena prn clrn d q ena optional serial shift register inputs from previous dsp block from the row interface block summation block pipeline register adder output block altera corporation 6?5 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices architecture the dsp block consists of the following elements: a multiplier block an adder/subtractor/accumulator block a summation block an output interface output registers routing and control signals multiplier block each multiplier block has input registers, a multiplier stage, and a pipeline register. see figure 6?3 . figure 6?3. multiplier block architecture clrn d q ena data a data b data out to adder blocks shiftoutb shiftouta shiftina shiftinb aclr[3..0] clock[3..0] ena[3..0] signa signb clrn d q ena clrn d q ena 6?6 altera corporation stratix device handbook, volume 2 july 2005 architecture input registers each operand feeds an input register or the multiplier directly. the dsp block has the following signals (one of each controls every input and output register): clock[3..0] ena[3..0] aclr[3..0] the input registers feed the multip lier and drive two dedicated shift output lines, shiftouta and shiftoutb . the shift outputs from one multiplier block directly feed the adjacent multiplier block in the same dsp block (or the next dsp block), as shown in figure 6?4 on page 6?7 , to form a shift register chain. this chai n can terminate in any block, i.e., you can create any length of shift register chain up to 224 registers. a shift register is useful in dsp applications such as fir filters. when implementing 9 9 and 18 18 multipliers, you do not need external logic to create the shift register chai n because the input shift registers are internal to the dsp block. this implementation greatly reduces the required le count and routing resources, and produces repeatable timing. altera corporation 6?7 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices figure 6?4. shift register chain clrn d q ena data a data b a[n] b[n] clrn d q ena clrn d q ena clrn d q ena shiftouta shiftoutb a[n - 1] b[n - 1] clrn d q ena clrn d q ena clrn d q ena shiftouta shiftoutb a[n - 2] b[n - 2] clrn d q ena clrn d q ena dsp block 0 dsp block 1 shiftouta shiftoutb 6?8 altera corporation stratix device handbook, volume 2 july 2005 architecture multiplier stage the multiplier stage supports 9 9, 18 18, or 36 36 multiplication. (the multiplier stage also support smaller multipliers. see ?operational modes? on page 6?18 for details.) based on the data width, a single dsp block can perform many multiplications in parallel. the multiplier operands can be si gned or unsigned numbers. two signals, signa and signb , indicate the representation of the two operands. for example, a logic 1 on the signa signal indicates that data a is a signed number; a logic 0 indicates an unsigned number. the result of the multiplication is signed if any one of the operands is a signed number, as shown in table 6?3 . the signa and signb signals affect the entire dsp block. therefore, all of the data a inputs feeding the same dsp block must have the same sign representation. similarly, all of the data b inputs feeding the same dsp block must have the same sign repres entation. the multiplier offers full precision regardless of the sign representation. 1 by default, the altera quartus ? ii software sets the multiplier to perform unsigned multiplication when the signa and signb signals are not used. pipeline registers the output from the multiplier can feed a pipeline register or be bypassed. you can use pipeline re gisters for any multiplier size; pipelining is useful for increa sing the dsp bloc k performance, particularly when using subsequent adder stages. 1 in the dsp block, pipelining improves the performance of 36 36 multipliers. for 18 18 multipliers and smaller, pipelining adds latency but does not improve performance. table 6?3. multiplier signed representation data a data b result unsigned unsigned unsigned unsigned signed signed signed unsigned signed signed signed signed altera corporation 6?9 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices adder/output block the adder/output block has th e following elements (see figure 6?5 on page 6?10 ): an adder/subtractor/accumulator block a summation block an output select multiplexer output registers you can configure the adder/output block as: a pure output interface an accumulator a simple one-level adder a two-level adder with dynamic addition/subtraction control on the first-level adder the final stage of a 36-bit multiplier the output select multiplexer sets th e output of the dsp block. you can register the adder/output block?s ou tput using the output registers. 1 you cannot use the adder/output block independently of the multiplier. 6?10 altera corporation stratix device handbook, volume 2 july 2005 architecture figure 6?5. adder/output block adder/subtractor/accumulator block the adder/subtractor/accumulator is the first level of the adder/output block. you can configure the bloc k as an accumulator or as an adder/subtractor. accumulator when the adder/subtractor/accumu lator is configured as an accumulator, the output of the adder/output block feeds back to the accumulator as shown in figure 6?5 . you can use the adder/ subtractor/ accumulator 0 adder result a result b result c result d addnsub1 accum_sload0 addnsub3 signa signb accum_sload1 accumulator feedback accumulator feedback overflow0 adder/ subtractor/ accumulator 1 output select multiplexer output registers overflow1 altera corporation 6?11 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices accum_sload[1..0] signals to clear the acc umulator asynchronously. this action is not the same as resetti ng the output registers. you can clear the accumulation and begin a new on e without losing any clock cycles. the overflow signal goes high on the posi tive edge of the clock when the accumulator ov erflows or underflows. in the next clock cycle, however, the overflow signal resets to zero even though an overflow (or underflow) occurred in the previous clock cycle. use a latch to preserve the overflow condition indefinitely (until the latch is cleared). adder/subtractor the addnsub[1..0] signals select addition or subtraction: high for addition and low for subtraction. you can control the addnsub[1..0] signals using external logic; therefore, the first-level block can switch from an adder to a subtractor dy namically, simply by changing the addnsub[1..0] signals. if the first stage is configured as a subtractor, the output is a - b and c - d. the adder/subtractor also uses two signals, signa and signb , like the multiplier block. these signals indicate the sign representation of both operands together. you can register th e signals with a latency of 1 or 2 clock cycles. summation block the output from the adde r/subtractor feeds to an optional summation block, which is an adder block that sums the outputs of the adder/subtractor. the summation bloc k is important in applications such as fir filters. output select multiplexer the outputs from the various elemen ts of the adder/output block are routed through an output select mu ltiplexer. based on the dsp block operational mode, the outputs of the multiplier block, adder/subtractor/accumulator, or su mmation block feed straight to the output, bypassing the remainin g blocks in the dsp block. 1 the output select multiplier configuration is configured automatically by software. output registers you can use the output registers to re gister the dsp bloc k output. like the input registers, the output regi sters are controlled by the four clock[3..0] , aclr[3..0] , and ena[3..0] signals. you can use the output registers in any ds p block operational mode. 6?12 altera corporation stratix device handbook, volume 2 july 2005 architecture 1 the output registers form part of the accumulator in the multiply-accumulate mode. routing structure & control signals this section describes the interface between the dsp blocks and the row interface blocks. it also describes how the dsp block generates control signals and how the signals route from the row interface to the dsp block. dsp block interface the dsp blocks are organized in columns, which provides efficient horizontal communication between the blocks and the column-based memory blocks. the dsp block commu nicates with other parts of the device through an input and output interface. each dsp block, including the input and output interface, is 8 logic array blocks (labs) long. the dsp block and row interface bloc ks consist of eight blocks that connect to eight adjacent lab rows on the left and right. each of the eight blocks has two regions: right and left, one per row. the dsp block receives 144 data input signals and 18 control signals for a total of 162 input signals. this bl ock drives out 144 data ou tput signals; 2 of the data signals can be used as overflow signals ( overflow ). figure 6?6 provides an overview of the dsp bloc k and its interface to adjacent labs. figure 6?6. dsp block interface to adjacent labs input interface the dsp block input interface has 162 input signals from adjacent labs; 18 data signals per row and 18 control signals per block. output interface the dsp block output interface driv es 144 outputs to adjacent labs, 18 signals per row from 8 rows. 144 8 lab rows row interfaces 0 through 7 dsp block 8 lab rows dsp block & row interface 144 18 data control 162 dsp block input interface dsp block output interface altera corporation 6?13 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices because the dsp block outputs comm unicate horizontally, and because each dsp block row has more outputs than an lab (18 from the dsp block compared to 10 from an lab), the dsp block has double the number of row channel drivers compared to an lab. the dsp block has the same number of row channels, bu t the row channels are staggered as if there were two labs within each block. the dsp blocks have the same number of column channels as labs because dsp blocks communicate primarily through row channels. row interface block each row interface block connects to the dsp block row structure with 21 signals. because each dsp block ha s eight row interf ace blocks, this block receives 162 signals from the eight row interfaces. of the 162 signals, 144 are data inputs and 18 are control signals. figure 6?7 on page 6?14 shows one row block within the dsp block. 6?14 altera corporation stratix device handbook, volume 2 july 2005 architecture figure 6?7. dsp row interface block control signals in the row interface block the dsp block has a set of input regi sters, a pipeline register, and an output register. each register is grouped in banks that share the same clock and clear resources: 1- to 9-bit banks for the input register 1- to 18-bit banks for the pipeline register 18 bits for the output register lab lab row interface block dsp block row structure 10 [17..0] [17..0] dsp block to lab row interface block interconnect region 1 8 inputs per row 1 8 outputs per row r4 and r 8 interconnects c 4 and c 8 int e r co nn ec t s dir ec tlink int e r co nn ect f rom ad j acent la b nine directlink outputs to adjacent labs directlink interconnect from adjacent lab 18 18 9 10 3 control 9 18 altera corporation 6?15 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices the row interface block generates the control signals and routes them to the dsp block. each dsp block has 18 control signals: four clock signals ( clock[3..0] ), which are available to each bank of dsp blocks four clear signals ( aclr[3..0] ), which are available to each bank of dsp blocks four clock enable signals ( ena[3..0] ), which the wh ole dsp block can use signa and signb , which are specific to each dsp block addnsub[1..0] signals accum_sload[1..0] signals the signa , signb , and addnsub[1..0] , accum_sload[1..0] signals have independent clocks an d clears and can be registered individually. when each 18 18 multiplier in the dsp block splits in half to two 9 9 multipliers, each 9 9 multiplier has independent control signals. figure 6?8 shows the dsp block row interface and shows how it generates the data and control signals. figure 6?8. dsp block row interface dsp row 1 dsp row 2 dsp row 3 dsp row 4 dsp row 5 dsp row 6 dsp row 7 dsp row 8 dsp block row interface input registers dsp block bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 dsp row bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 bit 17 dsp row 21 signals for data to input register dsp row unit control block 3 30 local interconnect signals lab row clocks detail of 1 dsp row 6?16 altera corporation stratix device handbook, volume 2 july 2005 architecture the dsp block interface generates the clock signals from lab row clocks or the local interconnect. the clear signals are generated from the local interconnects within each dsp bloc k row interface or from lab row clocks. the four clock en able signals are generated from the 30 local interconnects from the same lab rows that generate the clock signals. the clock enable is paired with th e clock because the enable logic is implemented at the interface. figure 6?9 shows the signal distribution within the row interface block. figure 6?9. dsp block row inte rface signal distribution 18 18 multiplier a1 b1 18 18 18 18 row 1 row 2 18 18 multiplier a4 b4 18 18 18 18 row 7 row 8 4 4 4 18 clock[3..0] aclr[3..0] ena[3..0] data[17..0] input registers 1 8 -bit data routed from 3 0 local interconnects four clock enable signals routed from 3 0 local interconnects four clear signals routed from 3 0 local interconnects or lab row clock four clock signals routed from lab row clock or local interconnect altera corporation 6?17 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices each row block provides 18 bits of data to the multiplier (i.e., one of the operands to the multiplier), whic h are routed through the 30 local interconnects within each dsp row in terface block. any signal in the device can be the source of the 18-bi t multiplier data, by connecting to the local row interconnect through any row or column. each control signal routes through one of the eight rows of the dsp block. table 6?4 shows the 18 control signals and the row to which each one routes. input/output data interface routing the 30 local interconnects generate the 18 inputs to the row interface blocks. the 21 outputs of the row inte rface block are the inputs to the dsp row block (see figure 6?7 on page 6?14 ). table 6?4. control signals in dsp block signal name row description signa 1 dsp block-wide signed and unsigned cont rol signals for all multipliers. the multiplier outputs are unsigned only if both signa and signb are low. signb 6 addnsub1 3 controls addition or subtraction of the two one-level adders. the addnsub0 signal controls the top two one-level adders; the addnsub1 signal controls the bottom two one-level adders. a high indicates addition; a low indicates subtraction. addnsub3 7 accum_sload0 2 resets the feedback input to the accumulator. the signal asynchronously clears the accumulato r and allows new accumulation to begin without losing any clock cycles. the accum_sload0 controls the top two one-level adders, and the accum_sload1 controls the bottom two one-level adders. a low is for normal accumulation operations and a high is for zeroing the accumulator. accum_sload1 7 clock0 3 dsp block-wide clock signals. clock1 4 clock2 5 clock3 6 aclr0 1 dsp block-wide clear signals. aclr1 4 aclr2 5 aclr3 7 ena[3..0] same rows as the clock signals dsp block-wide clock enable signals. 6?18 altera corporation stratix device handbook, volume 2 july 2005 operational modes the row interface block has directli nk? connections that connect the dsp block input or output signals to th e left and right adjacent labs at each row. (the directlink connections provide interconnects between labs and adjacent blocks.) the dire ctlink connection reduces the use of row and column interconnects, providing higher performance and flexibility. each row interface block receives 10 directlink connections from the right adjacent labs and 10 from the le ft adjacent labs. additionally, the row interface block receiv es signals from the dsp block, making a total of 30 local interconnects for each row interface block. all of the row and column resources within the dsp block can access this interconnect region (see figure 6?7 on page 6?14 ). a dsp block has nine outputs that dr ive the right adjacent lab and nine that drive the left adjacent lab th rough directlink interconnects. all 18 outputs drive any row or column. operational modes you can use the dsp block in one of four operational modes, depending on your application needs (see table 6?4 ). the quartus ii software has built-in megafunctions that you can use to control the mode. after you have made your parameter setti ngs using the megafunction?s megawizard ? plug-in, the quartus ii soft ware automatically configures the dsp block. simple multiplier mode in simple multiplier mode, the dsp block performs individual multiplication operations for general-purpose multipliers and for applications such as equalizer coefficient updates that require many individual multiplication operations. table 6?5. dsp block operational modes mode 9 9 18 18 36 36 simple multiplier eight multipliers with eight product outputs four multipliers with four product outputs one multiplier multiply accumulator two 34-bit multiply- accumulate blocks two 52-bit multiply- accumulate blocks ? two-multiplier adder four two-mult iplier adders two two-multiplier adders ? four-multiplier adder two four-multi plier adders one four-multiplier adder ? altera corporation 6?19 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices 9- & 18-bit multipliers you can configure each dsp block multiplier for 9 or 18 bits. a single dsp block can support up to 8 individual 9-bi t or smaller multipliers, or up to 4 individual multipliers with operand widths between 10- and 18-bits. figure 6?10 shows the simple multiplier mode. figure 6?10. simple multiplier mode the multiplier operands can accept sign ed integers, unsigned integers, or a combination. the signa and signb signals are dynamic and can be registered in the dsp block. addition ally, you can register the multiplier inputs and results independently. pipelining the result, using the pipeline registers in the block, in creases the performance of the dsp block. 36-bit multiplier the 36-bit multiplier is a subset of the simple multiplier mode. it uses the entire dsp block to implement one 36 36-bit multiplier. the four 18-bit multipliers are fed part of each input, as shown in figure 6?11 on page 6?21 . the adder/output block adds the partial products using the clrn d q ena a clrn d q ena clrn d q ena a b shiftoutb shiftouta signb signa adder output block 6?20 altera corporation stratix device handbook, volume 2 july 2005 operational modes summation block. you can use pipeline registers between the multiplier stage and the summation block. the 36 36-bit multiplier supports signed and unsigned operation. the 36-bit multiplier is useful when your application needs more than 18-bit precision, for example, for ma ntissa multiplication of precision floating-point arithm etic applications. altera corporation 6?21 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices figure 6?11. 36-bit multiplier clrn d q ena a[17..0] a[17..0] b[17..0] b[17..0] a[35..18] a[35..18] b[35..18] b[35..18] signa signb clrn d q ena clrn d q ena clrn d q ena clrn d q ena clrn d q ena clrn d q ena clrn d q ena clrn d q ena clrn d q ena clrn d q ena clrn d q ena clrn d q ena data out partial product summation block a b c d 6?22 altera corporation stratix device handbook, volume 2 july 2005 operational modes multiply accumulator mode in multiply accumulator mode, the ou tput of the multiplier stage feeds the adder/output block, which is configured as an accumulator or subtractor (see figure 6?12 ). you can implement up to two independent 18-bit multiply accumulators in one dsp block. the quartus ii software implements smaller multiplier-accumulators by tying the unused low- order bits of an 18-bi t multiplier to ground. figure 6?12. multiply accumulator mode note to figure 6?12 : (1) the signa and signb signals are the same in the multipli er stage and the adder/output block. the multiply accumulator output can be up to 52 bits wide for a maximum 36-bit result with 16-bits of accumulation. in this mode, the dsp block uses output registers and the accum_sload and overflow signals. the accum_sload[1..0] signal synchronously loads the multiplier result to the accumulator output. this signal can be unregistered or registered once or twice. the dsp block can then begin a new accumulation without lo sing any clock cycles. the overflow signal indicates an overflow or underflow in the accumulator. this signal is clrn d q ena clrn d q ena data a data b data out overflow shiftoutb shiftouta shiftina shiftinb aclr clock ena signa (1) signb (1) clrn d q ena clrn d q ena accumulator addnsub1 signa signb accum_sload1 clrn d q ena altera corporation 6?23 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices cleared for the next accumulation cycl e, and you can use an external latch to preserve the signal. you can use the addnsub[1..0] signals to perform accumulation or su btraction dynamically. 1 if you want to use dsp blocks and your design only has an accumulator, you can use a multiply by one followed by an accumulator to force the software to implement the logic in the dsp block. two-multiplier adder mode the two-multiplier adder mode uses the adder/output block to add or subtract the outputs of the multipl ier block, which is useful for applications such as fft functions and complex fir filters. additionally, in this mode, the dsp block outputs two sums or differences for multipliers up to 18 bits, or 4 sums or differences for 9-bit or smaller multipliers. a single dsp block can implement one 18 18-bit complex multiplier or two 9 9-bit complex multipliers. a complex multiplicatio n can be written as: ( a + jb ) ( c + jd ) = ( a c ? b d ) + j ( a d + b c ) in this mode, a single dsp bloc k calculates the real part ( a c ? b d ) using one adder/subtractor/accumula tor and the imaginary part ( a d + b c ) using another adder/subtractor/acc umulator for data up to 18 bits. figure 6?13 shows an 18-bit complex multiplication. for data widths up to 9 bits, the dsp block can perfor m two complex multiplications using four one-level adders. resources ou tside of the dsp block route each input to the two multiplier inputs. 1 you can only use the adder block if it follows multiplication operations. 6?24 altera corporation stratix device handbook, volume 2 july 2005 operational modes figure 6?13. complex multiplier implem ented using two-multiplier adder mode four-multiplier adder mode in the four-multiplier adder mode, which you can use for 1-dimensional and 2-dimensional filtering applications, the dsp block adds the results of two adder/subtractor/accumulator s in a final stage (the summation block). 1 you can only use the adder block if it follows multiplication operations. 9- & 18-bit summation blocks a single dsp block can implement one 18 18 or two 9 9 summation blocks (see figure 6?14 on page 6?25 ). the multiplier product widths must be the same size. subtractor 36 36 18 18 18 37 a c b d 18 a c - b d (real part) adder 36 36 18 18 37 a d b c a d + b c (imaginary part) 18 18 18 dsp block altera corporation 6?25 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices figure 6?14. four-multiplier adder mode clrn d q ena data a data b shiftinb shiftina aclr clock ena signa signb clrn d q ena clrn d q ena clrn d q ena data a data b clrn d q ena clrn d q ena adder/ subtractor clrn d q ena data a data b clrn d q ena clrn d q ena clrn d q ena data a data b shiftoutb shiftouta clrn d q ena clrn d q ena adder/ subtractor addnsub0 signa signb clrn d q ena data out addnsub1 adder 6?26 altera corporation stratix device handbook, volume 2 july 2005 operational modes fir filters the four-multiplier adder mode can be used for fir filter and complex fir filter applications. the dsp bloc k combines a four-multiplier adder with the input registers configured as shift registers. one set of shift inputs contains the filter data, wh ile the other holds the coefficients, which can be loaded serially or in parallel (see figure 6?15 ). the input shift register eliminates th e need for shift registers external to the dsp block (e.g., implemented in device logic elements). this architecture simplifies filter design and improves performance because the dsp block implements all of the filter circuitry. 1 serial shift inputs in 36-bit simple multiplier mode require external registers. one dsp block can implement an entire 18-bit fir filter with up to four taps. for fir filters larger than fo ur taps, you can cascade dsp blocks with additional adder stages implemented in logic elements. altera corporation 6?27 july 2005 stratix device handbook, volume 2 dsp blocks in stratix & stratix gx devices figure 6?15. input shift registers configured for a fir filter clrn d q ena data a data b a[n] b[n] (to adder) clrn d q ena clrn d q ena clrn d q ena data a data b a[n - 1] b[n - 1] (to adder) clrn d q ena clrn d q ena clrn d q ena data a data b a[n - 2] b[n - 2] (to adder) clrn d q ena clrn d q ena 6?28 altera corporation stratix device handbook, volume 2 july 2005 software support software support altera provides two distinct method s for implementing various modes of the dsp block in your design: instan tiation and inferenc e. both methods use the following three quartus ii megafunctions: lpm_mult altmult_add altmult_accum you can instantiate the megafunction s in the quartus ii software to use the dsp block. alternatively, with in ference, you can create a hdl design an synthesize it using a third-party synthesis tool like leonardospectrum or synplify or quartus ii native sy nthesis that infers the appropriate megafunction by recognizing multipliers, multiplier adders, and multiplier accumula tors. using either method, the quartus ii software maps the functionality to the ds p blocks during compilation. f see the implementing high-performance dsp functions in stratix & stratix gx devices chapter in the stratix device ha ndbook, volume 2 or the stratix gx device handbook, volume 2 for more informat ion on using dsp blocks to implement high-p erformance dsp functions such as fir filters, iir filters, and discreet cosine transforms (dcts). f see quartus ii on-line help for inst ructions on using the megafunctions and the megawizard plug-in manager. f for more information on dsp bl ock inference support, see the recommended hdl coding styles chapter of the quartus ii development software handbook v4.1, volume 1 . conclusion the stratix and stratix gx device dsp blocks are optimized to support dsp applications that need high data throughput, such as fir filters, fft functions, and encoders. these dsp blocks are flexible and can be configured in one of four operationa l modes to suit any application need. the dsp block?s adder/subtractor /accumulator and the summation blocks minimize the amou nt of logic resources used and provide efficient routing. this efficiency results in improved performance and data throughput for dsp applications. the quartus ii software , together with the leonardospectrum and synplify software, provides a complete and easy-to-use flow for implementing functionality in the dsp block. altera corporation 7?1 september 2004 7. implementing high performance dsp functions in stratix & stratix gx devices introduction digital signal processing (dsp) is a rapidly advancing field. with products increasing in complexity, designers face the challenge of selecting a solution with both flexibility and high performance that can meet fast time-to-market requirements . dsp processors offer flexibility, but they lack real-time performance, while application-specific standard products (assps) and application-specific integrated circuits (asics) offer performance, but they are in flexible. only programmable logic devices (plds) offer both flexibility and high performance to meet advanced design challenges. the mathematical theory underlying basic dsp building blocks?such as the finite impulse respon se (fir) filter, infinite impulse response (iir) filter, fast fourier transform (fft), and direct cosine transform (dct)?is computationally intensive. altera ? stratix ? and stratix gx devices feature dedicated dsp blocks optimized for implementing arithmetic operations, such as multiply, mult iply-add, and multiply-accumulate. in addition to dsp blocks, strati x and stratix gx devices have trimatrix? embedded memory blocks that feature various sizes that can be used for data buffering, which is important for most dsp applications. these dedicated hardware features make stratix and stratix gx devices an ideal dsp solution. this chapter describes the implemen tation of high performance dsp functions, including filters, transforms, and arithmetic functions, using stratix and stratix gx dsp blocks. the following topics are discussed: fir filters iir filters matrix manipulation discrete cosine transform arithmetic functions stratix & stratix gx dsp block overview stratix and stratix gx devices feature dsp blocks that can efficiently implement dsp functions, including multiply, multiply-add, and multiply-accumulate. the dsp blocks al so have three built-in registers sets: the input registers, the pipeline registers at the multiplier output, and the output registers. figure 7?1 shows the dsp block operating in the 18 18-bit mode. s52007-1.1 7?2 altera corporation stratix device handbook, volume 2 september 2004 stratix & stratix gx dsp block overview figure 7?1. dsp block diagram for 18 x 18-bit mode adder/ subtractor/ accumulator 2 adder/ subtractor/ accumulator 1 summation optional pipeline register stage m ultiplier stage output selection m ultiplexer optional output register stage clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena clrn dq ena optional serial shift register inputs from previous dsp block optional stage configurable as accumulator or dynamic adder/subtractor summation stage for adding four m ultipliers together optional input register stage with parallel input or shift register configuration optional serial shift register outputs to next dsp block in the column to multitrack interconnect altera corporation 7?3 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices the dsp blocks are organized into co lumns enabling efficient horizontal communication with adjacent trimatrix memory blocks. tables 7?1 and 7?2 show the dsp block resources in stratix and stratix gx devices, respectively. table 7?1. dsp block resour ces in stratix devices device dsp blocks maximum 9 9 multipliers maximum 18 18 multipliers maximum 36 36 multipliers ep1s10 6 48 24 6 ep1s20 10 80 40 10 ep1s25 10 80 40 10 ep1s30 12 96 48 12 ep1s40 14 112 56 14 ep1s60 18 144 72 18 ep1s80 22 176 88 22 table 7?2. dsp block resource s in stratix gx devices device dsp blocks maximum 9 9 multipliers maximum 18 18 multipliers maximum 36 36 multipliers ep1sgx10c 6 48 24 6 ep1sgx10d 6 48 24 6 ep1sgx25c 10 80 40 10 ep1sgx25d 10 80 40 10 ep1sgx25f 10 80 40 10 ep1sgx40d 14 112 56 14 ep1sgx40g 14 112 56 14 7?4 altera corporation stratix device handbook, volume 2 september 2004 trimatrix memory overview each dsp block supports either eight 9 9-bit multipliers, four 18-bit multipliers, or one 36 36-bit multiplier. these multipliers can feed an adder or an accumulator unit based on the operation mode. table 7?3 shows the different operation modes for the dsp blocks. implementing multipliers, multiply-adders, and multiply-accumulators in the dsp blocks has a performa nce advantage over logic cell implementation. using dsp blocks also reduces logic cell and routing resource consumption. to achieve hi gher performance, register each stage of the dsp block to allow pipelining. for implementing applications, such as fir filters, effi ciently use the input registers of the dsp block as shift registers. f for more information on dsp blocks, see the dsp blocks in stratix & stratix gx devices chapter. trimatrix memory overview stratix and stratix gx devices feature the trimatrix memory structure, composed of three sizes of embedd ed ram blocks. these include the 512-bit size m512 block, the 4-kbit si ze m4k block, and the 512-kbit size m-ram block. each block is configurable to support a wide range of features. tables 7?4 and 7?5 show the number of memory blocks in each stratix and stratix gx device, respectively. table 7?3. operation modes for dsp blocks dsp block mode number & size of multipliers per dsp block 9 x 9-bit 18 x 18-bit 36 x 36-bit simple multiplier eight multipliers with eight product outputs four multipliers with four product outputs one multiplier with one product output multiply-accumulate two multiply and accumulate (34 bit) two multiply and accumulate (52 bit) two-multipliers adder 4 two-multiplie rs adders 2 two-multipliers adders four-multipliers adder 2 f our-multipliers adder 1 four-multipliers adder table 7?4. trimatrix memory resources in stratix devices (part 1 of 2) device m512 m4k m-ram ep1s10 94 60 1 ep1s20 194 82 2 ep1s25 224 138 2 altera corporation 7?5 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices most dsp applications require local data storage for intermediate buffering or for filter storage. th e trimatrix memory blocks enable efficient use of available resources for each application. the m512 and m4k memory blocks can implement shift registers for applications, such as multi-channel filtering, auto-correlation, and cross- correlation functions. implementing shift registers in embedded memory blocks reduces logic cell and routing resource consumption. f for more information on trim atrix memory blocks, see the tr i m a t r i x embedded memory blocks in stratix & stratix gx devices chapter. dsp function overview the following sections describe commonly used dsp functions. each section illustrates the im plementation of a basi c dsp building block, including fir and iir filters, in stratix and stratix gx devices using dsp blocks and trimatrix memory blocks. finite impulse response (fir) filters this section describes the basic theory and implementation of basic fir filters, time-domain multi plexed (tdm) fir filters, and interpolation and decimation polyphase fir filters. an introduction to the complex fir filter is also presented in this section. ep1s30 295 171 4 ep1s40 384 183 4 ep1s60 574 292 6 ep1s80 767 364 9 table 7?5. trimatrix memory resources in stratix gx devices device m512 m4k m-ram ep1sgx10c 94 60 1 ep1sgx10d 94 60 1 ep1sgx25c 224 138 2 ep1sgx25d 224 138 2 ep1sgx25f 224 138 2 ep1sgx40d 384 183 4 ep1sgx40g 384 183 4 table 7?4. trimatrix memory resources in stratix devices (part 2 of 2) device m512 m4k m-ram 7?6 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters fir filter background digital communications systems use fir filters for a variety of functions, including waveform shaping, anti-aliasing, band selection, decimation/interpolation, and low pass filtering. the basic structure of a fir filter consists of a series of multiplications followed by an addition. the following equation represents an fir filter operation: where: x ( n ) represents the sequence of input samples h ( n ) represents the filter coefficients l is the number of filter taps a sample fir filter with l =8 is shown in figure 7?2 . figure 7?2. basic fir filter this example filter in figure 7?2 uses the input values at eight different time instants to produce an output. hence, it is an 8-tap filter. each register provides a unit sample delay. the delayed inputs are multiplied with their respective filter coefficien ts and added together to produce the output. the width of the output bus depends on the number of taps and the bit width of the input and coefficients. yn () xn () hn () ? = yn () xn i ? () hi () i0 = l1 ? = x(n) y(n) h (2) h (1) h (3) h (4) h (5) h (6) h (7) h (0) altera corporation 7?7 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices basic fir filter a basic fir filter is the simplest fir filter type. as shown in figure 7?2 , a basic fir filter has a single input channel and a single output channel. basic fir filter implementation stratix and stratix gx devices? dedicated dsp blocks can implement basic fir filters. because these dsp blocks have closely integrated multipliers and adders, filters can be implemented with minimal routing resources and delays. for implementing fir filters, the dsp blocks are configured in the four-multipliers adder mode. f see the dsp blocks in stratix & stratix gx devices chapter for more information on the different modes of the dsp blocks. this section describes the implementa tion of an 18-bit 8-tap fir filter. because stratix and stratix gx devices support modularity, cascading two 4-tap filters can implement an 8-tap filter. larger fir filters can be designed by extending this concept. users can also increase the number of taps available per dsp block if 18 bi ts of resolution are not required. for example, by using only 9 bits of resolution for input samples and coefficient values, 8 multipliers are av ailable per dsp block. therefore, a 9-bit 8-tap filter can be implemented in a single dsp block provided an external adder is implemented in logic cells. the four-multipliers adder mode, shown in figure 7?3 , provides four 18 18-bit multipliers and three adders in a single dsp block. hence, it can implement a 4-tap filter. the data width of the input and the coefficients is 18 bits, which results in a 38-bit output for a 4-tap filter. 7?8 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters figure 7?3. hardware view of a dsp bl ock in four-multipliers adder mode notes (1) . (2) , (3) notes to figure 7?3 : (1) the input registers feed the multiplier blocks. these registers can increase the dsp block performance, but are optional. these registers can also function as shift registers if the dedicated shiftin/shiftout signals are used. (2) the pipeline registers are fed by the multiplier blocks. these registers can increase th e dsp block performance, but are optional. (3) the output registers register the dsp block output. these registers can increase the dsp block performance, but are optional. d q d q d q d q d q d q d q d q 18 18 18 18 18 18 18 18 18 18 18 36 36 36 36 37 37 38 output y ( n ) x ( n ) h (0) x ( n -1) h (1) x ( n -2) h (2) x ( n -3) h (3) multiplier d multiplier c multiplier b multiplier a clk1 clr1 clk2 clr2 shiftout input from previous block shiftout input from previous block data from row interface block coefficients from row interface block shiftin input to next block shiftin input to next block data from row interface block data from row interface block data from row interface block coefficients from row interface block coefficients from row interface block coefficients from row interface block 18 18 18 18 18 d q d q d q d q d q 38 altera corporation 7?9 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices figure 7?4. quartus ii software view of megawizard implem entation of a dsp bloc k in four-multipliers adder mode each input register of the dsp bloc k provides a shiftout output that connects to the shiftin input of the adja cent input register of the same dsp block. the registers on the boundaries of a dsp block also connect to the registers of adjacent dsp blocks th rough the use of shiftin/shiftout connections. these connec tions create register chains spanning multiple dsp blocks, which makes it easy to increase the length of fir filters. figure 7?5 shows two dsp blocks connected to create an 8-tap fir filter. filters with more taps can be implem ented by connecting dsp blocks in a similar manner, provided sufficient dsp blocks are available in the device. 1 adding the outputs of the two dsp blocks requires an external adder which can be implemented using logic cells. the input data can be fed directly or by using the shiftout/shiftin chains, which allow a single input to shift down the register chain inside the dsp block. the input to each of the register s has a multiplexer, hence, the data can be fed either from outside the dsp block or the preceding register. this can be selected from the megawizard ? in the quartus ? ii software, as shown in figure 7?4 . the example in figure 7?5 uses the shiftout/shiftin flip-flop chains where the multiplexers are configured to use these chains. in this example, the flip-flops inside the dsp blocks serve as the taps of the fir filter. 7?10 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters when the coefficients are loaded in parallel, they can be fed directly from memory elements or any other muxi ng scheme. this facilitates the implementation of an adap tive (variable) filter. further, if the user wants to implemen t the shift register chains external to the dsp block, this can be done by using the altshift_taps megafunction. in this case, the coef ficient and data shifting is done external to the dsp block. the dsp block is only used to implement the multiplications and the additions. parallel vs. serial implementation the fastest implementations are fully parallel, but consume more logic resources than serial implementations. to trade-off performance for logic resources, implement a serial scheme with a specified number of taps. to facilitate this, altera provides the fir compiler core through its megacore program. the fir compiler is an easy-to-use, fully-integrated graphical user interface (gui) ba sed fir filter design software. f for more information on the fir compiler megacore, visit the altera web site at www.altera.com and search for ?fir compiler? in the ?intellectual property? page. it is important to note that the four-multipliers adder mode allows a dsp block to be configured for parallel or se rial input. when it is configured for parallel input, as shown in figure 7?6 , the data input and the coefficients can be loaded directly without the need for shiftin/shiftout chains between adjacent registers in the dsp block. when the dsp block is configured for serial input, as shown in figure 7?5 , the shiftin/shiftout chains create a register cascade b oth within the dsp block and also between adjacent dsp blocks. altera corporation 7?11 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices figure 7?5. serial loading 18-bit 8-tap fir filter using two dsp blocks notes (1) , (2) , (3) notes to figure 7?5 : (1) unused ports grayed out. (2) the indexing x ( n -1), ..., x ( n -7) refers to the case of parallel loading and should be ignored here. this indexing is retained in this figure for consistency with other figures in this chapter. (3) to increase the dsp block performance, in clude the pipeline and output registers. see figure 7?3 on page 7?8 for the details. dq d q d q d q d q d q d q d q dsp block 1 filter output y ( n ) h (0) h ( 1 ) h ( 2 ) h ( 3 ) x (n) filter coefficients data input x (n-2) x x x (n-3) x x x (n-1) x x h ( 4 ) h (5 ) h ( 6 ) h (7) x (n-4) x x x (n-5) x x x (n-6) x x x (n-7) x x d q d q d q d q d q d q d q dq dsp block 2 7?12 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters figure 7?6. parallel loading 18-bit 8-tap fir filter using two dsp blocks notes (1) , (2) notes to figure 7?6 : (1) the indexing x ( n -1), ..., x ( n -7) refers to the case of parallel loading. (2) to increase the dsp block performance, include the input, pipeline, and output registers. see figure 7?3 on page 7?8 for the details. d q d q d q d q d q d q d q d q dsp block 1 filter output y ( n ) h (0) h (1) h (2) h (3) x (n) filter coefficients data input x (n-2) x (n-3) x (n-1) h (4) h (5) h (6) h (7) x (n-4) x (n-5) x (n-6) x (n-7) d q d q d q d q d q d q d q d q dsp block 2 altera corporation 7?13 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices basic fir filter implementation results table 7?6 shows the results of the serial implementation of an 18-bit 8 tap fir filter as shown in figure 7?5 on page 7?11 basic fir filter design example download the basic fir filter ( base_fir.zip ) design example from the design examples section of the altera web site at www.altera.com. time-domain multiplexed fir filters a tdm fir filter is clocked n -times faster than the sample rate in order to reuse the same hardware. consider the 8-tap filter shown in figure 7?2 . the tdm technique can be used wi th a tdm factor of 2, i.e., n = 2, to implement this filter using only four multipliers, provided the filter is clocked two times faster internally. to understand this concept, consider figure 7?7 that shows a tdm filter with a tdm factor of 2. a 2 -multiplied clock is required to run the filter. on cycle 0 of the 2 clock, the user loads four coefficients into the four multiplier inputs. the resulting output is stored in a register. on cycle 1 of the 2 clock, the user loads the rema ining four coefficients into the multiplier inputs. th e output of cycle 1 is adde d with the output of cycle 0 to create the overall output. see the ?tdm filter implementation? on page 7?14 section for details on the coefficient loading schedule. the tdm implementation shown in figure 7?7 requires only four multipliers to achieve the functionalit y of an 8-tap filter. thus, tdm is a good way to save logic resources, pr ovided the multipliers can run at n- times the clock speed. the coefficien ts can be stored in rom/ram, or any other muxing scheme. table 7?6. basic fir filter implementation results part ep1s10f780 utilization lcell: 130/10570 (1 % ) dsp block 9-bit elements: 16/48 (33 % ) memory bits: 288/920448 (<1 % ) performance 247 mhz 7?14 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters figure 7?7. block diagram of 8-tap fir filter with tdm factor of n=2 tdm filter implementation tdm fir filters are implemented in stratix and stratix gx devices by configuring the dsp blocks in the multiplier-adder mode. figure 7?9 shows the implementation of an 8-tap tdm fir filter ( n =2) with 18 bits of data and coefficient inputs. becaus e the input data needs to be loaded into the dsp block in parallel, a shift register chain is implemented using a combination of logic cells and the altshift_taps function. this shift register is clocked with the same data sample rate (clock 1 ). the filter coefficients are stored in rom and loaded into the dsp block in parallel as well. because the tdm factor is 2, both the rom and dsp block are clocked with clock 2 . figure 7?8 and table 7?7 show the coefficient loading schedule. for example, during cycle 0, only the flip-flops corresponding to h (1), h (3), h (5), and h (7) are enabled. this produces the temporary output, y 0 , which is stored in a flip-flop outside the dsp block. during cycle 1, only the flip- d q fir filter with four multipliers 18-bit input 2x clock output table 7?7. operation of tdm filter (shown in figure 7?9 on page 7?16 ) cycle of 2 clock cycle output operation overall output, y(n) 0 y 0 = x ( n -1)h(1) + x ( n -3)h(3) + x ( n -5)h(5) + x ( n -7)h(7) store result n/a 1 y 1 = x ( n )h(0) + x ( n -2)h(2) + x ( n -4)h(4) + x ( n -6)h(6) generate output y ( n ) = y 0 + y 1 2 y 2 = x ( n )h(1) + x ( n -2)h(3) + x ( n -4)h(5) + x ( n -6)h(7) store result n/a 3 y 3 = x ( n +1)h(0) + x ( n -1)h(2) + x ( n -3)h(4) + x ( n -5)h(6) generate output y ( n ) = y 2 + y 3 4 y 4 = x ( n +1)h(1) + x ( n -1)h(3) + x ( n -3)h(5) + x ( n -5)h(7) store result n/a 5 y 5 = x ( n +2)h(0) + x ( n )h(2) + x ( n -2)h(4) + x ( n -4)h(6) generate output y ( n ) = y 4 + y 5 6 y 6 = x ( n +2)h(1) + x ( n )h(3) + x ( n -2)h(5) + x ( n -4)h(7) store result n/a 7 y 7 = x ( n +3)h(0) + x ( n +1)h(2) + x ( n -1)h(4) + x ( n -3)h(6) generate output y ( n ) = y 6 + y 7 altera corporation 7?15 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices flops corresponding to h (0), h (2), h (4) and h (6) are enabled. this produces the temporary output, y 1 , which is added to y 0 to produce the overall output, y ( n ). the following shows what the overall output, y ( n ), equals: this is identical to the output of the 8-tap filter shown in figure 7?2 . after cycle 1, this process is repeated at every cycle. figure 7?8. coefficient loading schedule in a tdm filter yn () y 0 y 1 + = yn () x0 () h0 () xn 1 ? () h1 () xn 2 ? () h2 () xn 3 ? () h3 () +++ = + x n 4 ? () h4 () xn 5 ? () h5 () xn 6 ? () h6 () xn 7 ? () h7 () +++ cycle 0 load h (1), h (3), h (5), h (7) cycle 1 load h (0), h (2), h (4), h (6) cycle 2 load h (1), h (3), h (5), h (7) cycle 3 load h (0), h (2), h (4), h (6) cycle 4 load h (1), h (3), h (5), h (7) 2x clock 1x clock 7?16 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters figure 7?9. tdm fir filter implementation note (1) note to figure 7?9 : (1) to increase the dsp block performance, inc lude the pipeline and output registers. see figure 7?3 on page 7?8 for details. if the tdm factor is more than 2, then a multiply-accumulator needs to be implemented. this multiply-accumulator can be implemented using the soft logic outside the dsp block if al l the multipliers of the dsp block are needed. alternatively, the multip ly-accumulator may be implemented inside the dsp block if all the multip liers of the dsp block are not needed. the accumulator needs to be zeroed at the start of each new sample input. the user also needs a way to store ad ditional sample in puts in memory. for example, consider a sample rate of r and tdm factor of 4. then, the filter output y ( n ) clock input (1x clock) 1x c l ock pll dq dq dq dq dq dq dq dq 2x clock x (n) x x dsp block data input ram / r o m 0 ram / r o m 1 ram / r o m 2 ram / rom 3 filt e r c o e ffi c i e nt s d q accumulator d q d q d q d q d q d q d q shift re g iste r altera corporation 7?17 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices user needs a way to accept this sample data and send it at a 4r rate to the input of the dsp block. one way to do this is using a first-in-first-out (fifo) memory with input clocked at ra te r and output clocked at rate 4r. the fifo may be implemented in the trimatrix memory. tdm filter implementation results table 7?8 shows the results of the implementation of an 18-bit 8-tap tdm fir filter as shown in figure 7?9 on page 7?16 . tdm filter design example download the tdm fir filter ( tdm_fir.zip ) design example from the design examples section of the altera web site at www.altera.com. polyphase fir interpolation filters an interpolation filter can be used to increase sample rate. an interpolation filter is efficiently implemented with a polyphase fir filter. dsp systems frequently use polyphas e filters because they simplify overall system design and also redu ce the number of computations per cycle required of the hardware. this section first describes interpolation filters and then how to implement them as polyphase filters in stratix and stratix gx devices. see the ?polyphase fir decimation filters? on page 7?24 section for a discussion of decimation filters. interpolation filter basics an interpolation filter increases the output sample rate by a factor of i through the insertion if i -1 zeros between input samples, a process known as zero padding. after the ze ro padding, the output samples in time domain are separated by ts / i = 1/( i f s ), where t s and f s are the sample period and sample frequency of the original signal, respectively. figure 7?10 shows the concept of signal interpolation. table 7?8. tdm filter implementation results part ep1s10f780 utilization lcell: 196/10570 (1 % ) dsp block 9-bit elements: 8/48 (17 % ) memory bits: 360/920448 (<1 % ) performance 240 mhz (1) note to ta b l e 7 ? 8 : (1) this refers to the performance of the ds p blocks. the input and output rate is 120 million samples per second (msps) , clocked in and out at 120 mhz. 7?18 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters inserting zeros between th e samples creates reflections of the original spectrum, thus, a low pass filter is needed to filter out the reflections. figure 7?10. block diagram repres entation of interpolation to see how interpolation filters work, consider the nyquist sampling theorem. this theorem states that the maximum frequency of the input to be sampled must be smaller than f s /2, where f s is the sampling frequency, to avoid alia sing. this frequency, f s /2, is also known as the nyquist frequency ( f n ). typically, before a signal is sampled using an analog to digital converter (adc), it needs to be low pass filtered using an analog anti-aliasing filter to prev ent aliasing. if the input frequency spectrum extends close to the nyquist freq uency, then the first alias is also close to the nyquist frequency. therefore, the low pass filter needs to be very sharp to reject this alias. a very sharp analog filter is hard to design and manufacture and could increase passband ripple, thereby compromising system performance. the solution is to increase the sampli ng rate of the adc, so that the new nyquist frequency is higher and the spacing between the desired signal and the alias is also higher. zero padding as described above increase the sample rate. this process also known as upsampling (oversampling) relaxes the roll off requirements of the anti-aliasing filter. consequently, a simpler filter achieves alias suppression . a simpler analog filter is easier to implement, does not compromise system performance, and is also easier to manufacture. similarly, the digital to analog conv erter (dac) typically interpolates the data before the digital to analog conv ersion. this relaxes the requirement on the analog low pass filter at the output of the dac. the interpolation filter does not need to run at the oversampled (upsampled) rate of f s i . this is because the extra sample points added are zeros, so they do not contribute to the output. figure 7?11 shows the time and frequency domain representation of interpolation for a specific case where the original signal spectrum is limited to 2 mhz and the interpolation factor ( i ) is 4. the nyquist frequency of the upsampled signal mus t be greater than 8 mhz, and is chosen to be 9 mhz for this example. i lpf input output sample rate f s sample rate i * f s altera corporation 7?19 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices figure 7?11. time & frequency domain represen tations of interpolation for i = 4 as an example, cd players use interpolation, where the nominal sample rate of audio input is 44.1 ki losamples per second. a typical implementation might have an interp olation (oversampling) factor of 4 generating 176.4 kilosamples per seco nd of oversampled data stream. polyphase interpolation filters a direct implementation of an in terpolation filter, as shown in figure 7?10 , imposes a high computational burden. for example, if the filter is 16 taps long and a multiplica tion takes one cycle, then the number of computations required per cycle is 16 i . depending on the interpolation factor ( i ), this number can be quite big and may not be achievable in hardware. a polyphas e implementation of the low pass filter can reduce the number of comput ations required per cycle, often by a large factor, as will be evident later in this section. the polyphase implementation ?spl its? the original filter into i polyphase filters whose impulse responses are defined by the following equation: h k n () hk ni + () = 7?20 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters where: k = 0,1, ?, i -1 n = 0,1, ?, p -1 p = l / i = length of polyphase filters l = length of the filter (selected to be a multiple of i ) i = interpolation factor h ( n ) = original filter impulse response this equation implies that the first polyphase filter, h 0 ( n ), has coefficients h (0), h ( i ), h (2 i ),..., h (( p -1) i ). the second polyphase filter, h 1 ( n ), has coefficients h (1), h (1+ i ), h (1+2 i ), ..., h (1+( p -1) i ). continuing in this way, the last polyphase filter, h i -1 ( n ) , has coefficients h( i-1 ), h (( i - 1) + n ), h (( i - 1) + 2 i ), ..., h (( i - 1) + ( p -1) i ). an example helps in understanding the polyphase implementation of interpolation. consider the polyphase representation of a 16-tap low pass filter with an interpolation factor of 4. thus, the output is given below: referring back to figure 7?11 on page 7?19 , the only nonzero samples of the input are x (0), x (4), x (8,) and x (12). the first output, y (0), only depends on h (0), h (4), h (8) and h (12) because x ( i ) is zero for i 0, 4, 8, 12. table 7?9 shows the coefficients required to generate output samples. table 7?9 shows that this filter operat ion can be represented by four parallel polyphase filters. this is shown in figure 7?12 . the outputs from the filters are multiplexed to generate the overall output. the multiplexer is controlled by a counter, which counts up modulo- i starting at 0 . it is illuminating to compare the comp utational requirements of the direct implementation versus po lyphase implementation of the low pass filter. in the direct implementation, the number of computations per cycle yn () hn ii ? () xi () i0 = 15 = table 7?9. decomposition of a 16-tap inter polating filter into four polyphase filters output sample coefficients require d polyphase filter impulse response y(0), y(4)... h(0), h(4), h(8), h(12) h 0 (n) y(1), y(5)... h(1), h(5), h(9), h(13) h 1 (n) y(2), y(6)... h(2), h(6), h(10), h(14) h 2 (n) y(3), y(7)... h(3), h(7), h(11), h(15) h 3 (n) altera corporation 7?21 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices required is 16 i = 16 4 = 64. in the polyphase implementation, the number of computations per cycle required is 4 4 = 16. this is because there are four polyphase filters, each with four taps. figure 7?12. polyphase representati on of i=4 interpolation filter polyphase interpolation filter implementation figure 7?13 shows the stratix or stratix gx implementation of the polyphase interpolation filter in figure 7?12 . the four polyphase filters share the same hardware, which is a 4-tap filter. one stratix or stratix gx dsp block can implement one 4-tap fi lter with 18-bit wide data and coefficients. a multiplexer can be used to load new coefficient values on every cycle of the 4 clock. stratix and stratix g x phase lock loops (plls) can generate the 4 clock. in the first cycle of the 4 clock, the user needs to load coefficients for polyphase filter h 0 ( n ); in the second cycle of the 4 i = 4 lpf with coefficients h (0), h (1), ... h (15) input x ( n ) output y ( n ) interpolation using a single low-pass filter interpolation using a polyphase filter polyphase filter with coefficients h (0), h (4), h (8), h (12) polyphase filter with coefficients h (1), h (5), h (9), h (13) polyphase filter with coefficients h (2), h (6), h (10), h (14) polyphase filter with coefficients h (3), h (7), h (11), h (15) output y ( n ) input x ( n ) y 1( n ) y 2( n ) y 3( n ) y 4( n ) modulo 4 up counter initialized at 0 4x clock 0 1 2 3 7?22 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters clock, the users needs to load coef ficients of the polyphase filter h 1 ( n ) and so on. table 7?10 summarizes the coefficient loading schedule. the output, y( n ), is clocked using the 4 clock. table 7?10. polyphase interpolation (i=4) filter coefficient loading schedule cycle of 4 clock coefficients to load corresponding ram/rom 1, 5,... h(0), h(4), h(8), h(12) 0, 1, 2, 3 2, 6,... h(1), h(5), h(9), h(13) 0, 1, 2, 3 3, 7,... h(2), h(6), h(10), h(14) 0, 1, 2, 3 4, 8,... h(3), h(7), h(11), h(15) 0, 1, 2, 3 altera corporation 7?23 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices figure 7?13. implementation of the poly phase interpolation filter (i=4) notes (1) , (2) , (3) notes to figure 7?13 : (1) the 1 clock feeds the input data shiftin register chain. (2) the 4 clock feeds the input registers for the filter coefficients and other option al registers in the dsp block. see note (3) . (3) to increase the dsp block performance, inc lude the pipeline, and ou tput registers. see figure 7?3 for the details. h ( 0 ) h ( 1 ) h ( 2 ) h ( 3 ) filter output y ( n ) note (2) clock input (1x clock) 1x clock pll dq dq dq dq dq dq dq dq 4x clock note (1) x (n) x x dsp block data input ram / r o m 0 ram / r o m 1 ram / r o m 2 ram / rom 3 filt e r c o e ffi c i e nt s 7?24 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters polyphase interpolation filt er implementation results table 7?11 shows the results of the polyphase interpolation filter implementation in a st ratix device shown in figure 7?13 . polyphase interpolation f ilter design example download the interpolation fir filter ( interpolation_fir.zip ) design example from the design examples se ction of the altera web site at www.altera.com. polyphase fir decimation filters a decimation filter can be used to decrease the sample rate. a decimation filter is efficiently implemented with a polyphase fir filter. dsp systems frequently use polyphase filters beca use they simplify overall system design and also reduce the number of computations per cycle required of the hardware. this section first describes decimation filters and then how to implement them as polyphase f ilters in stratix devices. see the ?polyphase fir interpolation filters? section for a discussion of interpolation filters. decimation filter basics a decimation filter decreases the output sample rate by a factor of d through keeping only every d -th input sample. consequently, the samples at the output of the deci mation filter are separated by d t s = d / f s , where t s and f s are the sample period and sample frequency of the original signal, respectively. figure 7?14 shows the concept of signal decimation. the signal needs to be low pass filtered before downsampling can begin in order to avoid the reflections of the original spectrum from being aliased back into the output signal. table 7?11. polyphase interpolation filter implementation results part ep1s10f780 utilization lcell: 3/10570 (<1 % ) dsp block 9-bit elements: 8/48 (17 % ) memory bits: 288/920448 (<1 % ) performance 240 mhz (1) note to ta b l e 7 ? 11 : (1) this refers to the performance of the ds p blocks, as well as the output clock rate. the input rate is 60 msps, clocked in at 60mhz. altera corporation 7?25 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices figure 7?14. block diagram repr esentation of decimation decimation filters reverse the effect of the interpolation filters. before the decimation process, a low pass filter is applied to the signal to attenuate noise and aliases present beyond th e nyquist frequency. the filtered signal is then applied to the decimati on filter, which processes every d-th input. therefore the values between samples d , d -1, d -2 etc. are ignored. this allows the filter to run m times slower than the input data rate. in a typical system, after the analog to digital conversion is complete, the data needs to be filtered to remove aliases inherent in the sampled data. further, at this point there is no need to continue to process this data at the higher sample (oversampled) rate. therefore, a decimation fir filter at the output of the adc lowers the data rate to a value that can be processed digitally. figure 7?15 shows a specific example where a signal spread over 8 mhz is decimated by a factor of 4 to 2 mhz. the nyquist frequency of the downsampled signal must be greater than 2 mhz, and is chosen to be 2.25 mhz in this example. d lpf input output sample rate f s sample rate f s /d 7?26 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters figure 7?15. time & frequency domain repr esentations of decimation for d=4 polyphase decimation filters figure 7?14 shows a direct implementation of a decimation filter, which imposes a high computational burden. fo r example, if the filter is 16 taps long and a multiplication takes one cycle, the number of computations required per cycle is 16 d . depending on the decimation factor ( d ), this number can be quite big and may not be achievable in hardware. a polyphase implementation of the low pass filter can reduce the number of computations required, often by a larg e ratio, as will be evident later in this section. the polyphase implementation ?spl its? the original filter into d polyphase filters with impulse responses defined by the following equation. h k n () hk nd + () = altera corporation 7?27 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices where: k = 0,1, ?, d -1 n = 0,1, ?, p -1 p = l / d = length of polyphase filters l is the length of the filter (selected to be a multiple of d ) d is the decimation factor h ( n ) is the original filter impulse response this equation implies that the first polyphase filter, h 0 ( n ) , has coefficients h (0), h ( d ), h (2 d )? h (( p -1) d ). the second polyphase filter, h 1 ( n ), has coefficients h (1), h (1+ d ), h (1+2 d ), ..., h (1+( p -1) d ). continuing in this way, the last polyphase filter, h d -1 ( n ) has coefficients h( d-1 ), h (( d - 1) + d ), h (( d - 1) + 2 d ), ..., h (( d - 1) + ( p -1) d ). an example helps in the understandin g of the polyphase implementation of decimation. consider the polyphase representation of a 16-tap low pass filter with a decimation fact or of 4. the output is given by: referring to figure 7?15 on page 7?26 , it is clear that the output, y( n ) is discarded for n 0, 4, 8, 12, hence the only values of y( n ) that need to be computed are y( 0 ) , y( 4 ) , y( 8 ) , y( 12 ) . table 7?12 shows which coefficients are required to generate the output samples. table 7?12 shows that the overall decimation filter operation can be represented by 4 parallel polyphase filters. figure 7?16 shows the polyphase representation of the decima tion filter. a demultiplexer at the input ensures that the in put is applied to only on e polyphase filter at a yn () hi () xnd i ? () i0 = 15 = table 7?12. decomposition of a 16-tap decimation filter into four polyphase filters output sample (1) coefficients required polyphas e filter impulse response y(0) 0 , y(4) 0 , . . . h(0), h(4), h(8), h(12) h 0 (n) y(0) 1 , y(4) 1 , . . . h(1), h(5), h(9), h(13) h 1 (n) y(0) 2 , y(4) 2 , . . . h(2), h(6), h(10), h(14) h 2 (n) y(0) 3 , y(4) 3 , . . . h(3), h(7), h(11), h(15) h 3 (n) note to table 7?12 : (1) the output sample is the sum of th e results from four polyphase filters: y ( n ) = y ( n ) 0 + y ( n ) 1 + y ( n ) 2 + y ( n ) 3. 7?28 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters time. the demultiplexer is controlled by a counter, which counts down modulo- d starting at 0 . the overall output is taken by adding the outputs of all the filters. the polyphase representation of the decimation filter also reduces the computational requirement. for the example in figure 7?16 , the direct implementation requires 16 d =16 4 = 64 computations per cycle, whereas the polyphase implem entation requires only 4 4 1 = 16 computations per cycle. this saving in computational complexity is quite significant and is often a very convin cing reason to use polyphase filters. figure 7?16. polyphase filter represent ation of a d=4 decimation filter d = 4 lpf with coefficients h (0), h (1), ... h (15) input x ( n ) output y ( n ) decimation using a single low-pass filter decimation using a polyphase filter polyphase filter with coefficients h (0), h (4), h (8), h (12) polyphase filter with coefficients h (1), h (5), h (9), h (13) polyphase filter with coefficients h (2), h (6), h (10), h (14) polyphase filter with coefficients h (3), h (7), h (11), h (15) output y ( n ) input x ( n ) modulo 4 down counter initialized at 0 4x clock 0 1 2 3 altera corporation 7?29 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices polyphase decimation filter implementation figure 7?17 shows the decimation polyphase filter example of figure 7?16 as it would fit into stratix or stratix gx dsp blocks. the coefficients of the polyphase filters n eed to be cycled using the schedule shown in table 7?13 . the output y(n ), is clocked using the 1 clock. table 7?13. coefficient loading schedule for polyphase decimation filter (d=4) cycle of 4 clock coefficients to load corresponding ram/rom 1, 5,... h(0), h(4), h(8), h(12) 0, 1, 2, 3 2, 6,... h(3), h(7), h(11), h(15) 0, 1, 2, 3 3, 7,... h(2), h(6), h(10), h(14) 0, 1, 2, 3 4, 8,... h(1), h(5), h(9), h(13) 0, 1, 2, 3 7?30 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters figure 7?17. implementation of the po lyphase decimation filter (d=4) notes (1) , (2) , (3) notes to figure 7?17 : (1) the 1 clock feeds the register after the accumulator block. (2) the 4 clock feeds the shift register for the data, the input regi sters for both the data and filter coefficients, the other optional registers in the dsp block (see note (3) ), and the accumulator block. (3) to increase the dsp block performance, inc lude the pipeline, and ou tput registers. see figure 7?3 on page 7?8 for the details. filter output y ( n ) note (2) clock input (1x clock) r om r om r o m r om 1x clock pll dq dq dq dq dq dq dq dq 4x clock note (1) dsp block filt e r c o e ffi c i e nt s x (n) x x d ata i n p u t d q d q d q d q d q d q d q d q d q d q d q d q d q d q altera corporation 7?31 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices polyphase decimation filter implementation results table 7?14 shows the results of the polyphase decimation filter implementation in a st ratix device shown in figure 7?17 . polyphase decimation filter design example download the decimation fir filter ( decimation_fir.zip ) design example from the design examples se ction of the altera web site at www.altera.com. complex fir filter a complex fir filter takes real and imaginary input sign als and performs the filtering operation with real an d imaginary filter coefficients. the output also consists of real and im aginary signals. therefore, a complex fir filter is similar to a regular fir filt er except for the fact that the input, output, and coefficients are all complex numbers. one example application of complex fi r filters is equalization. consider a phase shift keying (psk) system; a single complex channel can represent the i and q data channels. a fir filter with complex coefficients could then process both data cha nnels simultaneously. the filter coefficients are chosen in order to reverse the effects of intersymbol interference (isi) inherent in practical communication channels. this operation is called equalization. often, the filter is adaptive, i.e. the filter coefficients can be varied as desired, to optimize performance with varying channel characteristics. a complex variable fir filter is a cascade of complex multiplications followed by a complex addition. figure 7?18 shows a block diagram representation of a complex fir filter. to compute the overall output of the fir filter, it is first necessary to determine the output of each complex multiplier. this can be expressed as: table 7?14. polyphase decimation filter implementation results part ep1s10f780 utilization lcell: 168/10570 (1 % ) dsp block 9-bit elements: 8/48 (17 % ) memory bits: 300/920448(<1 % ) performance 240 mhz (1) note to table 7?14 : (1) this refers to the performance of the ds p blocks, as well as the input clock rate. the output rate is 60 msps (clocked out at 60mhz). 7?32 altera corporation stratix device handbook, volume 2 september 2004 finite impulse response (fir) filters where: x real is the real input signal x imag is the imaginary input signal h real is the real filter coefficients h imag is the imaginary filter coefficients y real is the real output signal y imag is the imaginary output signal in complex representa tion, this equals: the overall real channel output is ob tained by adding the real channel outputs of all the multip liers. similarly, the overall imaginary channel output is obtained by adding the imaginary channel outputs of all the multipliers. figure 7?18. complex fir filter block diagram complex fir filter implementation complex filters can be easily implemented in stratix devices with the dsp blocks configured in the two-multip liers adder mode. one dsp block can implement a 2-tap complex fir filter with 9-bit inputs, or a single tap complex fir filter with 18-bit inpu ts. dsp blocks can be cascaded to implement complex filters with more taps. 1 the two-multipliers ad der mode has two adders, each adding the outputs of two mult ipliers. one of the adders is configured as a subtractor. y real x real h real x imag h imag ? = y imag x real h imag h real x imag + = y real jy imag + x real jx imag + () h real jh imag + () = complex fir filter x real x imag y real y imag h real h imag altera corporation 7?33 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices f for more information on the different modes of the dsp blocks, see the dsp blocks in strati x & stratix gx devices chapter. figure 7?19 shows an example of a 2-tap co mplex fir filter design with 18-bit inputs. the real and the comp lex outputs of the dsp blocks are added externally to generate the overal l real and imaginary output. as in the case of basic, tdm, or polyphase fir filters, the coefficients may be loaded in series or parallel. figure 7?19. 2-tap 18-bit complex fir filter implementation dsp block configured as a subtractor h imag1 h real1 x imag1 x real1 out real1 = x real1 * h real1 - x imag1 * h imag1 out imag1 = x real1 * h imag1 + x imag1 * h real1 configured as a adder dsp block configured as a subtractor h imag2 h real2 x imag2 x real2 out real2 = x real2 * h real2 - x imag2 * h imag2 out imag2 = x real2 * h imag2 + x imag2 * h real2 configured as a adder overall real output overall imaginary output 7?34 altera corporation stratix device handbook, volume 2 september 2004 infinite impulse response (iir) filters infinite impulse response (iir) filters another class of digital filters are ii r filters. these are recursive filters where the current output is dependen t on previous outputs. in order to maintain stability in an iir filter, careful design consideration must be given, especially to the effects of word-length to avoid unbounded conditions. the following section discusses the general theory and applications behind iir filters. iir filter background the impulse response of an iir filter extends for an infinite amount of time because their output is based on feedback from previous outputs. the general expression for iir filters is: where a i and b i represent the coefficients in the feed-forward path and feedback path, respectively, and n represents the filter order. these coefficients determine where the poles and zeros of the iir filter lie. consequently, they also determine how the filter functions (i.e., cut-off frequencies, band pass, low pass, etc.). the feedback feature makes iir filter s useful in high data throughput applications that require low hardwa re usage. however, feedback also introduces complications and caution must be taken to make sure these filters are not exposed to situations in which they may become unstable. the complications include phase distorti on and finite word length effects, but these can be overcome by ensuring that the filter always operates within its intended range. figure 7?20 shows a direct form ii structure of an iir filter. yn () ai () xn i ? () i0 = n bi () yn i ? () i1 = n ? = altera corporation 7?35 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices figure 7?20. direct form ii st ructure of an iir filter the transfer function for an iir filter is: the numerator contains the zeros of the filter and the denominator contains the poles. the iir filter structure requires a multiplication followed by an accumulation. construc ting the filter directly from the transfer function shown above may result in finite word length limitations and make the filter potent iality unstable. this becomes more critical as the filter order increases, because it only has a finite number of bits to represent the output. to prev ent overflow or instability, the transfer function can be split into two or more terms representing several second order filters called biquads. these biquads can be individually scaled and cascaded, splitting the poles into multiples of two. for example, an iir filter having ten po les should be spli t into five biquad sections. doing this minimizes quan tization and recu rsive accumulation errors. x( n ) -b 1 a 1 z -1 z -1 z -1 -b 2 -b n y( n ) a 2 a n a 0 w( n ) hz () a i z i ? i0 = n 1b i z i ? i1 = n + ------------------------------ = 7?36 altera corporation stratix device handbook, volume 2 september 2004 infinite impulse response (iir) filters this cascaded structure rearranges the transfer function. this is shown in the equation below, where each produc t term is a second order iir filter. if n is odd, the last product term is a first order iir filter: figure 7?21 shows the cascaded structure. figure 7?21. cascaded iir filter basic iir filters in this section, the basic iir filter is implemented using cascaded second order blocks or biquads in the direct form ii structure. basic iir filter implementation multiplier blocks, adders and delay elements can implement a basic iir filter. the stratix architecture lends itself to iir filters because of its embedded dsp blocks, which can easily be configured to perform these operations. the altmult_add megafunction can be used to implement the multiplier-adder mode in the dsp blocks. figure 7?22 shows the implementation of an in dividual biquad using st ratix and stratix gx dsp blocks. hz () c a 0k a 1k z 1 ? a + 2k z 2 ? + 1b 1k z 1 ? b 2k z 2 ? ++ ---------------------------------------------------- k1 = n1 + () 2 ? ch k z () k1 = n1 + () 2 ? == x(n) y(n ) h (z) 1 h (z) k h (z) n c altera corporation 7?37 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices figure 7?22. iir filter biquad note (1) note to figure 7?22 : (1) unused ports are grayed out. 7?38 altera corporation stratix device handbook, volume 2 september 2004 infinite impulse response (iir) filters the first dsp block in figure 7?22 is configured in the two-multipliers adder mode, and the second dsp block is in the four-multipliers adder mode. for an 18-bit input to the iir fi lter, each biquad requires five multipliers and five adders (two ds p blocks). one of the adders is implemented using logic elements. ca scading several biquads together can implement more complex, higher order iir filters. it is possible to insert registers in between the biquad stages to improve the performance. figure 7?23 shows a 4 th order iir filter realized using two cascaded biquads in three dsp blocks. figure 7?23. two cascaded biquads x[n] first biquad second biquad y[n] two-multipliers adder mode dsp block 2 four-multipliers adder mode dsp block 3 four-multipliers adder mode dsp block 1 a 20 a 21 b 22 b 21 a 12 a 22 a 10 a 11 b 12 b 11 altera corporation 7?39 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices basic iir filter implementation results table 7?15 shows the results of implementing a 4 th order iir filter in a stratix device. basic iir filter design example download the 4 th order iir filter ( iir.zip ) design example from the design examples section of the altera web site at www.altera.com. butterworth iir filters butterworth filters are the most popular version of iir analog filters. these filters are also kn own as ?maximally flat? because they have no passband ripple. additionally, they have a monotonic response in both the stopband and the passband. butterworth filters trade-off roll off steepness for their no ripple char acteristic. the distinguishing butterworth filter feature is its poles are arranged in a uniquely symmetrical manner along a circle in the s -plane. the expression for the butterworth filter?s magnitude-squared function is as follows: where: c is the cut-off frequency n is the filter order the filter?s cutoff characteristics become sharper as n increases. if a substitution is made such that j = s , then the following equation is derived: table 7?15. 4 th order iir filter implementation results part ep1s10f780c5 utilization lcell: 102/10570(<1 % ) dsp block 9-bit elements: 24/48 (50 % ) memory bits: 0/920448(0 % ) performance 73 mhz latency 4 clock cycles h c j () 2 1 1 j j c ------ - ?? ?? 2n + ---------------------------- = 7?40 altera corporation stratix device handbook, volume 2 september 2004 infinite impulse response (iir) filters with poles at: for k =0,1,?,2 n -1 there are 2 n poles on the circle with a radius of c in the s -plane. these poles are evenly spaced at / n intervals along the circle. the poles chosen for the implementation of the filt er lie in the left half of the s -plane, because these generate a stable, causal filter. each of the impulse invariance, the bilinear, and matched z transforms can transform the laplace transform of the butterworth filter into the z - transform. impulse invariance transforms ta ke the inverse of the laplace transform to obtain the impuls e response, then perform a z -transform on the sampled impulse response. the impulse invariance method can cause some aliasing. the bilinear transform maps the entire j -axis in the s -plane to one revolution of the unit circle in the z -plane. this is the most popular method because it inherently eliminates aliasing. the matched z -transform maps the poles and the zeros of the filter directly from the s -plane to the z -plane. usually, these transforms are transparent to the user because seve ral tools, such as matlab, exist for determining the coefficients of the filter. the z -transform generates the coefficients much like in the basic iir filter discussed earlier. butterworth filter implementation for digital designs, cons ideration must be made to optimize the iir biquad structure so that it maps op timally into logic. because speed is often a critical requirement, the goal is to reduce the number of operations per biquad. it is possible to reduce the number of multipliers needed in each biquad to just two. h c s () h c s ? () 1 1 s j c ------ - ?? ?? 2n + ---------------------------- = s k 1 ? () 1 2n ------- j c () = c e j 2n ------- ?? ?? 2k n 1 ? + () = altera corporation 7?41 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices through the use of integer feedforward multiplies, which can be implemented by combining addition, shifting, and complimenting operations, a butterworth filter?s transfer function biquad can be optimized for logic synthesis. the most efficient transformation is that of an all pole filter. this is because ther e is a unique relationship between the feedforward integer coefficients of the filter represented as: as can be seen by this equation, the z -1 coefficient in the numerator (representing the feedforward path) is twice the other two operands ( z - 2 and 1). this is always the case in the transformation from the frequency to the digital domain. this represents the normalized response, which is faster and smaller to implement in ha rdware than real multipliers. it introduces a scaling factor as well, but this can be corrected at the end of the cascade chain through a single multiply. figure 7?24 shows how a butterworth filter biquad is implemented in a stratix or stratix gx device. hz () 12z 1 ? z 2 ? ++ 1b 1 z 1 ? b 2 z 2 ? ++ ------------------------------------------ - = 7?42 altera corporation stratix device handbook, volume 2 september 2004 infinite impulse response (iir) filters figure 7?24. butterworth filter biquad notes (1) , (2) notes to figure 7?24 : (1) unused ports are grayed out. (2) the z -1 coefficient is a multiple of the other coefficients ( z -2 and 1) in the feedforward path. this is implemented using a shift operation. w(n-1) w(n-2) b 1 b 2 w(n) w(n-1) y(n) x ( n ) dsp block w(n) dq d q altera corporation 7?43 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices the dsp block in figure 7?24 is configured in multiply and add mode. the three external adders are implemented in logic elements and therefore are not part of the dsp block. therefore, for an 18-bit input, each biquad requires half a dsp block and three logic element adders. the gain factor can be compensated for at the end of the filtering stage and is not shown in this simple example. more complex, higher order butterworth filters can be realized by cascading se veral biquads together, as in the iir example. figure 7?25 below shows a 4th order butterworth filter using two cascaded biquads in a single dsp block. 7?44 altera corporation stratix device handbook, volume 2 september 2004 infinite impulse response (iir) filters figure 7?25. cascaded butterworth biquads note (1) note to figure 7?25 : (1) the gain factor is compensated for at the end of the filtering stag e and is not shown in this figure. d q d q d q d q w 1 (n-1) b 11 w 1 (n-2) b 12 d q d q w 2 (n-1) b 21 w 2 (n-2) b 22 w 1 (n) w 1 (n-2) dsp block w 2 (n) d q d q w 2 (n-2) w 2 (n-1) y(n) x(n) w 1 (n-1) second biquad first biquad d q d q d q d q altera corporation 7?45 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices butterworth filter implementation results table 7?16 shows the results of implementing a 4 th order butterworth filter as shown in figure 7?25 . butterworth filter design example download the 4 th order butterworth filter ( butterworth.zip ) design example from the design examples se ction of the altera web site at www.altera.com. matrix manipulation dsp relies heavily on matrix manipula tion. the key idea is to transform the digital signals into a format that can then be manipulated mathematically. this section describes an example of matrix manipulation used in 2-d convolution filter, and its implem entation in a stratix device. background on matrix manipulation a matrix can represent all digital sign als. apart from the convenience of compact notation, matrix representati on also exploits the benefits of linear algebra. as with one-dimensional, discrete sequences, this advantage becomes more apparent wh en processing multi-dimensional signals. in image processing, ma trix manipulation is important because it requires analysis in the spatial do main. smoothing, trend reduction, and sharpening are examples of common image processing operations, which are performed by convolution. this can also be viewed as a digital filter operation with the matrix of filter coefficients forming a convolutional kernel, or mask. table 7?16. 4 th order butterworth filter implementation results part ep1s10f780c6 utilization lcell: 251/10570(2 % ) dsp block 9-bit elements: 16/48 (33 % ) memory bits: 0/920448 (0 % ) performance 80 mhz latency 4 clock cycles 7?46 altera corporation stratix device handbook, volume 2 september 2004 matrix manipulation two-dimensional filtering & video imaging fir filtering for video applications and image processing in general is used in many applications, including noise removal, image sharpening to feature extraction. for noise removal, the goal is to re duce the effects of undesirable, contaminative signals that have b een linearly added to the image. applying a low pass filter or smooth ing function flatte ns the image by reducing the rapid pixel-to-pixel variation in gray levels and, ultimately, removing noise. it also has a blurring effect usually used as a precursor for removing unwanted deta ils before extracting certain features from the image. image sharpening focuses on the fine details of the image and enhances sharp transitions between the pixels. th is acts as a high-pass filter that reduces broad features like the uniform background in an image and enhances compact features or details that have been blurred. feature extraction is a form of imag e analysis slightly different from image processing. the goal of image analysis in general is to extract information based on certain characte ristics from the image. this is a multiple step process that includes ed ge detection. the easiest form of edge detection is the derivative filter, using gradient operators. all of the operations above involve transformation of the input image. this can be presented as the convolution of the two-dimensional input image, x( m , n ) with the impulse response of the transform, f( k , l ) , resulting in y( m , n ) which is the output image. the f( k , l ) function refers to th e matrix of filter coefficients. because the matrix operation is analogous to a filt er operation, the matrix itself is considered the impulse response of th e filter. depending on the type of operation, the choice of the convolutional kernel or mask, f( k , l ) is different. figure 7?26 shows an example of convolving a 3 3 mask with a larger image. ym n , () fk l , () xm n , () ? = ym n , () fk l , () xm k n l ? , ? () ln ? = n kn ? = n = altera corporation 7?47 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices figure 7?26. convolution using a 3 3 kernel the output pixel value, y( m , n ) depends on the surrounding pixel values in the input image, as well as the filter weights: to complete the transformation, the ke rnel slides across the entire image. for pixels on the edge of the image, the convolution operation does not have a complete set of input data. to work around this problem, the pixels on the edge can be left unchanged. in some cases, it is acceptable to have an output image of reduced size. alte rnatively, the matrix effect can be applied to edge pixels as if they are surrounded on the ?empty? side by ym n , () w 1 xm 1 n 1 ? , ? () w 2 xm 1 n , ? () w 3 xm 1 n 1 + , ? () ++ = + w 4 xm n 1 ? , () w 5 xm n , () w 6 xm n 1 + , () ++ + w 7 xm 1 + n1 ? , () w 8 xm 1 n , + () w 9 xm 1 n 1 + , + () ++ 7?48 altera corporation stratix device handbook, volume 2 september 2004 matrix manipulation black pixels, that is pixels with value zero. this is similar to padding the edges of the input image ma trix with zeros and is referred to as the free boundary condition. this is shown in figure 7?27 . figure 7?27. using free boundary condition for edge pixels convolution implementation this design example shows a 3 3 2-d fir filter that takes in an 8 8 input image with gray pi xel values ranging from 0-255 (8-bit). data is fed in serially starting from the top left pixel, moving horizontally on a row- by-row basis. next the data is stored in three separate ram blocks in the buffering stage. each m512 memory bloc k represents a line of the image, and this is cycled through. for a 32 32 input image, the design needs m4k memory blocks. for larger images (640 480), this can be extended to m-ram blocks or other buffering schemes. the control logic block provides the ram control signals to in terleave the data across all three x ( x x m + 1 , n + 1 ) x ( x x m + 1 , n ) x ( x x m , n + 1 ) 0 x ( x x 3 x 3 kernel slides across ima g e 0 0 0 0 image boundar y ima g e image boundary altera corporation 7?49 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices ram blocks. the 9-bit signed filter coeffi cients feed directly into the filter block. as the data is shifted out from the ram blocks, the multiplexer block checks for edge pixels and us es the free boundary condition. figure 7?28 shows a top-level diagram of the design. figure 7?28. block diagram on implementation of 3 3 convolutional fi lter for an 8 8 pixel input image the 3 3 filter block implements the nine multiply-add operations in parallel using two dsp blocks. one dsp block can implement eight of these multipliers. the second dsp bl ock implements the ninth multiplier. the first dsp block is in the four-mul tipliers adder mode, and the second is in simple multiplier mode. in ad dition to the two dsp blocks, an external adder is required to sum the output of all nine multipliers. figure 7?29 shows this implementation. 7?50 altera corporation stratix device handbook, volume 2 september 2004 matrix manipulation figure 7?29. implementation of 3 3 convolutional filter block dsp block in four-multipliers adder mode (9-bit) le implemented adder dsp block in sim p le multi p lier mode ( 8-bit ) w 9 x ( m + 1, n + 1) w 8 x ( m + 1, n ) w 7 x ( m + 1, n - 1) w 6 x ( m , n + 1) w 5 x ( m , n ) w 4 x ( m , n - 1) w 3 x ( m - 1, n + 1) w 2 x ( m - 1, n ) w 1 x ( m - 1, n - 1) y ( m , n ) note: unused multipliers and adders grayed out. these multipliers can be used by other functions. altera corporation 7?51 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices in cases where a symmetric 2-d filter is used, pixels sharing the same filter coefficients from three separate line-stores a, b, and c can be added together prior to the multiplication op eration. this reduces the number of multipliers used. referring to figure 7?30 , w 1 , w 2 , and w 3 are the filter coefficients. figure 7?31 shows the implementati on of this circular symmetric filter. figure 7?30. symmetric 3 3 kernel figure 7?31. details on implem entation of symmetric 3 3 convolution filter block dsp block - four multipliers adder mode (9-bit) logic elements g n d w 3 w w w 2 w w w 1 y y ( m , n ) g n d a b c note: unused multipliers and adders grayed out. these multipliers can be used by other functions. 7?52 altera corporation stratix device handbook, volume 2 september 2004 discrete cosine transform (dct) convolution implementation results table 7?17 shows the results of the 3 3 2-d fir filter implementation in figure 7?28 . the design requires the input to be an 8 8 image, with 8-bit input data and 9-bit filter coefficient width. the output is an image of the same size. convolution design example download the 3 3 2-d convolutional filter ( two_d_fir.zip ) design example from the design examples se ction of the altera web site at www.altera.com. discrete cosine transform (dct) the discrete cosine transform (dct) is widely used in video and audio compression, for example in jpeg, mpeg video, and mpeg audio. it is a form of transform coding, which is the preferred method for compression techniques. images tend to compact th eir energy in the frequency domain making compression in the frequency domain much more effective. this is an important element in compressing data, where the goal is to have a high data compression rate without significant degradation in the image quality. dct background similar to the discrete four ier transform (dft), the dct is a function that maps the input signal or image from the spatial to the frequency domain. it transforms the input into a linear combination of weighted basis functions. these basis functions ar e the frequency components of the input data. table 7?17. 3 3 2-d convolution filter implementation results part ep1s10f780 utilization lcell: 372/10570 (3 % ) dsp block 9-bit elements: 9/48 (18 % ) memory bits: 768/920448 (<1 % ) performance 226 mhz latency 15 clock cycles altera corporation 7?53 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices for 1-d with input data x( n ) of size n , the dct coefficients y( k ) are: for 0 k n ?1 where: for k = 0 for 1 k n ?1 for 2-d with input data x( m , n ) of size n n , the dct coefficients for the output image, y( p , q ) are: where: for p = 0 for q = 0 for 1 p n ?1 for 1 q n ?1 2-d dct algorithm the 2-d dct can be thought of as an extended 1-d dct applied twice; once in the x direction and again in the y direction. because the 2-d dct is a separable transform, it is possible to calculate it using efficient 1-d algorithms. figure 7?32 illustrates the concept of a separable transform. yk () k () 2 ----------- xn () 2n 1 + () k 2n -------------------------- - ?? ?? cos n0 = n1 ? = k () 1 n --- - = k () 2 n --- - = yp q , () p () q () 2 ---------------------- - xm n , () 2m 1 + () p 2n ---------------------------- - ?? ?? cos 2n 1 + () q 2n -------------------------- - ?? ?? cos n0 = n1 ? m0 = n1 ? = p () 1 n --- - = q () 1 n --- - = p () 2 n --- - = q () 2 n --- - = 7?54 altera corporation stratix device handbook, volume 2 september 2004 discrete cosine transform (dct) figure 7?32. a 2-d dct is a separable transform this section uses a standard algorithm proposed in [1]. figure 7?33 shows the flow graph for the algorith m. this is similar to the butterfly computation of the fast fourier transform (fft). similar to the fft algorithms, the dct algori thm reduces the complexity of the calculation by decomposing the computation into successively smaller dct components. the even coefficients ( y 0 , y 2 , y 4 , y 6 ) are calculated in the upper half and the odd coefficients ( y 1 , y 3 , y 5 , y 7 ) in the lower half. as a result of the decomposition, th e output is reordered as well. figure 7?33. implementing an n=8 fast dct stage 1 stage 4 stage 3 stage 2 x 0 x 7 x 6 x 5 x 4 x 3 x 2 x 1 y 0 y 7 y 5 y 3 y 1 y 6 y 2 y 4 y k = c m1 s 3 1 + c m2 s 3 2 + ... + c mn s 3 n c x = cos ( 16 x ) multiplied by -1 b a sum a and b multiply-addition block c m1 y k s3 2 s3 1 c m2 c mn . . . . . . . s3 n c 7 c 5 c 3 c 1 c 6 c 2 c 6 -c 2 c 4 -c 5 -c 1 -c 7 c 3 c 3 c 7 -c 1 c 5 -c 1 c 3 -c 5 c 7 stage 3 output (s3) matrix coefficent (c mn ) where altera corporation 7?55 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices the following defines in matrix format, the 8-point 1-d dct of figure 7?33 : where: [ x ] is the 1 8 input matrix y 1d x add 1 add 2 add 3 c = add 1 10000001 01000010 00100100 00011000 0001 1 ? 000 00100 1 ? 00 010000 1 ? 0 1000000 1 ? = add 2 10010000 01100000 01 1 ? 00000 100 1 ? 0000 00001000 00000100 00000010 00000001 = add 3 11000000 11 ? 000000 00100000 00010000 00001000 00000100 00000010 00000001 = 7?56 altera corporation stratix device handbook, volume 2 september 2004 discrete cosine transform (dct) all of the additions in stages 1, 2 and 3 of figure 7?32 appear in symmetric add and subtract pairs. the entire first stage is simply four such pairs in a very typical cross-over pattern. this pattern is repeated in stages 2 and 3. multiplication operations are confined to stage 4 in the algorithm. this implemen tation is shown in more detail in the next section. dct implementation in taking advantage of the separable transform property of the dct, the implementation can be divided into se parate stages; row processing and column processing. however, some data restructuring is necessary before applying the column processi ng stage to the results from the row processing stage. the data buffering stage must transpose the data first. figure 7?34 shows the different stages. figure 7?34. three separate stages in implementing the 2-d dct because the row processing and column processing blocks share the same 1-d 8-point dct algorithm, the hard ware implementation shows this block as being shared. th e dct algorithm requires a serial-to-parallel conversion block at the input because it works on blocks of eight data c 10000000 0c 4 000000 00c 6 c ? 2 0000 00c 2 c 6 0000 0000c 7 c ? 5 c 3 c ? 1 0000c 5 c ? 1 c 7 c 3 0000c 3 c ? 7 c ? 1 c ? 5 0000c 1 c 3 c 5 c 7 = c x x 16 ----- - cos = row processing column processing transpose matrix altera corporation 7?57 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices points in parallel. there is also a parallel-to-serial conversion block at the output because the column processing stage gene rates the output image column-by-column. in order to have th e output in the same order as the input (i.e., row-by-row), this conversi on is necessary. appropriate scaling needs to be applied to the completed tr ansform but this can be combined with the quantization stage wh ich often follows a dct [1]. figure 7?35 shows a top-level block diagram of this design. figure 7?35. block diagram on serial implementation of 2-d dct the implementation of the 1-d dct block is based on the algorithm shown in figure 7?33 . the simple addition and subtraction operations in stages 1, 2 and 3 are implemented using logic cells. the multiply and multiply-addition operat ions in stage 4 are implemented using dsp blocks in the stratix device in the simple multiplier mode, two-multiplier adder mode, and the four-multiplier adder mode. an example of the multiply-addition bl ock is shown in figure 7?36 . 7?58 altera corporation stratix device handbook, volume 2 september 2004 discrete cosine transform (dct) figure 7?36. details on the im plementation of the mult iply-addition operation in stage 4 of the 1-d dct algorithm note to figure 7?36 : (1) referring to figure 7?33 . s3 n is an output from stage 3 of the dct and c mn is a matrix coefficient. c x =cos (x /16). dct implementation results table 7?18 shows the results of implem enting a 2-d dct with 18-bit precision, as shown in figure 7?35 . dct design example download the 2-d convolutional filter ( d_dct.zip ) design example from the design examples section of the altera web site at www.altera.com. table 7?18. 2-d dct impl ementation results part ep1s20f780 utilization lcell: 1717/18460 (9 % ) dsp block 9-bit element: 18/80 (22 % ) memory bits: 2816/1669248 (<1 % ) performance 165 mhz latency 80 clock cycles dsp block - four-multipliers adder mode (18-bit) c m1 c m2 c m3 c m4 s3 1 y k s3 4 s3 3 s3 2 altera corporation 7?59 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices arithmetic functions arithmetic functions, such as trig onometric functions, including sine, cosine, magnitude and phase calculat ion, are important dsp elements. this section discusses the implementa tion of a simple vector magnitude function in a stratix device. background complex numbers can be expressed in two parts: real and imaginary. where: a is the real part b is the imaginary part j 2 = ?1 in a two-dimensional plane, a vector ( a , b ) with reference to the origin (0,0) can also be represented as a complex number. in essence, the x-axis represents the real part, and the y-ax is represents the imaginary part (see figure 7?37 ). figure 7?37. magnitude of vector (a,b) complex numbers can be converted to phase and amplitude or magnitude representation, using a cartesian-to-polar coordinate conversion. for a vector ( a , b ), the phase and magnitude representation is the following: zajb + = 7?60 altera corporation stratix device handbook, volume 2 september 2004 arithmetic functions magnitude phase angle = tan -1 ( b / a ) this conversion is useful in different applications, such as position control and position monitoring in robo tics. it is also important to have these transformations at very hi gh speeds to accommodate real-time processing. arithmetic function implementation a common approach to implementing th ese arithmetic functions is using the coordinate rotation digital computer (cordic) algorithm. the cordic algorithm calculat es the trigonometric func tions of sine, cosine, magnitude, and phase using an iterative process. it is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of 2. using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. in stratix devices, it is possible to calculate some of these arithmetic functions directly, without having to implement the cordic algorithm. this section describes a design example that calculates the magnitude of a 9-bit signed vector ( a , b ) using a pipelined version of the square root function available at the altera ip megastore. to calculate the sum of the squares of the input ( a 2 + b 2 ), configure the dsp block in the two- multipliers adder mode. the square root function is implemented using an iterative algorithm similar to the lo ng division operation. the binary numbers are paired off, and subtract ed by a trial number. depending on if the remainder is positive or nega tive, each bit of the square root is determined and the process is repeated . this square root function does not require memory and is implemented in logic cells only. in this example, the input bit precision ( in_prec ) feeding into the square root macro is set to twenty, and the output precision ( out_prec ) is set to ten. the number of precision bits is parameterizable. also, there is a third parameter, pipeline , which controls the architecture of the square root macro. if this parameter is set to yes , it includes pipeline stages in the square root macro. if set to no , the square root macro becomes a single- cycled combinatorial function. figure 7?38 shows the implementation the magnitude design. ma 2 b 2 + = altera corporation 7?61 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices figure 7?38. implementing the vector magnitude function dsp block - two multipliers adder mode (9-bit) a b note: unused multipliers and adders grayed out. le implemented square root function 7?62 altera corporation stratix device handbook, volume 2 september 2004 conclusion arithmetic function implementation results table 7?19 shows the results of the implementation shown in figure 7?38 with the pipeline parameter set to yes . table 7?20 shows the results of the implementation shown in figure 7?38 with the pipeline parameter set to no . arithmetic function design example download the vector magnitude function ( magnitude.zip ) design example from the design examples se ction of the altera web site at www.altera.com. conclusion the dsp blocks in stratix and strati x gx devices are optimized to support dsp functions requiring high data throughput, such as fir filters, iir filters and the dct. the dsp blocks are flexible and configurable in different operation modes based on the application?s needs. the trimatrix memory provides the data storage capability often needed in dsp applications. the dsp blocks and trimatrix memory in stratix and stratix gx devices offer performance and flexibility that translates to higher performance dsp functions. table 7?19. vector magnitude func tion implementation results (pipeline=yes) part ep1s10f780 utilization lcell: 497/10570 (4 % ) dsp block 9-bit elements: 2/48 (4 % ) memory bits: 0/920448 (0 % ) performance 194 mhz latency 15 clock cycles table 7?20. vector magnitude func tion implementation results (pipeline=no) part ep1s10f780 utilization lcell: 244/10570 (2 % ) dsp block 9-bit elements: 2/48 (4 % ) memory bits: 0/920448 (0 % ) performance 30 mhz latency 3 clock cycles altera corporation 7?63 september 2004 stratix device handbook, volume 2 implementing high performance dsp functions in stratix & stratix gx devices references see the following for more information: optimal dct for hardware implementation m. langhammer. proceedings of inte rnational conference on signal processing applications & tech nology (icspat) '95, october 1995 digital signal processi ng: principles, algori thms, and applications john g. proakis, dimitris g. manolakis. prentice hall hardware implementation of multirate digital filters tony san. communication systems design, april 2000 an 73: implementing fir filters in flex devices efficient logic synthesis techniques for iir filters m.langhammer. proceedings of international conference on signal processing applications & tech nology (icspat) '95, october 1995 7?64 altera corporation stratix device handbook, volume 2 september 2004 references altera corporation section v?1 section v. ip & design considerations this section provides documentation on some of the ip functions offered by altera ? for stratix ? devices. (also see the intellectual property section of the altera web site for a complete offering of ip cores for stratix devices.) the last chapter details design considerations for migrating from the apex ? architecture. this section contains the following chapters: chapter 8, implementing 10-gigabit ethernet using stratix & stratix gx devices chapter 9, implementing sfi-4 in stratix & stratix gx devices chapter 10, transitioning apex designs to stratix & stratix gx devices revision history the table below shows th e revision history for chapters 8 through 10 . chapter date/version changes made 8 july 2005, v2.0 updated stratix gx device information. september 2004, v1.2 table 8?2 on page 8?10 : updated table, deleted note 1, and updated note 2. updated table 8?4 on page 8?12 . november 2003, v1.1 removed support for series and parallel on-chip termination. april 2003, v1.0 no new changes in stratix device handbook v2.0. 9 july 2005, v2.0 updated stratix gx device information. september 2004, v1.1 table 9?2 on page 9?9 : updated table, deleted note 1, and updated note 2. updated table 9?4 on page 9?10 . april 2003, v1.0 no new changes in stratix device handbook v2.0. section v?2 altera corporation ip & design considerations stratix device handbook, volume 2 10 july 2005, v3.0 updated stratix gx device information. september 2004, v2.1 updated table 10?9 on page 10?26 . april 2004, v2.0 synchronous occurrences renamed pipelined. asynchronous occurrences renamed flow-through. november 2003, v1.2 removed support for series and parallel on-chip termination. october 2003, v1.1 updated table 10?6 . april 2003, v1.0 no new changes in stratix device handbook v2.0. chapter date/version changes made altera corporation 8?1 july 2005 8. implementing 10-gigabit ethernet using stratix & stratix gx devices introduction ethernet has evolved to meet ever-i ncreasing bandwidth demands and is the most prevalent local-area netw ork (lan) communications protocol. 10-gigabit ethernet extends that protocol to higher bandwidth for future high-speed applications. the accelerated growth of network traffic and the resulting increase in bandwidth requirements is driving service providers and enterprise network arch itects towards high-speed network solutions. potential applications fo r 10-gigabit ethernet include private campus or lan backbone s, high-speed access links between service providers and enterprises, and aggregation and transport in metropolitan area networks (mans). the i/o features of stratix ? and stratix gx devices enable support for 10- gigabit ethernet, supporting 10-gigabi t 16-bit interface (xsbi) and 10- gigabit medium independent interface (xgmii). stratix gx devices can additionally support th e 10-gigabit attachment unit interface (xaui) using the embedded 3. 125-gbps transceivers. you can find more information on xaui support in section ii, stratix gx transceiver user guide , of the stratix gx device handbook , volume 1 . this chapter discusses the following topics: fundamentals of 10-gigabit ethernet description and implementation of xsbi description and implementation of xgmii description of xaui i/o characteristics of xsbi, xgmii, and xaui related links 10-gigabit ethernet alliance at www.10gea.org the stratix device family data sheet section of the stratix device handbook, volume 1 and the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 the high-speed differential i/o interfaces in stratix devices chapter 10-gigabit ethernet ethernet speed has increased to keep pace with demand, initially to 10 megabits per second (mbps), later to 100 mbps, and recently to 1 gigabit per second (gbps). ethe rnet is the dominant network technology in lans, and with the advent of 10-gigabit ethernet, it is entering the man and wide area network (wan) markets. s52010-2.0 8?2 altera corporation stratix device handbook, volume 2 july 2005 10-gigabit ethernet the purpose of the 10-gigabit ethernet proposed standard is to extend the operating speed to 10 gbps defi ned by protocol ieee 802.3 and include wan applications. these additions provide a significant increase in bandwidth while maintaining maximum compatibility with current ieee 802.3 interfaces. since its inception in march 1999, the 10-gigabit ethernet task force has been working on the ieee 802.3ae st andard. some of the information in the following sections is derived from clauses 46, 47, 49, and 51 of the ieee draft p802.3ae/d3.1 document. a fully ratified standard is expected in the first half of 2002. figure 8?1 shows the relationship of 10-gigabit ethernet to the open systems interconnection (osi) protocol stack. figure 8?1. 10-gigabit ethernet protocol in relation to osi protocol stack notes to figure 8?1 : (1) llc: logical link controller (2) mac: media access controller (3) pcs: physical coding sublayer (4) phy: physical layer (5) pma: physical medium attachment (6) pmd: physical medium dependent (7) mdi: medium dependent interface application presentation session transport network data link physical higher layers llc (1) mac (2) reconciliation pcs (3) pma ( 5 ) pmd ( 6 ) medium xgmii xsbi mdi (7) phy (4 ) osi reference model layers altera corporation 8?3 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices the ethernet phy (layer 1 of the os i model) connects the media (optical or copper) to the mac (layer 2). the ethernet architecture further divides the phy (layer 1) into a pmd sublay er, a pma sublayer, and a pcs. for example, optical transceivers are pm d sublayers. the pma converts the data between the pmd sublayer and the pcs sublayer. the pcs is made up of coding (e.g., 8b/10b, 64b/66 b) and serializer or multiplexing functions. figure 8?2 shows the components of 10-gigabit ethernet and how altera implements cert ain blocks and interfaces. 10-gigabit ethernet has three different implementations for the phy: 10gbase-x, 10gbase-r, and 10gbase-w. the 10gbase-x implementation is a phy that suppo rts the xaui interface. the xaui interface used in conjunction with the xgmii extender sublayer (xgxs) allows more separation in distance between the mac and phy. 10gbase-x pcs uses four lanes of 8b/10b coded data at a rate of 3.125 gbps. 10gbase-x is a wide wave division multiplexing (wwdm) lan phy. 10gbase-r and 10gbase-w are serial lan phys and serial wan phys, respectively. unlike 10gbase-x, 10gbase-r and 10gbase-w implementation s have a xsbi interface and are described in more detail in the following section. 8?4 altera corporation stratix device handbook, volume 2 july 2005 10-gigabit ethernet figure 8?2. 10-gigabit et hernet block diagram notes to figure 8?2 : (1) the reconciliation sublayer (rs) interfaces the se rial mac data stream and the parallel data of xgmii. (2) the xgmii extender sublayer (xgxs) extends the distance of xgmii when used with xuai and provides the data conversion between xgmii and xaui. (3) the wan interface sublayer (wis) implements the oc-192 fr aming and scrambling functions. pcs pma pcs pma wis (3) 10gbase-r 10gbase-w xgmii (32 bits at 156.25 mbps ddr 1.5-v hstl) mac rs (1) xgxs (2) 8b/10b xaui (4 bits at 3.125 gbps pcml) xgmii (32 bits at 156.25 mbps ddr 1.5-v hstl) 8b/10b phy mdi 10gbase-x 64b/66b 8b/10b xsbi (16 bits at 622.08 mbps lvds) 64b/66b oc-192 framing interface directly covered in this application note interface indirectly covered in this application note can be implemented in altera plds xgxs pcs mdi xsbi (16 bits at 644.5 mbps lvds) pmd pmd pma pmd altera corporation 8?5 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices interfaces the following sections discuss xsbi, pcs, xgmii, and xaui. xsbi one of the blocks of 10-gigabit ethernet is the xsbi interface. xsbi is the interface between the pcs and the pma sublayers of the phy layer of the osi model. xsbi supports two types of phy layers, lan phy and wan phy. the lan phy is part of 10gbase-r, and supports existing gigabit ethernet applications at te n times the bandwidth. the wan phy is part of 10gbase-w, and supports connections to existing and future installations of sonet/sdh circuit-switched access equipment. 10gbase-r is a physical layer implem entation that is comprised of the pcs sublayer, the pma, and the pmd. 10gbase-r is based upon 64b/66b data coding. 10gbase-w is a phy layer implementation that is comprised of the pcs sublayer, the wan interface sublayer (wis), the pma, and the pmd. 10gbase-w is based on sts-192c/sdh vc-4-64c encapsulation of 64b/66b encoded data. figure 8?3 shows the construction of these two phy layers. figure 8?3. xsbi interface for the two phy layers pcs pma pmd medium pcs pma pmd medium wis xsbi mdi 10gbase-r 10gbase-w phy 8?6 altera corporation stratix device handbook, volume 2 july 2005 interfaces functional description xsbi uses 16-bit lvds data to inte rface between the pcs and the pma sublayer. figure 8?4 shows xsbi between these two sublayers. figure 8?4. xsbi functional block diagram on the transmitter side , the transmit data ( tx_d[15..0] ) is output by the pcs and input at the pma using the transmitter clock ( pma_txclk ), which is derived from the pma source clock ( pma_txclk_src ). the pma source clock is generated from the pma with its reference clock ( refclk ). on the receiver side, the receiver data ( rx_d[15..0] ) is output by the pma and input at the pcs using the pma-generated receiver clock ( pma_rxclk ). the sync_err optional signal is sent to the pcs by the pma if the pma fails to reco ver the clock from the serial data stream. the ratios for these two clocks and da ta are dependent on the type of phy used. table 8?1 shows the rates for both phy types. table 8?1. xsbi clock & data rates for wan & lan phy parameter wan phy lan phy unit tx_d[15..0] 622.08 644.53125 mbps pma_txclk 622.08 644.53125 mhz pma_txclk_src 622.08 644.53125 mhz rx_d[15..0] 622.08 644.53125 mbps pma_rxclk 622.08 644.53125 mhz tx_d[15..0] transmitter pma_txclk_src rx_d[15..0] pma_rxclk sync_err (optional) pma_txclk refclk pcs pcs pma pma receiver transmitter receiver altera corporation 8?7 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices implementation the 16-bit full duplex lvds implementation of xsbi in stratix devices is shown in figure 8?5 . the source-synchronous i/o implemented in stratix gx devices optionally includes dynamic phase alignment (dpa). dpa automatically and continuously tracks fluctuations caused by system variations and self-adjusts to eliminate the phase skew between the multiplied clock and the serial data, allowing for data rates of 1 gbps. in non dpa mode the i/o behaves similarly to that of the stratix i/o. this document assumes that dpa is disabled. however, it is simple to implement the same system with dpa enabled to take advantage of its features. for more information on dpa, see the stratix gx transceivers chapter in the stratix gx device handbook , volume 1 . figure 8?5. stratix & stratix gx device xsbi implementation transmitter serdes receiver serdes 1 8 8 180? stratix & stratix gx pcs data data transmitter receiver pma tx_d[15..0] pma_txclk pma_txclk_src pma_rxclk rx_d[15..0] phase shift receiver transmitter pll1 pll2 stratix & stratix gx lo g ic array 8?8 altera corporation stratix device handbook, volume 2 july 2005 interfaces the transmit serializer/deserialize r (serdes) clock comes from the transmitter clock source ( pma_txclk_src ). the receiver serdes clock comes from the pma receiver recovered clock ( pma_rxclk ). figure 8?6 shows the transmitter output of the xsbi core. data transmitted from the pcs to the pma starts at the core of the stratix or stratix gx device and travels to the stratix or stratix gx transmitter serdes block. the transm itter serdes block converts the parallel data to serial data for 16 individual channels ( tx_d[15..0] ). the pma source clock ( pma_txclk_src ) is used to clock out the signal data. pma_txclk is generated from the same ph ase-locked loop (pll) as the data, and it travels to the pma at the same rate as the data. by using one of the data channels in the middle of the bus as the clock (in this case, the eighth channel ch8), the clock-to-data skew improves. figure 8?6. stratix & stra tix gx device xsbi tr ansmitter impl ementation figure 8?7 shows the receiver input of the xsbi core. from the receiver side, data ( rx_d[15..0] ) comes from the pma to the stratix or stratix gx receiver serdes block al ong with the pma receiver clock ( pma_rxclk ). the pma receiver clock is us ed to convert the serial data to parallel data. the phase shift or inversion on the pma receiver clock is needed to capture the receiver data. tx_d[0] stratix & stratix gx lo g ic array fast pll w = 1 j = 4 or 8 4 or 8 stratix & stratix gx serdes w ch0 ch16 pma transmitter tx_d[15] pma_txclk_src stratix & stratix gx pcs transmitter j 622 mhz 622 mhz 622 mbps ch9 ch7 parallel re g ister parallel-to-serial re g ister 4 or 8 ch8 tx_d[7] pma_txclk tx_d[8] altera corporation 8?9 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices stratix and stratix gx devices contain up to eight fast plls. these plls provide high-speed outputs for high-speed differential i/o support as well as general- purpose clocking wi th multiplication and phase shifting. the fast pll incorporates this 180 ph ase shift. the stratix and stratix gx device?s data realignment feature enables you to save more logic elements (les). this fe ature provides a byte-alignment capability, which is embedded inside the serdes. the data realignment circuitry can correct for bit misalignment s by slipping data bits. f for more information about fast plls, see the stratix device family data sheet section of the stratix device handbook, volume 1 or the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 . figure 8?7. stratix & stra tix gx device xsbi receiver implementation rx_d[0] stratix & stratix gx lo g ic array fast pll w = 1 j = 4 or 8 4 or 8 stratix & stratix gx serdes w ch0 ch15 pma receiver rx_d[15] pma_rxclk_src stratix & stratix gx pcs receiver j 622 mhz 622 mhz 622 mbps parallel re g ister parallel-to-serial re g ister 4 or 8 8?10 altera corporation stratix device handbook, volume 2 july 2005 interfaces with this xsbi transmitter and receiv er block implementation, each xsbi core requires two fast plls. the po tential number of xsbi cores per device corresponds to the number of fast plls each stratix or stratix gx device contains. tables 8?2 and 8?3 show the number of lvds channels, the number of fast plls, and the nu mber of xsbi cores that can be supported for each stratix or stratix gx device. table 8?2. stratix device xsbi core support stratix device number of lvds channels (receive/transmit) (1) number of fast plls number of xsbi interfaces (maximum) ep1s10 44/44 4 2 ep1s20 66/66 4 2 ep1s25 78/78 4 2 ep1s30 82/82 8 4 ep1s40 90/90 8 4 ep1s60 116/116 8 4 ep1s80 152/156 8 4 note to ta b l e 8 ? 2 : (1) the lvds channels can go up to 840 mbps for flip-chip packages and up to 624 mbps for wire-bond packages. this number includes both high speed and low speed channels. the high speed lvds channels can go up to 840 mbps. the low speed lvds channels can go up to 462 mbps. the high-speed differential i/o support chapter in the stratix device handbook, volume 1, and the device pin-outs on the web ( www.altera.com ) specify which channels are high and low speed. altera corporation 8?11 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices ac timing specifications stratix and stratix gx devices support a pcs interface. figures 8?8 and 8?9 and tables 8?4 and 8?5 illustrate timi ng characteristics of the pcs transmitter and receiver interfaces. figure 8?8 shows the ac timing diagram for the stratix and stratix gx pcs transmitter. you can determin e pcs channel-to-channel skew by adding the data invalid window before the rising edge (t cq_pre ) to the data invalid window after the rising edge (t cq_post ). figure 8?8. pcs transmitter timing diagram table 8?3. stratix gx device xsbi core support stratix gx device number of lvds channels (receive/transmit) (1) number of fast plls number of xsbi interfaces (maximum) ep1sgx10 22/22 2 1 ep1sgx25 39/39 2 2 ep1sgx40 45/45 4 2 note to ta b l e 8 ? 3 : (1) the lvds channels can go up to 840 mbps for flip-chip packages and up to 624 mbps for wire-bond packages. this number includes both high speed and low speed channels. the high speed lvds channels can go up to 840 mbps. the low speed lvds channels can go up to 462 mbps. the high-speed differential i/o support chapter in the stratix device handbook, volume 1, and the device pin-outs on the web ( www.altera.com ) specify which channels are high and low speed. t period t cq_pre t cq_post t setup t hold valid data tx_data[15..0] pma_tx_clk 8?12 altera corporation stratix device handbook, volume 2 july 2005 interfaces table 8?4 lists the ac timing specifications for the pcs transmitter. figure 8?9 shows the ac timing diagram for the stratix and stratix gx pcs receiver interface. you can dete rmine the pcs sampling window by adding t setup to t hold . receiver skew margin (rskm) refers to the amount of skew tolerated on the printed circuit board (pcb). figure 8?9. pcs receiver timing diagram table 8?5 lists the ac timing specifications for the pcs receiver interface. table 8?4. pcs transmitter timing specifications parameter value unit min typ max pma_tx_clk t period (wan) 1,608 ps pma_tx_clk t period (lan) 1,552 ps data invalid window before the rising edge (t cq_pre ) 200 ps data invalid window after the rising edge (t cq_post ) 200 ps pma_tx_clk duty cycle 40 60 % pcs transmitter channel-to-channel skew 200 ps t period t cq_pre t cq_post t setup t hold valid data rx_data[15..0] rskm sampling window rskm transmitter channel-to-channel skew/2 transmitter channel-to-channel skew/2 t period rx_data[15..0] pma_rx_clk pma_rx_clk table 8?5. pcs receiver timing specifications (part 1 of 2) parameter value unit min typ max pma_rx_clk t period (wan) 1,608 ps pma_rx_clk t period (lan) 1,552 ps data invalid window before the rising edge (t cq_pre )200ps data invalid window after the rising edge (t cq_post )200ps altera corporation 8?13 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices xgmii the purpose of xgmii is to provide a simple, inexpensive, and easy to implement interconnection between the mac sublayer and the phy. though xgmii is an optional interfac e, it is used extensively in the 10-gigabit ethernet standard as the basis for the specification. the conversion between the parallel data paths of xgmii and the serial mac data stream is carried out by the reconciliation sublayer. the reconciliation sublayer maps the si gnal set provided at the xgmii to the physical layer signaling (pls) service primitives provided at the mac. xgmii supports a 10-gbps mac data rate. functional description the xgmii is composed of independent transmit and receive paths. each direction uses 32 data signals, txd[31..0] and rxd[31..0] , 4 control signals, txc[3..0] and rxc[3..0] , and a clock tx_clk and rx_clk . figure 8?10 shows the xgmii functional block diagram. pma_rx_clk duty cycle 45 55 % data set-up time (t setup ) 300 ps data hold time (t hold ) 300 ps pcs sampling window 600 ps rskm (wan) 304 ps rskm (lan) 276 ps table 8?5. pcs receiver timing specifications (part 2 of 2) parameter value unit min typ max 8?14 altera corporation stratix device handbook, volume 2 july 2005 interfaces figure 8?10. xgmii functi onal block diagram the 32 txd and four txc signals as well as the 32 rxd and four rxc signals are organized into four data lanes. the four lanes in each direction share a common clock ( tx_clk for transmit and rx_clk for receive). the four lanes are used in round-robin sequence to carry an octet stream (8 bits of data per lane). the reconcil iation sublayer generates continuous data or control characters on the tr ansmit path and expects continuous data or control characters on the receive path. implementation xgmii uses the 1.5-v hs tl i/o standard. stratix and stratix gx devices support the 1.5-v hstl class i and cl ass ii i/o standard (eia/jesd8-6). the standard requires a differential input with an external reference voltage (v ref ) of 0.75 v, as well as a termination voltage v tt of 0.75 v, to which termination resistors are connected. the hstl class i standard requires a 1.5-v v ccio voltage, which is supported by stratix and stratix gx devices. figure 8?11 shows the 32-bit full-duplex 1. 5-v hstl implementation of xgmii. pcs transmit pcs pcs receive pma xgmii tx_data[15..0] rx_data[15..0] txd[31..0] rxd[31..0] xsbi tx_clk rx_clk rxc[3..0] txc[3..0] altera corporation 8?15 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices figure 8?11. stratix & stratix gx xgmii implementation for this implementation, the shift regi ster clocks can either be generated from a divided down mac reconcilia tion sublayer transmitter clock ( mac_txclk ), or the asynchronous core cl ock, or both if using a fifo buffer. figure 8?12 shows one channel of the output half of xgmii. data that is transmitted from the pcs to the mac reco nciliation sublayer starts at the core of the stratix or stratix gx device and travels to the shift register. the shift register takes in the parallel da ta (even bits sent to the top register and odd bits sent to the bottom regist er) and serializes the data. after the data is serialized, it travels to the double data rate (ddr) output circuitry, which is clocked with the 4 clock from the pll. out of the ddr output circuitry, the data drives off-chip along with the 4 clock. this transaction creates the ddr relationship between the clock and the da ta output. this implementation only shows one channel, but can be duplicated to include all 32 bits of the rx_d signal and all 4 bits of the rx_c signal. shift re g ister shift re g ister 4 4 clk data clk data transmitter receiver mac (rs) rx_d[31..0] mac_rxclk mac_txclk tx_d[31..0] receiver transmitter stratix & stratix gx pcs rx_c[3..0] tx_c[3..0] ddr in p u t c i rc ui tr y ddr o u tp u t c i rc ui tr y pll1 pll2 stratix & stratix gx lo g ic array 8?16 altera corporation stratix device handbook, volume 2 july 2005 interfaces figure 8?12. stratix & stratix gx xgmii output implementation (one channel) figure 8?13 shows one channel of the input half of the xgmii interface. from the receiver side, the ddr data is captured from the mac to the stratix and stratix gx pcs ddr input circuitry. the serial data is separated into two individual data st reams with the even bits routed to the top register and odd bits routed to the bottom register. the ddr input circuitry produces two output data stre ams that go into the shift registers. from the shift registers, the data is deserialized using the clock from the mac, combining into an 8-bit word. th is parallel data goes to a register that is clocked by the di vide-by-4 clock from the pl l. this data and clock go to the stratix and stratix gx core. this implementation shows only one channel, but can be duplicated to include all 32 bits of the tx_d signal and all 4 bits of the tx_c signal. rx_d[0] 8 4 mac receiver mac_rxclk stratix & stratix gx pcs output 156.25 mhz 312.5 mbps 4 shift re g ister d0,d2,d4,d6 d1,d3,d5,d7 dff dff pll 4 data clk data clk 39.0625 mhz 156.25 mhz ddr o u tp u t c i rc ui tr y shift re g ister stratix & stratix gx lo g ic array altera corporation 8?17 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices figure 8?13. stratix & stratix gx xgmi i input implementation (one channel) stratix and stratix gx devices contai n up to four enhanced plls. these plls provide features such as clock switchover, spread-spectrum clocking, programmable bandwidth, phase and delay control, and pll reconfiguration. since the maximum cl ock rate is 156.25 mhz, you can use a fast or enhanced pll for both the xgmii output and input blocks. f for more information about fast plls, see the stratix device family data sheet section of the stratix device handbook, volume 1 or the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 . with this implementation for the xgmii output and input blocks, the number of xgmii cores per device corresponds to the number of plls each stratix and stratix gx device contains. tables 8?6 and 8?7 show the number of 1.5-v hstl i/o pins, plls, and xgmii cores that are supported in each stratix and stratix gx device. each core requires 72 1.5- tx_d[0] 8 8 mac_txclk stratix & stratix gx pcs input 156.25 mhz 312.5 mbps 4 shift re g ister ddr in p u t c i rc ui tr y d0,d2,d4,d6 d1,d3,d5,d7 39.0625 mhz 156.25 mhz mac transmitter data clk stratix & data clk dff dff latch dff pll 4 shift re g ister 4 stratix gx lo g ic array 8?18 altera corporation stratix device handbook, volume 2 july 2005 interfaces v hstl i/o pins for data and control and 2 clock pins fo r the transmitter and receiver clocks. each xgmii core also needs two plls (one for each direction). reduced system noise the output buffer of each stratix and stratix gx device i/o pin has a programmable drive strength control for certain i/o standards. the 1.5- v hstl class i standard supports the minimum setting, which is the lowest drive strength that guarantees i oh and i ol of the standard. using minimum settings provides signal sl ew rate control to reduce system noise and signal overshoot. f for more information on i oh and i ol values, see operating conditions in the dc & switching characteristics chapter of the stratix device handbook, volume 1 or operating conditions in the dc & switching characteristics chapter of the stratix gx device handbook, volume 1 . table 8?6. stratix xgmii core support stratix device number of 1.5-v hstl class i i/o pins number of fast & enhanced plls number of xgmii interfaces ep1s10 410 6 3 ep1s20 570 6 3 ep1s25 690 6 3 ep1s30 718 10 5 ep1s40 814 12 6 ep1s60 1,014 12 6 ep1s80 1,195 12 6 table 8?7. stratix gx xgmii core support stratix device number of 1.5-v hstl class i i/o pins number of fast & enhanced plls number of xgmii interfaces ep1sgx10 c, d 226 4 2 ep1sgx25 c 253 4 2 ep1sgx25 d, f 370 4 2 ep1sgx40 d, g 430 8 4 altera corporation 8?19 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices timing xgmii signals must meet the ti ming requirements shown in figure 8?14 . make all xgmii timing me asurements at the driver output (shown in figure 8?14 ) and a capacitive load from all sources of 20 pf that are specified relative to the v il _ac(max) and v ih _ac(min) thresholds. figure 8?14. xgmii timing diagram table 8?8 shows the xgmii timing specifications. stratix and stratix gx devices support ddr data with clock rates of up to 200 mhz, well above the xgmii clock rate of 156.25 mhz. for the hstl class i i/o standard, stratix and stra tix gx device i/o drivers provide a 1.0-v/ns slew rate at the input buffer of the receiving device. xaui xaui (pronounced zowie) is located between the xgmii at the reconciliation sublayer and the xgmii at the phy layer. figure 8?15 shows the location of xaui. xaui is de signed to either extend or replace xgmii in chip-to-chip applicatio ns of most ethernet mac to phy interconnects. table 8?8. xgmii timin g specifications note (1) symbol driver receiver unit t setup 960 480 ps t hold 960 480 ps note to ta b l e 8 ? 8 : (1) the actual set-up and hold times will be made available after device characterization is complete. t setup t hold t setup t hold tx_clk rx_clk txc, txd, rxc, rxd v ih _ac(min) v il _ac(max) v ih _ac(min) v il _ac(max) 8?20 altera corporation stratix device handbook, volume 2 july 2005 interfaces figure 8?15. xaui location functional description xaui can replace the 32 bits of para llel data required by xgmii for transmission with just 4 lanes of serial data. xaui uses clock data recovery (cdr) to eliminate the need for separate clock signals. 8b/10b encoding is employed on the data st ream to embed the clock in the data. the 8b/10b protocol to encode an 8-bi t word stream to 10-bit codes that results in a dc-balanced serial stream and eases the receiver synchronization. to support 10-gigabit ethernet, each lane must run at a speed of at least 2.5 gbps. using 8b/10b encoding increases the rate for each lane to 3.125 gbps, which will be supported in stratix gx gbps devices. this circuitry is supported by the embedded 3.125 gbps transceivers within the stratix gx architecture. you can find more xgxs phy xaui xgmii xgmii reconciliation mac xgmii extender sublayer (xgxs) altera corporation 8?21 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices information on xaui support in section ii, stratix gx transceiver user guide of the stratix gx device handbook, volume 2 . figure 8?16 shows how xaui is implemented. figure 8?16. stratix gx xa ui implementation i/o characteristics for xsbi, xgmii & xaui the three interfaces of 10-gigabit ethernet (xsbi, xgmii, and xaui) each have different rates and i/o standards. table 8?9 shows the characteristics for each interface. tx_d[0] 8 8 ch0 ch0 rx_d[0] stratix gx xaui cdr tx tx_d[3] 8 ch3 cdr tx 8 ch3 rx_d[3] pcs receiver transmitter cdr rx cdr rx 3.125 gbps stratix gx lo g ic array table 8?9. 10-gigabit ethernet in terfaces char acteristics interface width clock rate (mhz) data rate per channel clocking scheme i/o type xgmii 32 156.25 312.5 mbps ddr source synchronous 1.5-v hstl xsbi 16 644.5 or 622.08 644.5 or 622.08 mbps sdr source synchronous lv d s xaui 4 none 3.125 gbps clock data recovery (cdr) 1.5-v pcml 8?22 altera corporation stratix device handbook, volume 2 july 2005 i/o characteristics for xsbi, xgmii & xaui software implementation you can use the assignment organizer in the altera ? quartus ? ii software to implement the i/o standard s for a particular interface. for example, set the i/o standard to lvds for xsbi and to hstl class i for xgmii. you can use the megawizard ? plug-in manager to create the plls and transmitter and receiver serdes blocks for the xsbi implementation and plls and ddr in put and output circuitry for the xgmii implementation. for more information on the assignment organizer or megawizard plug-in mana ger, see the quartus ii software help. ac/dc specifications table 8?10 lists the xsbi dc electrical ch aracteristics, similar to stratix and stratix gx devices, that are based on the ansi/tia-644 lvds specification. i/o characteristics for the 1.5-v hstl standard for stratix and stratix gx devices are shown in figure 8?17 and comply with xgmii electrical specifications available in 10-giga bit ethernet draft ieee p802.3ae. table 8?10. xsbi dc specifications parameter value unit min typ max output differential voltage (v od ) 250 400 (1) mv output offset voltage (v os ) 1,125 1,375 mv output impedance, single ended 40 140 w change in v od between ?0? and ?1? 50 mv change in v os between ?0? and ?1? 50 mv input voltage range (v i ) 900 1,600 mv differential impedance 100 w input differential voltage (v id ) 100 600 mv receiver differential input impedance 70 130 w ground potential difference (between pcs and pma) 50 mv rise and fall times (20 % to 80 % ) 100 400 ps note to table 8?10 : (1) larger v od is possible for better signal intensity. altera corporation 8?23 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices figure 8?17. electrical characteristic s for stratix & stratix gx devices (1.5-v hstl class i) v ref c l = 20pf v in v out r t = 50 v tt output buffer input buffer t z (min) = 1 v/ns t pd hstl ac load circuit for class i hstl ac waveform & i/o interface t f (min) = 1 v/ns v swing = 1.0 v input output tri-stated output t pl2 t ph2 80 % v swing v ref 20 % v swing v oh = v ccn ? 0.4 v = 1.1 v v tt = v ccn /2 = 0.75 v v ol = 0.4 v v ih(ac) = 0.95 v v tt = 0.75 v v il(ac) = 0.55 v 8?24 altera corporation stratix device handbook, volume 2 july 2005 i/o characteristics for xsbi, xgmii & xaui table 8?11 lists the dc specifications for stratix and stratix gx devices (1.5-v hstl class i). 10-gigabit ethernet mac core as an altera megafunction partners program (ampp sm ) member, morethanip provides a 10-gigabit ethernet mac core for altera customers. morethanip?s 10-gigabit ethernet mac core implements the rs, the mac layer, and user-progra mmable fifo buffers for clock and data decoupling. core features morethanip?s 10-gigabit ethernet mac core provides the following features: includes automatic pause frame generation (per ieee 802.3 31) with user-programmable pause quanta and pause-frame termination includes a programmable 48-bit mac address with a promiscuous mode option, and a programmable ethernet frame length that supports ieee 802.1q vlan-tagged frames or jumbo ethernet frames table 8?11. dc specificat ions for stratix & stratix gx devices (1.5-v hstl class i) note (1) symbol parameter conditions minimum typical maximum units v ccio i/o supply voltage 1.4 1.5 1.6 v v ref input reference voltage 0.68 0.75 0.9 v v tt termination voltage 0.7 0.75 0.8 v v ih (dc) dc high-level input voltage v ref + 0.1 v v il (dc) dc low-level input voltage ?0.3 v ref ? 0.1 v v ih (ac) ac high-level input voltage v ref + 0.2 v v il (ac) ac low-level input voltage v ref ? 0.2 v i i input pin leakage current 0 < v in < v ccio ?10 10 a v oh high-level output voltage i oh = ?8 ma v ccio ? 0.4 v v ol low-level output voltage i ol = 8 ma 0.4 v i o output leakage current (when output is high z) gnd v out v ccio ?10 10 a note to ta b l e 8 ? 11 : (1) drive strength is programmable according to values shown in the stratix device family data sheet section of the stratix device handbook, volume 1 or the stratix gx device fa mily data sheet section of the stratix gx device handbook, volume 1 . altera corporation 8?25 july 2005 stratix device handbook, volume 2 implementing 10-gigabit ethernet using stratix & stratix gx devices supports broadcast traffic and multi- cast address reso lution with a 64-entry hash table compliant with the ieee802.3ae draft 4.0 implements xgmii, allowing it to interface to xaui through a 10-gigabit commercial serdes conclusion 10-gigabit ethernet takes advantage of the existing gigabit ethernet standard. with their rich i/o feat ures, stratix and stratix gx devices support the components of 10-gigabit ethernet as well as xsbi and xgmii. stratix gx devices also support xaui. these interfaces are easily implemented using the core architecture, differential i/o capabilities, and superior plls of stratix and stratix gx devices. 8?26 altera corporation stratix device handbook, volume 2 july 2005 i/o characteristics for xsbi, xgmii & xaui altera corporation 9?1 july 2005 9. implementing sfi-4 in stratix & stratix gx devices introduction the growth of the internet has created huge bandwidth demands as voice, video, and data push the limits of the existing wide area network (wan) backbones. to facilitate this bandwidth growth, speeds of oc-192 and higher are being deployed in wan backbones (see figure 9?1 ). today?s carrier backbone networks are supported by sonet/sdh transmission tech nology. sonet/sdh is a transmission technology for transporting optical signals at sp eeds ranging from 51 megabits per second (mbps) up to 40 gigabits per second (gbps). sonet/sdh rings make up the majority of the existi ng backbone infrastructure of the internet and the public switched telephone network (pstn). the optical internetworking forum (oif ) standard sfi-4 is a 16-bit lvds interface used in an oc-192 sonet system to link the framer and the serializer/deserializer (serdes). stratix ? and stratix gx devices support the required data rates of up to 622.08 mbps along with the one-to-one relationship required between clock frequency and data rate. the fast phase-locked loop (pll) was designed to support the high clock frequencies and the one-to-one relationship (between clock and data rate) needed for interfaces su ch as xsbi and sfi-4. support for sfi-4 extends the reach of high-density programmable logic from the backplane to the physical layer (phy) devices. this chapter focuses on the implemen tation of the interface between the serdes and the framer. figure 9?1. wan backbone a sonet/sdh transmission network is composed of several pieces of equipment, including terminal multiplexers, add-drop multiplexers, and repeater and digital cross-connect systems. sonet is the standard used in north america and sdh is the standard used outside north america. sonet oc-48 sonet oc-192 sdh stm-64 dwdm 40 g ~~ s52011-2.0 9?2 altera corporation stratix device handbook, volume 2 july 2005 introduction the sonet/sdh specification outlines the frame format, multiplexing method, synchronization method, an d optical interface between the equipment, as well as the specific optical interface. sonet/sdh continues to play a key role in the next generation of networks for many carriers. in the core network, the carriers offer services such as telephone, dedica ted leased lines, and inte rnet protocol (ip) data, which are continuously transmitted. the individual data channels are not transmitted on separate lines; instea d, they are multiplexed into higher speeds and transmitted on sonet/sd h networks at the corresponding transmission speed. figure 9?2 shows a typical sonet/sdh line card. the system operates as follows: 1. the sonet/sdh line card first ta kes a high-speed serial optical signal and converts it into a high-s peed serial electrical signal. the devices are called physical media dependent (pmd) devices. 2. the system then recovers the cloc k from the electrical data using a clock data recovery (cdr) unit. 3. the serdes parallelizes the data so that it can be manipulated easily at lower clock rates. 4. the interface between the serdes and framer is called the serdes framer interface. the interface re quirements are defined by the oif. 5. the framer identifies the beginn ing of the sonet/sdh frames and monitors the performance of the system. 6. the mapper following the framer maps asynchronous transfer mode (atm) cells, ip packets, or t/e carrier signals into the sonet frame. 7. the phy-link layer interface prov ides a bus interface to packet/cell processors or other link-layer devices. altera corporation 9?3 july 2005 stratix device handbook, volume 2 implementing sfi-4 in stratix & stratix gx devices figure 9?2. sonet/sdh line card the oif has defined the electric al interface (sfi) between the sonet/sdh framer and high-speed serdes devices. to keep up with evolving transmission speeds and technology enhanc ements, different versions of electrical interfaces are defined. sfi-4 is the version of sfi that acts as an interface between an oc-192 serdes and sonet framer, as shown in figure 9?2 . an aggregate of 9953.28 mbps is transferred in each direction. with their differential i/o capabilities, stratix and stratix gx devices are ideally suited to support the framer side of th e sfi-4 interface. support for sfi-4 extends the reach of high-density programmable logic from the backplane to the phy devices. system topology the sfi-4 interface uses 16 channels of source-synchronous lvds to interface between a sonet framer and an oc-192 serdes. figure 9?3 shows the sfi-4 interface. cdr oe module sonet/sdh mapper/protocol processor sonet/sdh framer serdes optical signal serdes framer interface optical-electrical conversion link layer interface to packet processor & switch fabri c 7 6 5 4 3 12 9?4 altera corporation stratix device handbook, volume 2 july 2005 introduction figure 9?3. sfi-4 interface signals the framer transmits outbound data via txdata[15..0] and is received at the serdes using txclk . txclk is derived from txclk_src , which is provided by the oc-192 serdes. the framer receives incoming data on rxdata[15..0] from the oc-192 serdes. the data received is latched on the rising edge of rxclk . table 9?1 provides the data rates and clock frequencies specified by sfi-4. the modes of txclk are specified by the sfi-4 standard. in required mode (622 mhz clock mode or 1 mode), txclk should run at 622.08 mhz. in optional mode (311 mhz clock mode or 2 mode), txclk should run at 311.04 mhz. table 9?1. sfi-4 interface data rates & clock frequencies signal performance txdata[15..0] 622.08 mbps txclk 622.08 mhz or 311.04 mhz txclk_src 622.08 mhz rxdata[15..0] 622.08 mbps rxclk 622.08 mhz refclk 622.08 mhz sonet framer transmitter oc-192 serdes transmitter txdata[15..0] txclk txclk_src rxdata[15..0] rxclk sonet framer receiver recovered clock receiver refclk altera corporation 9?5 july 2005 stratix device handbook, volume 2 implementing sfi-4 in stratix & stratix gx devices interface implementation in stratix & stratix gx devices the 16-bit full-duplex lvds implementa tion of the framer part of the sfi-4 interface is shown in figure 9?4 . stratix devices support source- synchronous interfacing and lvds di fferential signaling up to 840 mbps. stratix devices have embedded serdes circuitry for serial and parallel data conversion. the source-synchronous i/o implemented in stratix gx devices optionally includes dynamic phase alignment (dpa). dpa automatically and continuously tracks fluctuations caused by system variations and self-adjusts to eliminate the phase skew between the multiplied clock and the serial data, allowing for data rates of 1 gbps. in non dpa mode the i/o behaves similarly to that of the stratix i/o. this document assumes that dpa is disabled. however, it is simple to implement the same system with dpa enabled to take advantage of its features. for more information on dpa, see the stratix gx transceivers chapter in the stratix gx device handbook , volume 1 . the fast pll enables 622.08 mbps data transmission by transmitting and receiving a differential clock at rates of up to 645 mhz. the clocks required in the serdes for parallel and serial data conversion can be configured from the received rxclk (divided down), the txclk_src (divided down), or the asynchronous core clock. see figure 9?4 . 9?6 altera corporation stratix device handbook, volume 2 july 2005 introduction figure 9?4. implementation of sfi-4 interface using stratix & stratix gx devices f for details on differential i/o buffer s, serdes, and clock dividers using plls, see the high-speed differential i/o interfaces in stratix devices chapter in the stratix device handbook or the stratix gx device handbook . figure 9?5 shows the transmitter block (from figure 9?4 ) of the sfi-4 framer interface implemented in stra tix and stratix gx devices. the data starts in the logic array and goes into the stratix and stratix gx serdes block. the transmitter serd es of the framer converts the parallel data to serial data for the 16 txdata channels ( txdata[15..0] ). a fast pll is used to generate txclk from txclk_src . the fast pll keeps the txdata and txclk edge-aligned. a divided down ( 8) clock generated from txclk_src is used to convert the parallel data to serial in the transmitter serdes. the divided down clock also clocks some of the logic in the logic array. transmitter serdes receiver serdes 1 8 8 180? stratix framer clk data clk data transmitter receiver oc-192 serdes txdata[15..0] txclk txclk_src rxclk rxdata[15..0] phase shift receiver transmitter pll1 128 128 refclk pll2 stratix & stratix gx lo g ic array altera corporation 9?7 july 2005 stratix device handbook, volume 2 implementing sfi-4 in stratix & stratix gx devices figure 9?5. framer transmitter interfac e in stratix & stratix gx devices figure 9?6 shows the receiver block (from figure 9?4 ) of the sfi-4 framer interface implemented in stratix and stratix gx devices. rxdata[15..0] is received from the oc-192 serdes on the differential i/o pins of the stratix or strati x gx device. the receiver serdes converts the high-speed serial data to parallel. you can generate the clocks required in the serdes for parallel and serial data conversion from the received rxclk . rxclk is inverted (phase-shifted by 180 ) to capture received data. while normal i/o operation guarantees that data is captured, it does not guarantee the parallelization boundary, which is randomly determined based on the power up of both communicating devices. the serdes has embedded data realignment capability, which can be used to save logic elements (les). txdata[0] fast pll w = 1 j = 8 8 8 stratix & stratix gx serdes w ch0 ch15 oc-192 serdes txdata[15] txclk txclk_src stratix & stratix gx sfi-4 transmitter j 622 mhz 622 mhz 622mhz 622 mbps parallel re g ister parallel-to-serial re g ister stratix & stratix gx lo g ic array 9?8 altera corporation stratix device handbook, volume 2 july 2005 introduction figure 9?6. framer receiver interface in stratix & stratix gx devices note to figure 9?6 : (1) the figure shows stratix gx dpa disabled. f for more information on the byte-a lignment feature in stratix and stratix gx devices, see the high-speed differential i/o interfaces in stratix devices chapter in the stratix device handbook or the stratix gx device handbook . rxdata[0] fast pll w = 1 j = 8 8 8 stratix & stratix gx serdes w ch0 ch15 oc-192 serdes rxdata[15] rxclk stratix & stratix gx sfi-4 receiver j 622 mhz 622 mhz parallel re g ister serial-to-parallel re g ister 622 mbps stratix & stratix gx lo g ic array altera corporation 9?9 july 2005 stratix device handbook, volume 2 implementing sfi-4 in stratix & stratix gx devices tables 9?2 and 9?3 list the number of sfi-4 cores that can be implemented in stratix and stratix gx devices. see the high-speed differential i/o interfaces in stratix devices chapter in the stratix device handbook or the stratix gx device handbook for the package type and the maximum number of channels supported by each package. table 9?2. stratix sfi-4 core support stratix device number of lvds channels (receiver/transmitter) (1) number of plls number of sfi-4 interfaces (maximum) ep1s10 44/44 4 2 ep1s20 66/66 4 2 ep1s25 78/78 4 2 ep1s30 82/82 8 4 ep1s40 90/90 8 4 ep1s60 116/116 8 4 ep1s80 152/156 8 4 note to ta b l e 9 ? 2 : (1) the lvds channels can go up to 84 0 mbps (or 1 gbps using dpa in stratix gx devices). this number includes both high speed and low speed channels. the high speed lvds channels can go up to 840 mbps. the low speed lvds channels can go up to 462 mbps. the high-speed differential i/o support chapters in the stratix device handbook, volume 1 and the stratix gx device handbook, volume 1 and the device pin-outs on the web ( www.altera.com ) specify which channels are high and low speed. table 9?3. stratix gx sfi-4 core support stratix gx device number of lvds channels (receiver/transmitter) (1) number of plls number of sfi-4 interfaces (maximum) ep1sgx10 22/22 2 1 ep1sgx25 39/39 2 2 ep1sgx40 45/45 4 2 note to ta b l e 9 ? 3 : (1) the lvds channels can go up to 84 0 mbps, or 1 gbps using dpa. this number includes both high speed and low speed ch annels. the high speed lvds channels can go up to 840 mbps. the low speed lvds channels can go up to 462 mbps. the high-speed differential i/o support chapter in the stratix device ha ndbook, volume 1 and the stratix gx device handbook, volume 1 and the device pin-outs on the web ( www.altera.com ) specify which channels are high and low speed. 9?10 altera corporation stratix device handbook, volume 2 july 2005 introduction ac timing specifications figures 9?7 through 9?9 and tables 9?4 through 9?6 illustrate the timing characteristics of sfi-4 at the fr amer. stratix and stratix gx devices support all the timing requirements needed to support transmitter and receiver functions of a sfi-4 fram er; only framer-related timing specifications are applicable. f for details on the timing specificatio ns of lvds i/o standards in stratix and stratix gx devices, see the stratix device family data sheet section of the stratix device handbook, volume 1 and the high-speed differential i/o interfaces in stratix devices chapter or the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 and the high- speed differential i/o interfaces in stratix devices chapter figure 9?7 shows the timing diagram for the stratix and stratix gx framer transmitter 1 (622 mhz clock) mode. figure 9?7. framer transmitter 1 (622 mhz clock) mode timing diagram table 9?4 lists the timing specifications fo r the sfi-4 framer transmitter in 1 (622 mhz clock) mode. t period t cq_pre t cq_post t setup t hold valid data tx_data[15..0] table 9?4. sfi-4 framer transmitter 1 (622 mhz clock) mode timing specifications parameter value unit min typ max tx_clk (t period ) 1,608 ps data invalid window before the rising edge (t cq_pre )200ps data invalid window after the rising edge (t cq_post )200ps tx_clk duty cycle 40 60 % framer transmitter channel-to-channel skew 200 ps altera corporation 9?11 july 2005 stratix device handbook, volume 2 implementing sfi-4 in stratix & stratix gx devices figure 9?8 shows the timing diagram for th e sfi-4 framer transmitter in 2 (311 mhz clock) mode figure 9?8. framer transmitter 2 (311 mhz clock) mode timing diagram table 9?5 lists the timing specifications fo r the sfi-4 framer transmitter in 2 (311 mhz clock) mode. figure 9?9 shows the timing diagram for the sfi-4 framer receiver. figure 9?9. framer receiver timing diagram t period/2 t cq_pre t cq_post valid data tx_data[15..0] valid data tx_clk(p) table 9?5. sfi-4 framer transmitter 2 (311 mhz clock) mode timing specifications parameter value unit min typ max tx_clk (t period ) 3,215 ps data invalid window before the rising edge (t cq_pre )200ps data invalid window after the rising edge (t cq_post )200ps tx_clk duty cycle 48 52 % framer transmitter channel-to-channel skew 200 ps t period t cq_pre t cq_post t setup t hold valid data rx_data[15..0] rx_clk(p) rx_clk(p) rskm sampling window rskm transmitter channel-to-channel skew/2 transmitter channel-to-channel skew/2 tperiod rx_data[15..0] 9?12 altera corporation stratix device handbook, volume 2 july 2005 introduction table 9?6 lists the timing specifications for the sfi-4 framer receiver. electrical specifications sfi-4 uses lvds as a high-speed da ta transfer mechanism to implement the sfi-4 interface. table 9?7 lists the dc electrical characteristics for the interface, which are based on the ie ee std. 1596.3-1996 7 specification. for more information on the voltage specification of lvds i/o standards in stratix and stratix gx devices, see the stratix device family data sheet section of the stratix device handbook, volume 1 and the high-speed differential i/o interfaces in stratix devices chapter or the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 and the high-speed differential i/o interfaces in stratix devices chapter. table 9?6. framer receiver timing specifications parameter value unit min typ max rx_clk (t period ) 1,608 ps data invalid window before the rising edge (t cq_pre )200ps data invalid window after the rising edge (t cq_post )200ps rx_clk duty cycle 45 55 % data set-up time (t setup ) 300 ps data hold time (t hold ) 300 ps framer sampling window 600 ps receiver skew margin (rskm) 304 ps altera corporation 9?13 july 2005 stratix device handbook, volume 2 implementing sfi-4 in stratix & stratix gx devices software implementation the sfi-4 interface uses a 16-bit lvds i/o interface. the altera ? quartus ? ii software version 2.0 support s stratix and stratix gx devices, allowing you to implement lvds i /o buffers through the quartus ii assignment organizer. f for information on the quartus ii assignment organizer, see the quartus ii software help. conclusion sfi-4 is the standard interface between sonet framers and optical serdes for oc-192 interfaces. with embedded serdes and fast plls, stratix and stratix gx devices can easily support the sfi-4 framer interface, enabling 10-gbps (oc-192) data transfer rates. stratix and stratix gx i/o supports the required data rates of up to 622.08 mbps. stratix and stratix gx fast plls are designed to support the hi gh clock frequencies and one-to-one relationship needed for interfaces su ch as xsbi and sfi-4. stratix and stratix gx devices can support multiple sfi-4 functions on one device. table 9?7. framer lvds dc specifications parameter value unit min typ max output differential voltage (v od ) 250 600 (1) mv output offset voltage (v os ) 1,125 1,375 mv output impedance, single ended 40 140 w change in v od between ?0? and '1' 50 mv change in v od between '1' and '0' 50 mv input voltage range (v i ) 0 2,400 mv differential impedance 100 w input differential voltage (v id ) 100 600 mv receiver differential input impedance 70 130 w ground potential difference (between pcs and pma) 50 mv rise and fall times (20 % to 80 % ) 100 400 ps note to ta b l e 9 ? 7 : (1) the ieee standard requires 400 mv. a larger swing is encouraged, but not required. 9?14 altera corporation stratix device handbook, volume 2 july 2005 introduction altera corporation 10?1 july 2005 10. transitioning apex designs to stratix & stratix gx devices introduction stratix ? and stratix gx devices are altera ?s next-generation, system-on- a-programmable-chip (sopc) soluti on. stratix and stratix gx devices simplify the block-based design methodology and bridge the gap between system bandwidth requir ements and programmable logic performance. this chapter highlights the new feat ures in the stratix and stratix gx devices and provides assistance when transitioning designs from apex tm ii or apex 20k devices to the st ratix or stratix gx architecture. you should be familiar with the ap ex ii or apex 20k architecture and available device features before usin g this chapter. us e this chapter in conjunction with the stratix device family data sheet section of the stratix device handbook, volume 1 or the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 . general architecture stratix and stratix gx devices offer many new features and architectural enhancements. enhanced logic elements (les) and the multitrack tm interconnect structure offer re duced resource utilization and considerable design performanc e improvement. the multitrack interconnect uses directdrive tm technology to ensure the availability of deterministic routing resources for an y design block, regardless of its placement within the device. all architectural changes between st ratix and stratix gx and apex ii or apex 20k devices described in this section do not require any design changes. however, you must resynthesi ze your design and recompile in the quartus ? ii software to target stratix and stratix gx devices. s52012-3.0 10?2 altera corporation stratix device handbook, volume 2 july 2005 general architecture logic elements stratix and stratix gx device les include several new, advanced features that improve design performance and reduce logic resource consumption (see table 10?1 ). the quartus ii software au tomatically us es these new le features to improve device utilization. in addition to the new le features described in table 10?1 , there are enhancements to the chains that conn ect les together. carry chains are implemented vertically in stratix and stratix gx devices, instead of horizontally as in apex ii and apex 20k devices, and continue across rows, instead of across columns, as shown in figure 10?1 . also note that the stratix and stratix gx architectures do not support the cascade primitive. therefore, the quartus i i compiler automatically converts table 10?1. stratix & stratix gx le features feature function benefit register chain interconnects direct path between the register output of an le and the register input of an adjacent le within the same logic array block (lab) ? conserves le resources ? provides fast shift register implementation ? saves local interconnect routing resources within an lab look-up table (lut) chain interconnects direct path between the combinatorial output of an le and the fast lut input of an adjacent le within the same lab ? allows luts within the same lab to cascade together for high-speed wide fan-in functions, such as wide xor operations ? bypasses local interconnect for faster performance register-to-lut feedback path allows the register output to feed back into the lut of the same le, such that the register is packed with its own fan- out lut ? enhanced register packing mode ? uses resources more efficiently dynamic arithmetic mode uses o ne set of les for implementing both an adder and subtractor ? improves performance for functions that switch between addition and subtraction frequently, such as correlators carry-select chain calculates outputs for a possible carry- in of 1 or 0 in parallel ? gives immediate access to result for both a carry-in of 1 or 0 ? increases speed of carry functions for high-speed operations, such as counters, adders, and comparators asynchronous clear and asynchronous preset function supports direct asynchronous clear and preset functions ? conserves le resources ? does not require additional logic resources to implement not-gate push-back altera corporation 10?3 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices cascade primitives in apex ii and apex 20k designs to a wire primitive when compiled for stratix and stra tix gx devices. these architectural changes are transparent to the user and do not require design changes. figure 10?1. carry chain impl ementation in apex ii & apex 20k devices vs. stratix & stratix gx devices multitrack interconnect stratix and stratix gx devices use the multitrack interconnect structure to provide a high-speed connectio n between logic resources using performance-optimized routing channe ls of different lengths. this feature maximizes overall design perf ormance by placing critical paths on routing lines with greater speed, resulting in minimal propagation delay. labs (with 1 0 les each) carry chains apex ii & apex 20k devices stratix devices carry-selec t chains 10?4 altera corporation stratix device handbook, volume 2 july 2005 general architecture stratix and stratix gx device multitrack interconnect resources are described in table 10?2 . direct link routing saves row routing resources while providing fast communication paths between resource blocks. direct link interconnects allow an lab, digital signal proc essing (dsp) bloc k, or trimatrix tm memory block to drive data into the loca l interconnect of its left and right neighbors. labs, dsp blocks, and trimatrix memory blocks can also use direct link interconnects to drive da ta back into themselves for feedback. the quartus ii software automatically uses these routing resources to enhance design performance. f for more information about le ar chitecture and the multitrack interconnect structure in stratix and stratix gx devices, see the stratix device family data sheet section of the stratix device handbook, volume 1 or the stratix gx device family data sheet section of the stratix gx device handbook, volume 1. directdrive technology when using apex ii or ape 20k devices, you must place critical paths in the same megalab tm column to improve perfor mance. additionally, you should place critical paths in the same megalab structure for optimal performance. however, this restrict ion does not exist in stratix and stratix gx devices because they do not contain megalab structures. with the new directdrive tm technology in stratix and stratix gx devices, the actual distance between the source and destination of a path is the most important criteria for meetin g timing performance. directdrive technology ensures that the same routing resources are available to each design block, regardless of its location in the device. table 10?2. stratix & stratix gx device multitrack inte rconnect resources routing type interconnect span row direct link adjacent labs and/or blocks row r4 four lab units horizontally row r8 eight lab units horizontally row r24 horizontal routing across the width of the device column c4 four lab units vertically column c8 eight lab units vertically column c16 vertical routing across the length of the device altera corporation 10?5 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices architectural element names the architectural element naming sy stem within stratix and stratix gx devices differs from the row-column coordinate system (for example, lc1_a2 , lab_b1 ) used in previous altera device families. stratix and stratix gx devices uses a new na ming system based on the x-y coordinate system, ( x , y ). a number ( n ) designates the location within the block where the logic resides, such as les within an lab. because the stratix and stratix gx architectures are column-based, this naming simplifies location assignments. stratix and stratix gx architectural blocks include: lab : logic array block dsp : digital signal processing block dspout : adder/subtractor/accumulator or summation block of the dsp block m512 : 512-bit memory block m4k : 4-kbit memory block m-ram : 512-kbit memory block elements within archit ectural bloc ks include: le : logic element ioc : i/o element pll : phase-locked loop dspmult : dsp block multiplier serdestx : transmitter serializer/deserializer serdesrx : receiver serializer/deserializer 10?6 altera corporation stratix device handbook, volume 2 july 2005 general architecture table 10?3 highlights the new location syntax used for stratix and stratix gx devices. use the following guidelines with the new naming system: the anchor point, or origin, in stra tix and stratix gx devices is in the bottom-left corner, instead of the top -left corner as in apex ii and apex 20k devices. the anchor point, or origin, of a large block element (e.g., a m-ram or dsp block) is also the bottom-left corner. all numbers are zero-based, meaning the origin at the bottom-left of the device is x0 , y0 . the i/o pins constitute the first and last rows and columns in the x-y coordinates. therefore, the bottom row of pins resides in x < number >, y0 , and the first left column of pins resides in x0 , y < number >. the sub-location of elements, n, numbering begi ns at the top. therefore, the les in an lab are still numbered from top to bottom, but start at zero. figure 10?2 show the stratix and stratix gx architectural element numbering convention. figure 10?3 displays the floorplan view in the quartus ii software. table 10?3. stratix & stratix gx location assignment syntax architectural elements element name location syntax example of location syntax location description blocks lab, dsp, dspout, m512, m4k, m-ram < element_name > _x < number > _y < number > lab_x1_y1 designates the lab in row 1, column 1 logic le, ioc, pll, dspmult, serdestx, serdesrx < element_name > _x < number > _y < number > _n < number > lc_x1_y1_n0 designates the first le, n0, in the lab located in row 1, column 1 pins (1) i/o pins pin_ < pin_label > pin_5 pin 5 note to table 10?3 : (1) you can make assignments to i/o pads using ioc_x < number > _y < number > _n < number >. altera corporation 10?7 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices figure 10?2. stratix & stratix gx architectural elements note (1) notes to figure 10?2 : (1) figure 10?2 shows part of a strati x and stratix gx device. (2) large block elements use their lower-le ft corner for the coordinate location. (3) the stratix gx architectural elements include tran sceiver blocks on the right side of the device. ori g in (0, 0) lab (16,18) lab (16,17) lab (16,16) lab (16,15) lab (13,18) lab (13,17) lab (13,16) lab (13,15) lab (11,18) lab (11,17) lab (11,16) lab (11,15) lab (1,18) lab (1,17) lab (1,16) lab (1,15) m512 (12,18) m512 (12,17) m512 (12,16) m512 (12,15) lab (13,1) lab (11,1) lab (1,1) pll (0,1,0) m512 (12,1) lab (16,14) lab (16,13) lab (16,2) lab (16,1) m4k (14,18) m4k (14,17) m4k (14,16) m4k (14,15) m4k (14,14) m4k (14,13) m4k (14,2) m4k (14,1) m4k r am b lo c k s are two u ni ts wi de a n d o n e u ni t hi g h mega ram (1,2) dspmult (17,7,0) and (17,7,1) dspmult (17,5,0) and (17,5,1) dspmult (17,3,0) and (17,3,1) dspmult (17,1,0) and (17,1,1) dspout (18,1,0) and (18,1,7) dsp b lo c k (17,1) i s two u ni ts wi de a n d ei g h t u ni ts hi g h ( 2 ) m ega r am b lo c k i s 1 3 u ni ts wi de a n d 1 3 u ni ts hi g h p in s ( 2 ) ( 2 ) ( 3 ) 10?8 altera corporation stratix device handbook, volume 2 july 2005 trimatrix memory figure 10?3. le numbering as shown in the quartus ii software trimatrix memory trimatrix memory has three different sizes of memory blocks, each optimized for a different purpose or application. m512 bl ocks consist of 512 bits plus parity (576 bits), m4k bloc ks consist of 4k bits plus parity (4,608 bits), and m-ram blocks cons ist of 512k bits plus parity (589,824 bits). this new structure dif fers from apex ii and apex 20k devices, which feature uniformly size d embedded system blocks (esbs) either 4 kbits (apex ii devices) or 2 kbits (apex 20k devices) large. stratix and stratix gx trimatrix me mory blocks give you advanced control of each memory block, with fe atures such as byte enables, parity bit storage, and shift-register mode, as well as mixed- port width support and true dual-port mode operation. altera corporation 10?9 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices table 10?4 compares trimatrix memory with esbs. stratix and stratix gx trimatrix memo ry blocks only support pipelined mode, while apex ii and apex 20k esbs support both pipelined and flow-through modes. since all tr imatrix memory blocks can be pipelined, all input data and address lines are registered, while outputs can be either registered or combinatorial. you can use stratix and stratix gx memory block registers to implement input and output registers without utilizing additional resources. you can compile designs containing pipeline d memory blocks (inputs registered) for stratix and stratix gx devices without any modificati ons. however, if an apex ii or table 10?4. stratix & stratix gx trimatrix memo ry blocks vs. apex ii & apex 20k esbs features stratix & stratix gx apex ii esb apex 20k esb m512 ram m4k ram m-ram size (bits) 576 4,608 589,824 4,096 2,048 parity bits yes yes yes no no byte enable no yes yes no no true dual-port mode no yes includes support for mixed width ye s includes support for mixed width ye s includes support for mixed width no embedded shift register yes yes no no no dedicated content- addressable memory (cam) support no no no yes yes pre-loadable initialization with a .mif (1) ye s ye s n o ye s ye s packed mode (2) no yes no yes yes feed-through behavior rising edge rising edge rising edge falling edge falling edge output power-up condition powers up cleared even if using a .mif (1) powers up cleared even if using a .mif (1) powers up with unknown state powers up cleared or to initialized value, if using a .mif (1) powers up cleared or to initialized value, if using a .mif (1) notes to table 10?4 : (1) .mif : memory initialization file. (2) packed mode refers to combining two single-port ram bl ocks into a single ram block that is placed into true dual-port mode. 10?10 altera corporation stratix device handbook, volume 2 july 2005 trimatrix memory apex 20k design contains flow-through memory, you must modify the memory modules to target the stratix and stratix gx architectures (see ?memory megafunctions? on page 10?12 for more information). f for more information about trimatrix memory and converting flow- through memory modules to pipelined, see the trimatrix embedded memory blocks in stratix & stratix gx devices chapter in the stratix gx device handbook and an 210: converting memory from asynchronous to synchronous for stratix & stratix gx designs. same-port read-during-write mode in same-port read-during-write mode , the ram block can be in single- port, simple dual-port, or true du al-port mode. one port from the ram block both reads and writes to the sa me address location using the same clock. when apex ii or apex 20k devices perform a same-port read- during-write operation, the new data is available on the falling edge of the clock cycle on which it was written, as shown in figure 10?4 . when stratix and stratix gx devices perform a same-port read-during-write operation, the new data is available on the rising edge of the same clock cycle on which it was written, as shown in figure 10?5 . this holds true for all trimatrix memory blocks. figure 10?4. falling edge feed-through behavior (apex ii & apex 20k devices) note (1) note to figure 10?4 : (1) figures 10?4 and 10?5 assume that the address stays constant throughout and that the outputs are not registered. inclock data_in wren data_out a b a old altera corporation 10?11 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices figure 10?5. rising edge feed-through behavior (stratix & stratix gx devices) note (1) note to figure 10?5 : (1) figures 10?4 and 10?5 assume that the address stays constant throughout and that the outputs are not registered. mixed-port read-during-write mode mixed-port read-during-write mode occurs when a ram block in simple or true dual-port mode has one port reading and the other port writing to the same address location using th e same clock. in apex ii and apex 20k designs, the esb outputs the old data in the first half of the clock cycle and the new data in the second half of the clock cycle, as indicated by figure 10?6 . figure 10?6. mixed-port feed-through behavior (apex ii & apex 20k devices) note (1) note to figure 10?6 : (1) figure 10?6 assumes that outputs are not registered. stratix and stratix gx device ram outputs the new data on the rising edge of the clock cycle immediately af ter the data was written. when you use stratix and stratix gx m512 and m4k blocks, you can choose whether to output the old data at the targeted address or output a don?t care value during the clock cycle when the ne w data is written. m-ram blocks inclock data_in wren data_out a b a old inclock port a data_in port a wren port b data_out a b a old port b wren b 10?12 altera corporation stratix device handbook, volume 2 july 2005 trimatrix memory always output a don?t care value. figures 10?7 and 10?8 show the feed- through behavior of the mixed-port mode. you can use the altsyncram megafunction to set the output behavior during mixed-port read-during- write mode. figure 10?7. mixed-port feed-through behavior (old_data) note (1) note to figure 10?7 : (1) figures 10?7 and 10?8 assume that the address stays constant throughout and that the outputs are not registered. figure 10?8. mixed-port feed-through behavior (dont_care) note (1) note to figure 10?8 : (1) figures 10?7 and 10?8 assume that the address stays constant throughout and that the outputs are not registered. memory megafunctions to convert ram and rom originally targeting the apex ii or apex 20k architecture to stratix or stratix gx memory, specify stratix or stratix gx as the target family in the megawizard plug-in manager. the software inclock port a data_in port a wren port b data_out ab a old port b wren b address q address a and address b inclock port a data_in port a wren port b data_out ab b unknown port b wren address q address a and address b altera corporation 10?13 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices updates the memory module for the stratix or stratix gx architecture and instantiates the new synchr onous memory megafunction, altsyncram , which supports both ram and rom bloc ks in the stratix and stratix gx architectures. fifo conditions first-in first-out (fifo) functionality is slightly different in stratix and stratix gx devices compared to apex ii and apex 20k devices. stratix and stratix gx devices do not support simultaneous reads and writes from an empty fifo buffer. also, st ratix and stratix gx devices do not support the lpm_showahead parameter when targeting a fifo buffer because the trimatrix memory blocks are synchronous. the lpm_showahead parameter for apex ii and apex 20k devices puts the fifo buffer in ?read-acknowledge? mo de so the first data written into the fifo buffer immediately flows thro ugh to the output. other than these two differences, all apex ii and apex 20k fifo functions are fully compatible with the stratix and stratix gx architectures. design migration mode in quartus ii software the quartus ii software features a migration mode for simplifying the process of converting apex ii an d apex 20k memory functions to the stratix or stratix gx architecture. if the design can use the stratix or stratix gx altsyncram megafunction as a replacement for a previous apex ii or apex 20k memory function while maintaining functionally similar behavior, the quartus ii soft ware automatically converts the memory. the software produces a warning message during compilation reminding you to verify that th e design migrated correctly. for memory blocks with all inputs re gistered, the existi ng megafunction is converted to the new altsyncram megafunction. the software generates a warning when the altsyncram megafunction is incompatible. for example, a ram block with all inputs re gistered except the read enable compiles with a wa rning message indi cating that the read-enable port is registered. you can suppress warning messages for the entire project or for individual memory blocks by setting the suppress_memory_conversion_warnings parameter to ?on? as a global parameter by selecting assignment organizer (tools menu). in the assignment organizer window, click parameters in the assignment categories box. type suppress_memory_conversion_warnings in the assignment name box and type on in the assignment setting box. to suppress these warning messages on a per-memory-instance basis, set the suppress_memory_conversion_warnings parameter in the assignment organizer to ?on? for the memory instance. 10?14 altera corporation stratix device handbook, volume 2 july 2005 trimatrix memory if the functionality of the apex ii or apex 20k memory megafunction differs from the altsyncram functionality and at least one clock feeds the memory megafunction, the quartu s ii software converts the apex ii or apex 20k memory megafunction to the stratix or stratix gx altsyncram megafunction. this conversion is useful for an initial evaluation of how a design might perf orm in stratix or stratix gx devices and should only be used for evaluation purposes. during this process, the quartus ii software generates a warning that the conversion may be functionally incorrect and timing re sults may not be accurate. since the functionality may be incorrect and the compilation is only intended for comparative purposes, the quartus ii software does not generate a programming file. a functionally correct conversion requires manually instantiating the altsyncram megafunction and ma y require additional design changes. if the previous memory function does not have a clock (fully asynchronous), the fitting-evaluatio n conversion results in an error message during compilation and do es not successfully convert the design. f see an 210: converting memory from asynchronous to synchronous for stratix & stratix gx designs for more information. table 10?5 summarizes the possible sc enarios when using design migration mode and the resulting behavior of the quartus ii software. the most common cases where design-migration mode may have difficulty converting the existing design are when: a port is reading from an address th at is being written to by another port (mixed-port read-during-write mode). if both ports are using the same clock, the read port in stratix and stratix gx devices do not see the new data until the next cl ock cycle, after the new data was written. altera corporation 10?15 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices there are differences in power- up behavior between apex ii, apex 20k, and stratix and stratix gx devices. you should manually account for these differences to maintain desired operation of the system. table 10?5. migration mode summary memory configuration conditions possible instantiated megafunctions quartus ii warning message(s) programming file generated single-port all inputs are registered. altram altrom lpm_ram_dq lpm_ram_io lpm_rom power-up differences. (1) ye s multi-port (two-, three-, or four-port functions) all inputs are registered. altdpram lpm_ram_dp altqpram alt3pram power-up differences. mixed-port read- during- write. (1) ye s dual-port read-enable ports are unregistered. other inputs registered. altdpram lpm_ram_dp altqpram alt3pram power-up differences. mixed-port read- during- write. read enable will be registered. (1) ye s dual-port any other unregistered port except read-enable ports. clock available. altdpram lpm_ram_dp altqpram alt3pram compile for fitting- evaluation purposes. no single-port at least one registered input. clock available. altram lpm_ram_dq lpm_ram_io compile for fitting- evaluation purposes. no no clock no clock. altram altrom altdpram altqpram alt3pram altdpram lpm_ram_dq lpm_ram_io lpm_rom lpm_ram_dp lpm_ram_dp error ? no conversion possible. no note to table 10?5 : (1) if the suppress_memory_counversion_warnings parameter is turned on, the quartus ii software does not issue these warnings. 10?16 altera corporation stratix device handbook, volume 2 july 2005 dsp block dsp block stratix and stratix gx device dsp blocks outperform le-based implementations for common dsp func tions. each dsp block contains several multipliers that can be configur ed for widths of 9, 18, or 36 bits. depending on the mode of operation, these multipliers can optionally feed an adder/subtractor/accumulator or summation unit. you can configure the dsp block?s input registers to efficiently implement shift registers for serial input sharing, eliminating the need for external shift registers in les. you can add pipeline registers to the dsp block for accelerated operation. regi sters are available at the input and output of the multiplier, and at the output of the adder/subtractor/accumulator or summation block. dsp blocks have four modes of operation: simple multiplier mode multiply-accumulator mode two-multipliers adder mode four-multipliers adder mode associated megafunctions are availa ble in the quartus ii software to implement each mode of the dsp block. dsp block megafunctions you can use the lpm_mult megafunction to configure the dsp block for simple multiplier mode. you can set the lpm_mult multiplier implementation option in the megawizard plug-in manager to either use the default implementation, esbs, or the dsp blocks. if you select the use default option, the compiler first attemp ts to place the multiplier in the dsp blocks. however, under certain conditions, the compiler may implement the multiplier in les. the placement depends on factors such as dsp block resource consumption, th e width of the multiplier, whether an operand is a constant, and other options chosen for the megafunction. stratix and stratix gx devices do not support the use esbs option. if you select this option, the quartus ii softwa re tries to place the multiplier in unused dsp blocks. you can recompile apex ii or apex 20k designs using the lpm_mult megafunction for stratix and stra tix gx devices in the quartus ii software without changing the mega function. this makes converting lpm_mult megafunction designs to st ratix or stratix gx devices straightforward. altera corporation 10?17 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices apex ii and apex 20k designs use pipeline stages to improve registered performance of le-based multipliers at the expense of latency. however, you may not need to use pipeline stages when targeting stratix and stratix gx high-speed dsp blocks. th e dsp blocks offer three sets of dedicated pipeline registers. therefore, altera recommends that you reduce the number of pipeline stages to three or fewer and implement them in the dsp blocks. additional pipeline stages are implemented in les, which add latency without pr oviding any performance benefit. for example, you can configure a dsp block for 36 36-bit multiplication using the lpm_mult megafunction. if you specify two pipeline stages, the software uses the dsp block inpu t and pipeline registers. if you specify three pipeline stages, the soft ware places the third pipeline stage in the dsp block output registers. this design yields the same performance with three pipeline stag es because the critical path for a 36 36-bit operation is within the multip lier. with four or more pipeline stages, the device inefficiently uses le resources for the additional pipeline stages. therefore, if multiplier modules in apex ii or apex 20k designs are converted to stratix or stratix gx designs and do not require the same number of pipeline stages , the surrounding circuitry must be modified to preserve the original functionality of the design. a design with multipliers feeding an accumulator can use the altmult_accum (mac) megafunction to set th e dsp block in multiply- accumulator mode. if the apex ii or apex 20k design already uses le- based multipliers feeding an accumul ator, the quartus ii software does not automatically instantiate the new altmult_accum (mac) megafunction. therefore, you sh ould use the megawizard plug-in manager to instantiate the altmult_accum (mac) megafunction. you can also use leonardospectrum ? or synplify synthesis tools, which have dsp block inference support, to instantiate the megafunction. designs that use multipliers feeding into adders can instantiate the new altmult_add megafunction to configur e the dsp blocks for two- multipliers adder or four-multipliers adder mode. you can also use the altmult_add megafunction for stand-alone multipliers to take advantage of the dsp blocks features such as dynamic sign control of the inputs and the input shift register connections. these features are not accessible through the lpm_mult megafunction. if your apex ii or apex 20k designs already use multipli ers feeding an adder/subtractor, the quartus ii software does not automatically infer the new altmult_add megafunction. therefore, yo u should step through the megawizard plug-in manager to instantiate the new altmult_add megafunction or use leonardospectr um or synplify synthesis tools, which have dsp block inference support. 10?18 altera corporation stratix device handbook, volume 2 july 2005 plls & clock networks furthermore, the altmult_add and altmult_accum (mac) megafunctions are only available for stratix and stratix gx devices because these megafunctions target stratix and stratix gx dsp blocks, which are not available in other devi ce families. if you attempt to use these megafunctions in designs that ta rget other altera device families, the quartus ii software reports an error message. use lpm_mult and an lpm_add_sub or an altaccumulate megafunction for similar functionality in other device families. if you use a third-party synthesis tool, you may be able to avoid the megafunction conversion process. leonardospectrum and synplify provide inference support for lpm_mult , altmult_add , and altmult_accum (mac) to use the dsp blocks. if your design does not require you to implement all the multipliers in dsp blocks, you must manually set a global parameter or a parameter for each instance to force the tool to implement the lpm_mult megafunction in les. depending on the synthesis tools, inference of dsp blocks is handled differently. f for more information about using ds p blocks in stratix and stratix gx devices, see the dsp blocks in stratix & stratix gx devices chapter of the stratix device handbook . plls & clock networks stratix and stratix gx devices prov ide exceptional clock management with a hierarchical clock network and up to four enhanc ed phase-locked loops (plls) and eight fast plls ve rsus the four general-purpose plls and four true-lvds tm plls in apex ii devices. by providing superior clock interfacing, numero us advanced clocking fe atures, and significant enhancements over apex ii an d apex 20k plls, the stratix and stratix gx device plls increase system performance and bandwidth. clock networks there are 16 global clock networks av ailable throughout each stratix or stratix gx device as well as two fast regional and four regional clock networks per device quadrant, resulting in up to 40 unique clock networks per device. the increased number of dedicated clock resources available in stratix and stratix gx devices eliminate the need to use general-purpose i/o pi ns as clock inputs. stratix ep1s25 and smaller devices have 16 dedicated clock pins and ep1s30 and larger devices have four additional clock pins to feed various clocking networks. in comparison, ap ex ii devices have eight dedicated clock pins and apex 20ke and apex 20kc devices have four dedicated clock pins. altera corporation 10?19 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices the dedicated clock pins in stratix and stratix gx devices can feed the pll clock inputs, the gl obal clock networks, and the regional clock networks. pll outputs and internally -generated signals can also drive the global clock network. these glob al clocks are available throughout the entire device to clock all device resources. stratix and stratix gx devices are divided into four quadrants, each equipped with four region al clock networks. the regional clock network can be fed by either the dedicated cloc k pins or the pll outputs within its device quadrant. the regional cloc k network can only feed device resources within its particular device quadrant. each stratix and stratix gx device provides eight dedicated fast clock i/o pins fclk[7..0] versus four dedicated fast i/o pins in apex ii and apex 20k devices. the fast regi onal clock network can be fed by these dedicated fclk[7..0] pins or by the i/o interconnect. the i/o interconnect allows internal logic or any i/o pin to drive the fast regional clock network. the fast regional cl ock network is available for general- purpose clocking as well as high fan-out control signals such as clear, preset, enable, trdy and irdy for pci applications, or bidirectional or output pins. ep1s25 and smaller devices have eight fast regional clock networks, two per device quadrant. the quadrants in ep1s30 and larger devices are divided in half, and each half-quadrant can be clocked by one of the eight fast regional networks. additionally, each fast regional clock network can drive its neighboring half-quadrant (within the same device quadrant). plls table 10?6 highlights stratix and stra tix gx pll enhancements to existing apex ii, apex 20ke and apex 20kc pll features. table 10?6. stratix & stratix gx p ll vs. apex ii, apex 20ke & apex 20kc pll features (part 1 of 2) feature stratix & stratix gx apex ii plls apex 20ke & apex 20kc plls enhanced plls fast plls number of plls two (ep1s30 and smaller devices); four (ep1s40 and larger devices) (9) four (ep1s25 and smaller devices); eight (ep1s30 and larger devices) (10) four general- purpose plls and four lvds plls up to four general- purpose plls. up to two lvds plls. (1) minimum input frequency 3 mhz 15 mhz 1.5 mhz 1.5 mhz maximum input frequency 250 to 582 mhz (2) 644.5 mhz (11) 420 mhz 420 mhz 10?20 altera corporation stratix device handbook, volume 2 july 2005 plls & clock networks enhanced plls stratix and stratix gx devices provide up to four enhanced plls with advanced pll features. in addition to the feature changes mentioned in table 10?6 , stratix and stratix gx device plls include many new, internal clock outputs per pll 63 (3) 22 external clock outputs per pll four differential/eight singled-ended or one single-ended (4) ye s (5) 11 phase shift down to 160-ps increments (6) down to 125-ps increments (6) 500-ps to 1-ns resolution 0.4- to 1-ns resolution time shift 250-ps increments for 3 ns (7) no no no m counter values 1 to 512 1 to 32 1 to 160 2 to 160 n counter values 1 to 512 n/a 1 to 16 1 to 16 pll clock input sharing no yes yes yes t1/e1 rate conversion (8) no no yes yes notes to table 10?6 : (1) ep20k200e and smaller devices only have two genera l-purpose plls. ep20k400e and larger devices have two lvds plls and four general-purpose plls. for more information, see an 115: using the clocklock & clockboost pll features in apex devices . (2) the maximum input frequency for stra tix and stratix gx enhanced plls depe nds on the i/o standard used with that input clock pin. for mo re information, see the stratix device family data sheet section of the stratix device handbook, volume 1 or the stratix gx device fa mily data sheet section of the stratix gx device handbook, volume 1 . (3) fast plls 1, 2, 3, and 4 have three internal clock output ports per pll. fast plls 7, 8, 9, and 10 have two internal clock output ports per pll. (4) every stratix device has two enhanced plls with ei ght single-ended or four differential outputs each. two additional enhanced plls in ep1s80, ep1s60, and ep 1s40 devices each have one single-ended output. (5) any i/o pin can be driven by the fast pll global or regional outputs as an external clock output pin. (6) the smallest phase shift unit is determined by the voltage-cont rolled oscillator (vco) period divided by 8. (7) there is a maximum of 3 ns between any two pll clock outputs. (8) the t1 clock frequency is 1.544 mhz and the e1 clock frequency is 2.048 mhz, whic h violates the minimum clock input frequency requirement of the stratix pll. (9) stratix gx ep1sgx10 and ep1sgx25 contain two. ep1sgx40 contains four. (10) stratix gx ep1sgx10 and ep1sgx25 contain two. ep1sgx40 contains four. (11) stratix gx supports clock rates of 1 gbps using dpa. table 10?6. stratix & stratix gx p ll vs. apex ii, apex 20ke & apex 20kc pll features (part 2 of 2) feature stratix & stratix gx apex ii plls apex 20ke & apex 20kc plls enhanced plls fast plls altera corporation 10?21 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices advanced features to improve sy stem timing management and performance. table 10?7 shows some of the new features available in stratix and stratix g x enhanced plls. fast plls stratix and stratix gx fast plls ar e similar to the apex ii true-lvds plls in that the w setting, which governs the relationship between the clock input and the data rate, and the j setting, which controls the width table 10?7. stratix & stratix gx enhanced pll features feature description programmable duty cycle (1) allows variable duty cycle for each pll clock output. pll clock outputs can feed logic array (1) allows the pll clock outputs to feed data ports of registers or combinatorial logic. pll locked output can feed the logic array (1) allows the pll locked port to feed data ports of registers or combinatorial logic. multiplication allowed in zero-delay buffer mode or external feedback mode the pll clock outputs can be a multiplied or divided down ratio of the pll input clock. programmable phase shift allowed in zero-delay buffer mode or external feedback mode (2) the pll clock outputs can be phase shifted. the phase shift is relative to the pll clock output. phase frequency detector (pfd) disable allows the vco to operate at its last set control voltage and frequency with some long term drift. clock output disable (3) pll maintains lock with output clocks disabled. (4) programmable lock detect & gated lock holds the lock signal low for a programmable number of input clock cycles. dynamic clock switchover enables the pll to switch between two reference input clocks, either for clock redundancy or dual-clock domain applications. pll reconfiguration allows the counters and delay elem ents within the pll to be reconfigured in real- time without reloading a programmer object file ( .pof ). programmable bandwidth provides advanced control of the pll bandwidth by using the programmable control of the pll loop characteristics. spread spectrum modulates the target freque ncy over a frequency range to reduce electromagnetic interfer ence (emi) emissions. notes to table 10?7 : (1) these features are also available in fast plls. (2) in addition to the delay chains at each counter, you can specify the programmable phase shift for each pll output at fine and coarse levels. (3) each pll clock output has an associated clock enable signal. (4) if the pll is used in external feedba ck mode, the pll will need to relock. 10?22 altera corporation stratix device handbook, volume 2 july 2005 plls & clock networks of the high-speed differential i/o da ta bus, do not have to be equal. additionally, stratix and stratix gx fast plls offer up to three clock outputs, two multiplied high-s peed pll clocks to drive the serializer/deserializer (serdes) bloc k and/or an external pin, and a low-speed clock to drive the logic arra y. you can use fast plls for both high-speed interfacing and for general-purpose pll applications. table 10?8 shows the differences between stratix and stratix gx fast plls and apex ii and apex 20k true-lvds plls. the stratix and stratix gx fast pll vco frequency range is 300 to 840 mhz, and the apex ii true-lvds pll vco frequency range is 200 mhz to 1 ghz. therefore, you must update de signs that use a data rate of less than 300 megabits per second (mbps) to use the enhanced plls and m512 ram blocks in serdes bypass mode. additionally, you must update designs that use a data rate faster than 840 mbps. altpll megafunction altera recommends that you replace instances of the altclklock megafunction with the altpll megafunction to take advantage of new stratix and stratix gx pll features. although in most cases you can retarget your apex ii or apex 20k design to a stratix or stratix gx table 10?8. stratix & stratix gx fast pll vs . apex ii & apex 20k true-lvds pll feature stratix & stratix gx apex ii apex 20ke apex 20kc number of fast plls or true- lvds plls (1) four (ep1s25 and smaller devices) fast plls eight (ep1s30 and larger devices) fast plls (4) four true-lvds plls two true-lvds plls (2) number of channels per transmitter/receiver block 20 18 18 vco frequency 300 to 840 mhz (5) 200 mhz to 1ghz 200 to 840 mhz minimum input frequency m = 4, 5, 6 300 ? m mhz 50 mhz 50 mhz m = 4 (3) minimum input frequency m = 7, 8, 9, 10 300 ? m mhz 30 mhz 30 mhz m = 7, 8 (3) notes to table 10?8 : (1) you can also use stratix and stratix gx device fast plls for general-pu rpose pll applications. (2) ep20k400e and larger devices have two true-lvds plls. (3) in apex 20ke and apex 20kc devices, m = 4, 7, or 8. (4) stratix gx ep1sgx10 and ep1sgx25 contain two. ep1sgx10 contains four. (5) stratix gx supports a frequency range of 300?1000 mhz (using dpa). altera corporation 10?23 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices device with the altclklock megafunction, there are specific cases where you must use the altpll megafunction, as explained in this section. in the megawizard plug-in manager, select the altpll megafunction in the i/o directory from the available megafunctions box (see figure 10?9 ). the altclklock megafunction is also available from the quartus ii software for backward comp atibility, but instantiates the new altpll megafunction when targeting stratix or stratix gx devices. the quartus ii compiler automatically selects whether the altpll module uses either an enhanced pll or a fast pll based on the design?s pll needs and the feature requirements of each pll. figure 10?9. altpll megafunction select ion in the megawizard plug-in manager you can compile apex ii, apex 20ke, and apex 20kc designs using the altclklock megafunction in normal mo de for stratix and stratix gx devices without updating the me gafunction. however, you should replace the altclklock megafunction with the altpll megafunction. if the quartus ii software cannot implement the requested clock multiplication and division of the pll, the compiler reports an error message with the appropriate reason stated. 10?24 altera corporation stratix device handbook, volume 2 july 2005 plls & clock networks apex ii, apex 20ke, and apex 20kc devices have only one external clock output available per pll. theref ore, when retargeting an apex ii, apex 20ke, or apex 20kc design that uses plls in zero delay buffer mode or external feedback mode to a stratix or stratix gx device, you should replace instances of the altclklock megafunction. if an apex ii, apex 20ke, or apex 20kc altclklock module only uses one pll clock output (internal or external) and is compiled to target a stratix or stratix gx device, the design compiles successfully with a warning that the design uses the stratix or stratix gx pll external clock output, extclk0 . however, if the apex ii, apex 20ke, or apex 20kc pll has more than one pll clock output, yo u must replace instances of the altclklock megafunction with the altpll megafunction because the quartus ii compiler does not know wh ich pll clock output is fed to an external output pin or fed back to the stratix or stratix gx device fbin pin. for example, if an apex ii, apex 20ke, or apex 20kc design with an altclklock megafunction uses the clock0 output port to feed the external clock output pin and the clock1 output port to feed the internal logic array, the quartus ii software generates an error during compilation and you must use the megawizard plug-in manager to instantiate the altpll megafunction. by using the altpll megafunction, you can choose which of the four external clock outputs to use and take advantage of the new stratix and stratix gx pll features now available in the zero delay buffer mode or external feedback mode. timing analysis when the quartus ii software performs a timing analysis for apex ii, apex 20ke, or apex 20kc designs, pll clock settings override the project clock settings. however, duri ng timing analysis for stratix and stratix gx designs using plls, the proj ect clock settings override the pll input clock frequency and duty cycl e settings. the megawizard plug-in manager does not use the project clock settings to determine the altpll parameters. this saves time with designs that use features such as clock switchover or pll reconfiguration because the quartus ii software can perform a timing analysis without reco mpiling the design. it is important to note the following: a warning during compilation reports that the project clock settings overrides the pll clock settings. the project clock setting overrides the pll clock settings for timing- driven compilation. the compiler will check the lock fr equency range of the pll. if the frequency specified in the project cl ock settings is outside the lock frequency range, the pll clock settings will not be overridden. performing a timing analysis with out recompiling your design does not change the programming files. you must recompile your design to update the programming files. altera corporation 10?25 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices a default required f max setting does not override the pll clock settings. only individual clock settings override the pll clock settings. therefore, you can enter different project clock settings corresponding to new pll settings and accelerate timing analysis by eliminating a full compilation cycle. f for more information about using st ratix and stratix gx plls, see the general-purpose plls in stratix & stratix gx devices chapter . i/o structure the stratix and stratix gx i/o element (ioe) architec ture is similar to the apex ii architecture, with a total of si x registers and a latch in each ioe. the registers are organized in three sets: two output registers to drive a single or double-data rate (ddr) ou tput path, two input registers and a latch to support a single or ddr in put path, and two output enable registers to enhance clock-to-output enable timing or for ddr sdram interfacing. a new synchronous reset signal is available to each of the three sets of registers for preset or clear, or neither. in addition to the advanced ioe architecture, the st ratix and stratix gx ioe features dedicated circuitry for external ra m interfacing, new i/o standards, differential on-chip termination, and high-speed differential i/o standard support. external ram interfacing the advanced stratix and stratix gx ioe architecture includes dedicated circuitry to interface with extern al ram. this ci rcuitry provides enhanced support for external high-s peed memory devices such as ddr sdram and fcram. the ddr sdram interface uses a bidirectional signal, dqs , to clock data, dq , at both the transmitting and receiving device. stratix and stratix gx devices transmit the dqs signal with the dq data signals to minimize clock to data skew. stratix and stratix gx devices in clude groups of programmable dqs and dq pins, in the top and bottom i/o banks of the device. each group consists of a dqs pin that supports a fixed number of dq pins. the number of dq pins depends on the dq bus mode. when using the external ram interfacing circuitry, the dqs pin drives a dedicated clock network that feeds the dq pins residing in that bank. the stratix and stratix gx ioe has programmable delay chains that can phase shift the dqs signal by 90 or 72 to ensure data is sampled at the ap propriate point in time. therefore, the stratix and stratix gx devices make full use of the ioes, and remove the need to build the in put data path in the logic array. you can make these i/o assignments in the qu artus ii assignment organizer. 10?26 altera corporation stratix device handbook, volume 2 july 2005 i/o structure f for more information on extern al ram interfacing, see the stratix device family data sheet section of the stratix device handbook, volume 1 or the stratix gx device family data sheet in the stratix gx device family handbook, volume 1. i/o standard support the stratix and stratix gx devices suppo rt all of the i/o standards that apex ii and apex 20k devices support, including high-speed differential i/o standards such as lvds, lvpecl, pcml, and hypertransport tm technology, differential hstl on input and output clocks, and differential sstl on output clocks. stratix and stratix gx devices also introduce support for sstl -18 class i & ii. similar to apex ii devices, stratix and stratix gx de vices only support certain i/o standards in designated i/o banks. in addition, vref pins are dedicated pins in stratix and stratix gx devices and now support up to 40 input pins. f for more information about i/o standard support in stratix and stratix gx devices, see the selectable i/o standards in stratix & stratix gx devices chapter . high-speed differential i/o standards stratix and stratix gx devices support high-speed differential interfaces at speeds up to 840 mbps using high-s peed plls that drive a dedicated clock network to the serdes. each fast pll can drive up to 20 high- speed channels. stratix and stratix gx devices use enhanced plls and m512 ram blocks to provide up to 420 mbps performance for serdes bypass clock interfacing. there is no restriction on the number of channels that can be clocked using this scenario. stratix and stratix gx devices have a different number of differential channels than apex ii devices. tables 10?9 and 10?10 highlight the number of differential channels supported in stratix and stratix gx devices. table 10?9. number of dedi cated differentia l channels in stratix devices (part 1 of 2) note (1) device pin count number of receiver channels number of transmitter channels ep1s10 672 36 36 780 44 44 altera corporation 10?27 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices ep1s20 672 50 48 780 66 66 ep1s25 672 58 56 780 66 70 1,020 78 78 ep1s30 780 66 70 956 80 80 1,020 80 80 22 ep1s40 956 80 80 1,020 80 80 10 10 1,508 80 80 10 10 ep1s60 956 80 80 1,020 80 80 10 12 1,508 80 80 36 36 ep1s80 956 80 80 040 1,508 80 80 56 72 note to table 10?9 : (1) for information on channel speeds, see the stratix device family data sheet section of the stratix device handbook, volume 1 and the high-speed differential i/o interfaces chapter in the stratix device handbook, volume 2 . table 10?9. number of dedi cated differentia l channels in stratix devices (part 2 of 2) note (1) device pin count number of receiver channels number of transmitter channels 10?28 altera corporation stratix device handbook, volume 2 july 2005 i/o structure the differential i/o within strati x gx also provides dynamic phase alignment (dpa). dpa enables the di fferential i/o to operate up to 1 gbps per channel. dpa automatically and continuously tracks fluctuations caused by system variations and self-adjusts to eliminate the phase skew between the multiplied cl ock and the serial data. the block contains a dynamic phase selector for phase detection and selection, a serdes, a synchronizer, and a data re aligner circuit. you can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel by using a separate deserializer. if you compile an apex ii lvds design that uses clock-data synchronization (cds) for a stratix or stratix gx device, the quartus ii software issues a warning during compilation that stratix and stratix gx devices do not support cds. stratix and stratix gx devices offer a flexible solution using new byte realignment circuitry to correct for byte misalignment by shifting, or slipping, data bits. stratix and st ratix gx devices activate the byte realignment circuitry wh en an external pin ( rx_data_align ) or an internal custom-made state machine asserts the sync node high. apex ii, apex 20ke, and apex 20kcdevices have a dedicated transmitter clock output pin ( lvdstxoutclk ). in stratix and stratix gx devices, a transmitter dataout channel with an lvds clock (fast clock) generates the transmitter clock outp ut. therefore, you can drive any table 10?10. number of dedicated di fferential channels in stratix gx devices note (1) device pin count number of transceivers number of source- synchronous channels ep1sgx10 c 672 4 22 ep1sgx10 d 672 8 22 ep1sgx25 c 672 4 39 ep1sgx25 d 672/1,020 8 39 ep1sgx25 f 1,020 16 39 ep1sgx40 d 1,020 8 45 ep1sgx40 g 1,020 20 45 note to table 10?10 : (1) for information on channel speeds, see the stratix gx device family data sheet section of the stratix gx device handbook, volume 1 and the high-speed source-synchronous differential i/o interfaces in stratix gx devices chapter of the stratix gx device handbook, volume 2 . altera corporation 10?29 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices channel as an output clock to an i/o pin, not just dedi cated clock output pins. this solution offers better vers atility to address various applications that require more complex clocking schemes. f for more information on differential i/o support, data realignment, and the transmitter clock output in stra tix and stratix gx devices, see the high-speed differenti al i/o interfaces in stratix devices chapter. altlvds megafunction to take full advantage of the high -speed differential i/o standards available in stratix and stratix gx devices, you should update each instance of the altlvds megafunction in apex ii, apex 20ke, and apex 20kc designs. in the megawizar d plug-in manager, choose the altlvds megafunction, select stratix or stratix gx as the target device family, update the megafunction , and recompile your design. the altlvds megafunction supports new stratix and stratix gx parameters that are not available for apex ii, apex 20ke, and apex 20kc devices. tables 10?11 and 10?12 describe the new parameters for the lvds receiver and lvds transmitter, respectively. table 10?11. new altlvds parameters for stratix lvds receiver note (1) parameter function input_data_rate (2) specifies the data rate in mbps. this parameter replaces the multiplication factor w . inclock_data_alignment indicates the alignment of rx_inclk and rx_in data. rx_data_align drives the data alignment port of the fast pll and enables byte realignment circuitry. registered_data_align_input registers the rx_data_align input port to be clocked by rx_outclock . common_rx_tx_pll (3) indicates the fast pll can be shared between receiver and transmitter applications. table 10?12. new altlvds parameters for stratix lvds transmitter (part 1 of 2) note (1) parameter function output_data_rate (2) specifies the data rate in mbps. this parameter replaces the multiplication factor w . inclock_data_alignment indicates the alignment of tx_inclk and tx_in data. outclock_alignment specifies the alignment of tx_outclock and tx_out data. 10?30 altera corporation stratix device handbook, volume 2 july 2005 configuration above the standard i/o offered by apex ii, apex 20k, and stratix devices, stratix gx devices provide up to 20 3.175 gbps transceivers. the transceivers provide high-speed serial links for chip-to-chip, backplane, and line-side connectivity and support a number of the emerging high-speed protocols. you can find more information in the stratix gx family data sheet in the stratix gx family handbook, volume 1 . configuration the stratix and stratix gx devices supports all current configuration schemes, including the use of enhanc ed configuration devices, passive serial (ps), passive parallel asynchronous (ppa), fast passive parallel (fpp), and jtag. stratix and stratix gx devices also provide a number of new configuration enhancements that you can take advantage of when migrating apex ii and apex 20k designs to stratix and stratix gx devices. configuration speed & schemes you can configure stratix and stratix gx devices at a maximum clock speed of 100 mhz, which is fast er than the 66-mhz and 33-mhz maximum configuration speeds for ap ex ii and apex 20k devices, respectively. similar to apex ii device s, you can use 8-bit parallel data to configure stratix and stratix gx devices (the target device can receive byte-wide configuration data on each clock cycle) significantly speeding up configuration times. you can select a configuratio n scheme based on how the msel pins are driven. stratix and stratix gx devices have three msel pins (apex ii and apex 20k devices have two msel pins) for determining the configuration scheme. registered_input specifies the clock source for th e input synchroniza tion registers, which can be either tx_inclock or tx_coreclock . used only when the registered inputs option is selected. common_rx_tx_pll (3) indicates the fast pll can be shared between receiver and transmitter applications. notes to tables 10?11 and 10?12 : (1) you can specify these parameters in the megawizard plug-in manager. (2) you must specify a data rate in the megawizard plug-in manager instead of a w factor. (3) the same fast pll can be used to clock both the receiv er and transmitter only if both are running at the same frequency. table 10?12. new altlvds parameters for stratix lvds transmitter (part 2 of 2) note (1) parameter function altera corporation 10?31 july 2005 stratix device handbook, volume 2 transitioning apex designs to stratix & stratix gx devices f for more information about stra tix and stratix gx configuration schemes, see the configuring stratix & stratix gx devices chapter . remote update configuration the apex 20k device family introduc ed the concept of remote update configuration, where you could send the apex 20k device new configuration files from a remote so urce and the device would store the files in flash memory and reconfigure itself with the new configuration data. the stratix and stratix gx de vices enhance suppo rt for remote update configuration with new, dedica ted circuitry to handle and recover from errors. if an error occurs either during device configuration or in user mode, this new circuitry reconfigures the stratix or stratix gx device to a known state. additionally, the stratix and stratix gx devices have a user watchdog timer to ensure th e application configuration data executes successfully during user mo de. user logic must continually reset this watchdog timer in order to validate that the application configuration data is functioning properly. f for more information about how to use the remote and local update modes, see the remote system configuration with stratix & stratix gx devices chapter . jtag instruction support stratix and stratix gx devices suppo rt two new jtag instructions, pulse_nconfig and config_io . the pulse_nconfig instruction emulates pulsing the nconfig signal low to trigger reconfiguration, while the actual nconfig pin on the device is unaffected. the config_io instruction allows you to us e the jtag chain to configure i/o standards for all pins. because this instruction interrupts device configuration, you should reconfigur e the stratix or stratix gx device after you finish jtag testing to ensure proper device operation. table 10?13 compares jtag instruction support in stratix and stratix gx devices versus apex ii and apex 20k devices. for further information about the supported jtag instructions, see the appropriate device family data sheet. table 10?13. jtag instruction support (part 1 of 2) jtag instruction stratix apex ii apex 20k sample/preload vvv extest vvv bypass vvv usercode vvv 10?32 altera corporation stratix device handbook, volume 2 july 2005 conclusion conclusion the stratix and stratix gx devices exte nd the advanced features available in the apex ii and apex 20k device families to deliver a complete system-on-a-programmable-chip (sop c) solution. by following these guidelines, you can easily transition current apex ii and apex 20k designs to take advantage of the ne w features available in stratix and stratix gx devices. idcode vvv icr instructions vvv signaltap tm ii instructions vvv highz vv clamp vv pulse_nconfig v config_io v table 10?13. jtag instruction support (part 2 of 2) jtag instruction stratix apex ii apex 20k altera corporation section vi?1 section vi. system configuration & upgrades this section describes configuration and remote system upgrade. this section also provides configuration information for all of the supported configuration schemes for stratix ? devices. these configuration schemes use either a microprocessor, configuration device, or download cable. there is detailed information on how to design with altera ? enhanced configuration devices which includes information on how to manage multiple configuration files and access the on-chip flash memory space. the last chapter shows you how to perform remote and local upgrades for your designs. this section contains the following chapters: chapter 11, configuring stratix & stratix gx devices chapter 12, remote system configur ation with strati x & stratix gx devices f for information on altera enhanced configuration devices, see the enhanced configuration devices (e pc4, epc8 & epc16) data sheet chapter in the configuration handbook, volume 2 . section vi?2 altera corporation system configuration & upgrades stratix device handbook, volume 2 revision history the table below shows th e revision history for chapters 11 through 12 . chapter date/version changes made 11 july 2005, v3.2 updated ?porsel pins? and ?nio_pullup pins? sections. updated ?fpp configuration using an enhanced configuration device? section. updated ?ppa configuration? section. september 2004, v3.1 corrected spelling error. april 2004, v3.0 in the ?porsel pins? section and the ?nio_pullup pins? section, several pull-down resistors were changed to pull-up resistors. updated notes in figure 11?3 . two vertical v cc lines removed in figures 11?12 to 11?14 . three paragraphs added regarding the conf_done and init_done pins on page 13-18. value in note 1 changed in tables 11?8 and 11?9 . deleted reference to as in table 11?15 because stratix does not support as mode. text added before callout of figure 11?7 . july 2003, v2.0 updated remote/local update ppa typical use description on page 11-1. updated vccsel pins section on page 11-3. updated figures to use 10k resistors throughout for configuration control signals. updated text on page 11-23 to tell how to connect a microprocessor to nstatus. figure 11?19 , note 3. updated table 11?12 . added note 6 to figure 11?21 and the text below the figure describing the nce pin. updated definitions for clkusr, and jtag pins in table 11?16 . 12 september 2004, v3.1 editorial corrections. april 2004, v3.0 the input file in figure 12?22 was changed to remote_update_initial_pgm.pdf. title in figure 12?23 was changed from local ... to remote update partial programming file generation. rearranged the ?quartus ii software support? section. july 2003, v2.0 added altremote_update megafunction section on pages 12-18 to 12- 21. altera corporation 11?1 july 2005 11. configuring stratix & stratix gx devices introduction you can configure stratix ? and stratix gx devices using one of several configuration schemes. all configuration schemes use either a microprocessor, configuration device, or a download cable. see table 11?1 . this chapter discusses how to configure one or more stratix or stratix gx devices. it should be used toge ther with the fo llowing documents: masterblaster serial /usb communication s cable data sheet usb blaster usb port download ca ble development tools data sheet byteblaster ii parallel port download cable data sheet byteblastermv parallel port download cabl e data sheets configuration devices for sram -based lut devices data sheet enhanced configuration devices (e pc4, epc8, & epc16) data sheet table 11?1. stratix & stratix gx device configuration schemes configuration scheme typical use fast passive parallel (fpp) configurat ion with a parallel synchronous conf iguration device or microprocessor interface where eight bits of configuration data are loaded on every clock cycle. passive serial (ps) configuration with a seri al synchronous mi croprocessor inte rface or the masterblaster tm communications cable, usb blaster, byteblaster tm ii, or byteblastermv parallel port download cable. passive parallel asynchronous (ppa) configuration with a parallel asynchronous microprocessor interface. in this scheme, the microprocessor treats the target device as memory. remote/local update fpp configuration using a nios tm (16-bit isa) and nios ? ii (32-bit isa) or other embedded processor. allows you to update the stratix or stratix gx device configuration remotely using the fpp scheme to load data. remote/local update ps passive serial synchronous configuration using a nios or other embedded processor. allows you to update the strati x or stratix gx device configuration remotely using the ps scheme to load data. remote/local update ppa passive parallel asynchr onous configuration using a nios or other embedded processor. in this scheme, the nios mi croprocessor treats the target device as memory. allows you to update the stratix or stratix gx device configuration remotely using the ppa scheme to load data. joint test action group (jtag) configuration through the ieee std. 1149.1 jtag pins. you can perform jtag configuration with either a download ca ble or an embedded device. ability to use signaltap ? ii embedded logic analyzer. s52013-3.2 11?2 altera corporation stratix device handbook, volume 2 july 2005 device configuration overview the remote system configuration with stratix & stratix gx devices chapter f for more information on setting device configuration options or generating configuration files, see the software setting chapter in volume 2 of the configuration handbook . device configuration overview during device operation, the fpga stores configuration data in sram cells. because sram memory is vola tile, you must load the sram cells with the configuration data each time the device powers up. after configuration, the device must initialize its registers and i/o pins. after initialization, the device enters user mode. figure 11?1 shows the state of the device during the configuratio n, initialization, and user mode. figure 11?1. stratix & stratix gx configuration cycle notes to figure 11?1 : (1) during initial power up and configuration, conf_done is low. after configuration, conf_done goes high. if the device is reconfigured, conf_done goes low after nconfig is driven low. (2) user i/o pins are tri-stated during co nfiguration. stratix and stratix gx devi ces also have a weak pull-up resistor on i/o pins during configuration that are enabled by nio_pullup . after initialization, the user i/o pins perform the function assigned in the user?s design. (3) if the init_done pin is used, it will be high because of an external 10 k resistor pull-up when nconfig is low and during the beginning of configuratio n. once the option bit to enable init_done is programmed into the device (during the first frame of configuration data), the init_done pin will go low. (4) dclk should not be left floating. it should be driven high or low. (5) data0 should not be left floating. it should be driven high or low. you can load the configuration data for the stratix or stratix gx device using a passive configuration sc heme. when using any passive configuration scheme, the stratix or st ratix gx device is incorporated into a system with an intelligent host, such as a microprocessor, that controls the configuration process. the host supplies configuration data from a storage device (e.g., a hard disk, ram, or other system memory). when using passive configuration, you can change the target device?s hi g h-z nconfig nstatus conf_done (1) dclk data user i/o pins ( 2 ) init_done ( 3 ) mode hi g h-z d0 d1 d2 d3 d (n ?1) dn confi g uration initialization user hi g h-z user i/o confi g uration (4) (5) altera corporation 11?3 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices functionality while the system is in operation by reconfiguring the device. you can also perform in-field upgrades by distributing a new programming file to system users. the following sections describe the msel[2..0] , vccsel , porsel , and nio_pullup pins used in stratix and stratix gx device configuration. msel[2..0] pins you can select a stratix or stratix gx device configuration scheme by driving its msel2 , msel1 , and msel0 pins either high or low, as shown in table 11?2 . the msel[] pins can be tied to v ccio of the i/o bank they reside in or ground. v ccsel pins you can configure stratix and stratix gx devices using the 3.3-, 2.5-, 1.8-, or 1.5-v lvttl i/o standard on co nfiguration and jtag input pins. vccsel is a dedicated input on stratix and stratix gx devices that selects between 3.3-v/2.5-v input buffers and 1.8-v/1.5-v input buffers for dedicated configuration input pins . a logic low supports 3.3-v/2.5-v signaling, and a logic high supports 1.8-v/1.5-v signalin g. a logic high can also support 3.3-v/2.5-v signaling. vccsel affects the configuration table 11?2. stratix & stratix gx device configuration schemes description msel2 msel1 msel0 fpp configuration 000 ppa configuration 001 ps configuration 010 remote/local update fpp (1) 100 remote/local update ppa (1) 101 remote/local update ps (1) 110 jtag-based configuration (3) (2) (2) (2) notes to ta b l e 11 ? 2 : (1) these schemes require that you drive a secondary pin runlu to specify whether to perform a remote update or local update. (2) do not leave msel pins floating. connect them to v ccio or gnd. these pins support the non-jtag configuration scheme used in production. if only jtag configuration is used you should connect the msel pins to ground. (3) jtag-based configuration takes precedence over other configuration schemes, which means the msel pins are ignored. 11?4 altera corporation stratix device handbook, volume 2 july 2005 device configuration overview related i/o banks (3, 4, 7, and 8) where the following pins reside: tdi , tms , tck , trst , msel0 , msel1 , msel2 , nconfig , nce , dclk , pll_ena , conf_done , nstatus . the vccsel pin can be pulled to 1.5, 1.8, 2.5, or 3.3-v for a logic high level. there is an internal 2.5-k pull-down resistor on vccsel . therefore, if you are using a pull-up resister to pull up this signal, you need to use a 1-k resistor. vccsel also sets the power-on-reset (por) trip point for all the configuration related i/o banks (3, 4, 7, and 8), ensuring that these i/o banks have powered up to the appropriate voltage levels before configuration begins. upon power- up, the fpga does not release nstatus until v ccint and all of the v ccio s of the configuration i/o banks are above their por trip points. if you set vccsel to ground (logic low), this sets the por trip point for all configuration i/o banks to a voltage consistent with 3. 3-v/2.5-v signaling. when vccsel = 0, the por trip point for these i/o banks may be as high as 1.8 v. if v ccio of any of the configuration banks is set to 1.8 or 1.5 v, the voltage supplied to this i/o bank(s) may never reach the por tr ip point, which will not allow the fpga to begin configuration. 1 if the v ccio of i/o banks 3, 4, 7, or 8 is set to 1.5 or 1.8 v and the configuration signals used requir e 3.3-v or 2.5-v signaling you should set vccsel to v cc (logic high) in order to lower the por trip point to enable successful configuration. table 11?3 shows how you should set the vccsel depending on the v ccio setting of the configuration i /o banks and your configuration input signaling voltages. the vccsel signal does not control any of the dual-purpose pins, including the dual-purpose configuration pins, such as the data[7..0] and ppa pins ( nws , nrs , cs , ncs , and rdynbsy ). during configuration, these dual-purpose pins drive out voltage levels corresponding to the v ccio supply voltage that po wers the i/o bank cont aining the pin. after configuration, the dual-purpose pins inherit the i/o standards specified in the design. table 11?3. vccsel setting v ccio (banks 3,4,7,8) configuration input signaling voltage v ccsel 3.3-v/2.5-v 3.3-v/2.5-v gnd 1.8-v/1.5-v 3.3-v/2.5-v/1.8-v/1.5-v vcc 3.3-v/2.5-v 1.8-v/1.5-v not supported altera corporation 11?5 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices porsel pins porsel is a dedicated input pin used to select por delay times of 2 ms or 100 ms during power-up. when the porsel pin is connected to ground, the por time is 100 ms; when the porsel pin is connected to vcc , the por time is 2 ms. th ere is an internal 2.5-k pull-down resistor on porsel . therefore if you are using a pull-up resistor to pull up this signal, you need to use a 1-k resistor. when using enhanced configuration de vices to configure stratix devices, make sure that the porsel setting of the stratix device is the same or faster than the porsel setting of the enhanced configuration device. if the fpga is not powered up after the enhanced configuration device exits por, the conf_done signal will be high since the pull-up resistor is pulling this signal high. when the enhanced configuration device exits por, oe of the enhanced configuration device is released and pulled high by a pull-up resistor. since the enhanced configuration device sees its ncs / conf_done signal also high, it enters a test mode. therefore, you must ensure the fpga powers up before the enhanced configuration device exits por. for more margin, the 100-ms setting can be selected when using an enhanced configuration device to al low the stratix fpga to power-up before configuration is attempted (see table 11?4 ). nio_pullup pins the nio_pullup pin enables a built-in weak pull-up resistor to pull all user i/o pins to vccio before and during device configuration. if nio_pullup is connected to v cc during configuration, the weak pull- ups on all user i/o pins and all dual-purpose pins are disabled. if connected to ground, the pull-ups are enabled during configuration. the nio_pullup pin can be pulled to 1.5, 1.8, 2.5, or 3.3-v for a logic level high. there is an internal 2.5-k pull-down resistor on nio_pullup . therefore, if you are using a pull-up resistor to pull up this signal, you need to use a 1-k resistor. table 11?4. porsel settings porsel settings por time (ms) gnd 100 v cc 2 11?6 altera corporation stratix device handbook, volume 2 july 2005 configuration file size tdo & nceo pins tdo and nceo pins drive out the same voltage levels as the v ccio that powers the i/o bank where the pi n resides. you must select the v ccio supply for the bank containing tdo accordingly. for example, when using the byteblastermv cable, the v ccio for the bank containing tdo must be powered up at 3.3-v. the current strength for tdo is 12 ma. configuration file size tables 11?5 and 11?6 summarize the approximate configuration file size required for each stratix and stratix gx device. to calculate the amount of storage space required for multi-dev ice configurations, add the file size of each device together. you should only use the numbers in tables 11?5 and 11?6 to estimate the file size before design compilation. the exact file size may vary because different altera ? quartus ? ii software versions may add a slightly table 11?5. stratix confi guration file sizes device raw binary file (.rbf) size (bits) ep1s10 3,534,640 ep1s20 5,904,832 ep1s25 7,894,144 ep1s30 10,379,368 ep1s40 12,389,632 ep1s60 17,543,968 ep1s80 23,834,032 table 11?6. stratix gx conf iguration file sizes device raw binary file size (bits) ep1sgx10c 3,579,928 ep1sgx10d 3,579,928 ep1sgx25c 7,951,248 ep1sgx25d 7,951,248 ep1sgx25f 7,951,248 ep1sgx40d 12,531,440 ep1sgx40g 12,531,440 altera corporation 11?7 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices different number of padding bits du ring programming. however, for any specific version of the quartus ii so ftware, any design targeted for the same device has the same configuration file size. altera configuration devices the altera enhanced configuratio n devices (epc16, epc8, and epc4 devices) support a single-device configuration solution for high-density fpgas and can be used in the fpp and ps configuration schemes. they are isp-capable through its jtag inte rface. the enhanced configuration devices are divided into two major blocks, the controller and the flash memory. f for information on enhanced co nfiguration devices, see the enhanced configuration devices (epc4, epc8 & epc16) data sheet and the using altera enhanced configuration devices chapter in the configuration handbook . the epc2 and epc1 configuration devices provide configuration support for the ps configuration scheme. the epc2 device is isp-capable through its jtag interface. the epc2 and epc1 can be cascaded to hold large configuration files. f for more information on epc2, epc1, and epc1441 configuration devices, see the configuration devices for sram-based lut devices data sheet . configuration schemes this section describes how to configure stratix and stratix gx devices with the following configuration schemes: ps configuration with configuration devices ps configuration with a download cable ps configuration with a microprocessor fpp configuration ppa configuration jtag programming & configuration jtag programming & configuration of multiple devices ps configuration ps configuration of stratix and stratix gx devices can be performed using an intelligent host, such as a max ? device, microprocessor with flash memory, an altera configuration device , or a download cable. in the ps scheme, an external host (max device, embedded processor, configuration device, or host pc) co ntrols configuration. configuration data is clocked into the target stratix devices via the data0 pin at each rising edge of dclk . 11?8 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes ps configuration with configuration devices the configuration device scheme uses an altera configuration device to supply data to the stratix or stratix gx device in a serial bitstream (see figure 11?3 ). in the configuration device scheme, nconfig is usually tied to v cc (when using epc16, epc8, epc4, or epc2 devices, nconfig may be connected to ninit_conf ). upon device power-up, the target stratix or stratix gx device senses th e low-to-high transition on nconfig and initiates configuration. the target device then drives the open-drain conf_done pin low, which in-turn drives the configuration device?s ncs pin low. when exiting power-on re set (por), both the target and configuration device release the open-drain nstatus pin. before configuration begins, the configuration device goes through a por delay of up to 200 ms to allow the power supply to stabilize (power the stratix or stratix gx device before or during the por time of the configuration device). this por delay has a maximum of 200 ms for epc2 devices. for enha nced configuration devices, you can select between 2 ms and 100 ms by connecting porsel pin to vcc or gnd , accordingly. during this time, the configuration device drives its oe pin low. this low signal delays configuration because the oe pin is connected to the target device?s nstatus pin. when the target and configuration devices complete por, they release nstatus , which is then pulled high by a pull-up resistor. when configuring multiple devices, co nfiguration does not begin until all devices release their oe or nstatus pins. when all devices are ready, the configuration device clocks data out se rially to the target devices using an internal oscillator. after successful configuration, the st ratix fpga starts initialization using the 10-mhz internal oscillator as the re ference clock. after initialization, this internal oscillator is turned off. the conf_done pin is released by the target device and then pulled high by a pull-up resistor. when initialization is complete, the fpga enters user mode. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. if an error occurs during configuration, the target device drives its nstatus pin low, resetting itself internally and resetting the configuration device. if the auto-restart configur ation on frame error option?available in the quartus ii global device options dialog box (assign menu)?is turned on, the device reconfigures automatically if an error occurs. to find this option, choose compiler settings (processing menu), then click on the chips & devices tab. altera corporation 11?9 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices if this option is turned off, the external system must monitor nstatus for errors and then pulse nconfig low to restart configuration. the external system can pulse nconfig if it is under system control rather than tied to v cc . when configuration is complete, the target device releases conf_done , which disables the configuration device by driving ncs high. the configuration device drives dclk low before and after configuration. in addition, if the configuration device sends all of its data and then detects that conf_done has not gone high, it re cognizes that the target device has not configured successfully. in this case, the configuration device pulses its oe pin low for a few microseconds, driving the target device?s nstatus pin low. if the auto-restart configuration on frame error option is set in the software, the ta rget device resets and then pulses its nstatus pin low. when nstatus returns high, the configuration device reconfigures the target device. when configuration is complete, the configuration device drives dclk low. do not pull conf_done low to delay initialization. instead, use the quartus ii software?s enable user-supplied start-up clock (clkusr) option to synchronize the initialization of multiple devices that are not in the same configuration ch ain. devices in the same configuration chain initialize together. when conf_done is driven low after device configuration, the configuration device recognizes that the target device has not configured successfully. figure 11?2 shows how to configure one stra tix or stratix gx device with one configuration device. 11?10 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes figure 11?2. single device configuration circuit notes to figure 11?2 : (1) the pull-up resistor sh ould be connected to the same supply voltage as the configuration device. (2) the enhanced configuration device s and epc2 devices have internal programmable pull-ups on oe and ncs . you should only use the internal pull-ups of the configuration device if the nstatus and conf_done signals are pulled up to 3.3 v or 2.5 v (not 1.8 v or 1.5 v). if external pull-ups are used, they should be 10 k . (3) the ninit_conf pin is available on epc16, epc8, epc4, and epc2 devices. if ninit_conf is not used, nconfig must be pulled to v cc through a resistor. he ninit_conf pin has an internal pull-up resistor that is always active in epc16, epc8, epc4, and epc2 devices. these devi ces do not need an external pull-up resistor on the ninit_conf pin. figure 11?3 shows how to configure multi ple stratix and stratix gx devices with multiple epc2 or epc1 configuration devices. stratix or stratix gx device dclk data oe ncs ninit_conf (3) msel1 msel0 msel2 dclk data0 nstatus conf_done nconfig v cc v cc gnd gnd (1) (1) nce v cc (1) nceo n.c. confi g uration device v cc 10 k (2) 10 k (2) (2) (2) 10 k ( 3 ) altera corporation 11?11 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?3. multi-device configuration circuit note (1) notes to figure 11?3 : (1) when performing multi-device active serial configuration, you must generate the configuration device programmer object file ( .pof ) from each project?s sof. you can combine multip le sofs using the quartus ii software through the device & pin option dialog box. for more information on how to create configuration and programming files, see the software settings section in the configuration handbook, volume 2 . (2) the pull-up resistor should be connected to the same supply volt age as the configuration device. (3) the enhanced configuration devices and epc2 devices have internal programmable pull-ups on oe and ncs . you should only use the internal pull-ups of the configuration device if the nstatus and conf_done signals are pulled up to 3.3 v or 2.5 v (not 1.8 v or 1.5 v). if external pull-ups are used, they should be 10 k (4) the ninit_conf pin is available on epc16, epc8, epc4, and epc2 devices. if ninit_conf is not used, nconfig must be pulled to v cc through a resistor. the ninit_conf pin has an internal pull-up resistor that is always active in epc16, epc8, epc4, and epc2 devices. these device s do not need an external pull-up resistor on the ninit_conf pin. after the first stratix or stratix gx device completes configuration during multi-device configuration, its nceo pin activates the second device?s nce pin, prompting the second device to begin configuration. because all device conf_done pins are tied together, all devices initialize and enter user mode at the same time. in addition, all nstatus pins are tied together; thus, if any device (including the configuration devices) detects an error, configuration stops for the entire chain. also, if the firs t configuration device does not detect conf_done going high at the end of configuration, it resets the chain by pulsing its oe pin low for a few microseconds. this low pulse drives the oe pin low on the second configuration device and drives nstatus low on all stratix and stratix gx devices, causing them to enter an error state. if the auto-restart configuration on frame error option is turned on in the software, the stratix or st ratix gx device releases its nstatus pins after a reset time-out period. when the nstatus pins are released and pulled high, the configuration devi ces reconfigure the chain. if the auto- epc1/epc2 dclk data oe ncs ninit_conf (4) dclk data0 nstatus conf_done nconfig v cc v cc gnd nce v cc dclk data ncs oe epc1/epc2 dclk data0 nstatus conf_done nconfig gnd nce msel2 msel1 nceo ncasc ( 2 ) ( 2 ) ( 2 ) nceo n.c. stratix or stratix gx device 2 stratix or stratix gx device 1 msel0 v cc gnd msel2 msel1 msel0 v cc 10 k 10 k ( 3 ) (4) ( 3 ) ( 3 ) ( 3 ) 10 k ninit_conf (4) 11?12 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes restart configuration on frame error option is not turned on, the stratix or stratix gx devices drive nstatus low until they are reset with a low pulse on nconfig . you can also cascade several epc2/epc1 configuration devices to configure multiple stratix and stratix gx devices. when all data from the first configuration device is sent, it drives ncasc low, which in turn drives ncs on the subsequent configuration device. because a configuration device requires less than one clock cycle to activate a subsequent configuration device, the data stream is uninterrupted. 1 you cannot cascade enhanced (epc16, epc8, and epc4) configuration devices. you can use a single configuration chain to configure multiple stratix and stratix gx devices. in this scheme, the nceo pin of the first device is connected to the nce pin of the second device in the chain. if there are additional device s, connect the nce pin of the next device to the nceo pin of the previous device. to configure properly, all of the device conf_done and nstatus pins must be tied together. figure 11?4 shows an example of configuring multiple stratix and stratix gx devices using a configuration device. altera corporation 11?13 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?4. configuring multiple stratix & stratix gx devices with a single configuration device note (1) notes to figure 11?4 : (1) when performing multi-device active serial configuration, you must generate the configuration device programmer object file ( .pof) from each project?s sof. you can combine multip le sofs using the quartus ii software through the device & pin option dialog box. for more information on how to create configuration and programming files, see the software settings section in the configuration handbook, volume 2 . (2) the pull-up resistor should be connected to the same supply volt age as the configuration device. (3) the enhanced configuration devices and epc2 devices have internal programmable pull-ups on oe and ncs . you should only use the internal pull-ups of the configuration device if the nstatus and conf_done signals are pulled up to 3.3 v or 2.5 v (not 1.8 v or 1.5 v). if external pull-ups are used, they should be 10 k . (4) epc16, epc8, and epc4 configuration devices cannot be cascaded. (5) the ninit_conf pin is available on epc16, epc8, epc4, and epc2 devices. if ninit_conf is not used, nconfig must be pulled to v cc through a resistor. the ninit_conf pin has an internal pull-up resistor that is always active in epc16, epc8, epc4, and epc2 devices. these device s do not need an external pull-up resistor on the ninit_conf pin. confi g uration device (4) dclk data oe ncs ninit_conf (5) dclk data0 nstatus conf_done nconfig v cc v cc gnd nce v cc dclk data0 nstatus conf_done nconfig gnd nce msel2 msel1 nceo ncasc ( 2 ) ( 2 ) ( 2 ) nceo n.c. stratix or stratix gx device 2 stratix or stratix gx device 1 msel0 v cc gnd msel2 msel1 msel0 v cc ( 3 ) 10 k 10 k 11?14 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes table 11?7 shows the status of the device data pins during and after configuration. ps configuration with a download cable in ps configuration with a download cable, an intelligent host transfers data from a storage device to the stra tix or stratix gx device through the masterblaster, usb-blaster, byteblas ter ii or byteblastermv cable. to initiate configuration in this scheme, the download cable generates a low-to-high transition on the nconfig pin. the programming hardware then places the configuration data one bit at a time on the device?s data0 pin. the data is clocked into the target device until conf_done goes high. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. when using programming hardware for the stratix or stratix gx device, turning on the auto-restart configur ation on frame error option does not affect the configuration cycle because the quartus ii software must restart configuration when an error occurs. additionally, the enable user-supplied start- up clock (clkusr) option has no affect on the device initialization since this option is disabled in the sof when programming the fpga using the quartus ii software programmer and a download cable. therefore, if you turn on the clkusr option, you do not need to provide a clock on clkusr when you are configuring the fpga with the quartus ii progra mmer and a download cable. figure 11?5 shows ps configuration for the stratix or stratix gx device using a masterblaster, usb-blaster, byteblaster ii or byteblastermv cable. table 11?7. data pin status before & after configuration pins stratix or stratix gx device during after data0 (1) used for configuration user defined data[7..1] (2) used in some configuration modes user defined i/o pins tri-state user defined notes to ta b l e 11 ? 7 : (1) the status shown is for configur ation with a conf iguration device. (2) the function of these pins depends upon the settings specif ied in the quartus ii software using the device & pin option dialog box (see the software settings section in the configuration handbook, volume 2, and the quartus ii help software for more information). altera corporation 11?15 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?5. ps configuration ci rcuit with a download cable notes to figure 11?5 : (1) you should connect the pull-u p resistor to the same supply voltage as the masterblaster ( vio pin) or byteblastermv cable. (2) the pull-up resistors on the data0 and dclk pins are only needed if the downlo ad cable is the only configuration scheme used on the board. this is to ensure that the data0 and dclk pins are not left floating after configuration. for example, if the design al so uses a configuration device, the pull-up resistors on the data0 and dclk pins are not necessary. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the device?s v ccio . this pin is a no-connect pin for the byteblastermv header. you can use programming hardware to configure multiple stratix and stratix gx devices by connecting each device?s nceo pin to the subsequent device?s nce pin. all other configur ation pins are connected to each device in the chain. because all conf_done pins are tied together, all devices in the chain initialize and enter user mode at th e same time. in addition, because the nstatus pins are tied together, the entire chain halts configuration if any device detects an error. in this si tuation, the quartus ii software must restart configuration; the auto-restart configuration on frame error option does not affect the configuration cycle. figure 11?6 shows how to configure multi ple stratix and stratix gx devices with a masterblaster or byteblastermv cable. download cable 10-pin male header (ps mode) v cc (1) v cc (1) v cc v cc (1) v cc (1) v cc (1) stratix or stratix gx device msel2 dclk nconfig conf_done shield gnd msel1 msel0 10 k 10 k 10 k 10 k 10 k nstatus data0 pin 1 nce gnd gnd vio (3) v cc (2) (2) (2) nceo n.c. 11?16 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes figure 11?6. multi-device ps confi guration with a download cable notes to figure 11?6 : (1) you should connect the pull-u p resistor to the same supply voltage as the masterblaster ( vio pin) or byteblastermv cable. (2) the pull-up resistors on the data0 and dclk pins are only needed if the downlo ad cable is the only configuration scheme used on the board. this is to ensure that the data0 and dclk pins are not left floating after configuration. for example, if the design al so uses a configuration device, the pull-up resistors on the data0 and dclk pins are not necessary. (3) v io is a reference voltage for the masterblaster output driver. v io should match the device?s v ccio . see the masterblaster serial/usb communications cable data sheet for this value. if you are using a download cable to configure device(s) on a board that also has configuration devices, you should electrically isolate the configuration devices from the target device(s) and cable. one way to isolate the configuration devices is to ad d logic, such as a multiplexer, that can select between the configuration devices and the cable. the multiplexer device should allow bidirectional transfers on the nstatus and conf_done signals. another op tion is to add swit ches to the five common signals ( conf_done , nstatus , dclk , nconfig , and data0 ) between the cable and the configuration devices. the last option is to remove the configuration devices from the board when configuring with the cable. figure 11?7 shows a combination of a configuration device and a download cable to configure a stratix or stratix gx device. stratix or stratix gx device 1 stratix or stratix gx device 2 msel0 nce nconfig conf_done dclk nce nceo nconfig conf_done dclk nceo gnd (ps mode) v cc v cc (1) gnd v cc (1) v cc (1) v cc (1) v cc (1) nstatus nstatus data0 data0 msel1 msel0 msel1 10 k 10 k 10 k 1 0 k 10 k pin 1 download cable 10-pin male header n.c. vio (3 ) gnd v cc msel2 msel2 gnd v cc (2) (2) altera corporation 11?17 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?7. configuring with a combi ned ps & configuration device scheme notes to figure 11?7 : (1) you should connect the pull-up resistor to th e same supply voltage as the configuration device. (2) the pull-up resistors on the data0 and dclk pins are only needed if the downlo ad cable is the only configuration scheme used on the board. this is to ensure that the data0 and dclk pins are not left floating after configuration. for example, if the design al so uses a configuration device, the pull-up resistors on the data0 and dclk pins are not necessary. (3) pin 6 of the header is a v io reference voltage for the masterblaster output driver. v io should match the target device?s v ccio . this is a no-connect pin for the byteblastermv header. (4) you should not attempt configuration with a download ca ble while a configuration device is connected to a stratix or stratix gx device. instead, you should either remove the configuration device from its socket when using the download cable or place a switch on the five common signals between the download cable and the configuration device. remove the download cable when configuring with a configuration device. (5) if ninit_conf is not used, nconfig must be pulled to v cc either directly or through a resistor. (6) if external pull-ups are used on conf_done and nstatus pins, they should always be 10 k resistors. you can use the internal pull-ups of the conf iguration device only if the conf_done and nstatus signals are pulled-up to 3.3 v or 2.5 v (not 1.8 v or 1.5 v). f for more information on how to use the masterblaster or byteblastermv cables, see the following documents: usb-blaster usb port download cable data sheet masterblaster serial /usb communication s cable data sheet byteblastermv parallel port download cable data sheet byteblaster ii parallel port download cable data sheet stratix or stratix gx device msel0 nce nconfig conf_done dclk nceo gnd download cable 10-pin male header (ps mode) v cc v cc v cc v cc (1) v cc (1) v cc (1) nstatus data0 msel1 10 k 10 k 1 0 k 10 k pin 1 dclk data oe ncs ninit_conf (5) configuration device (4) (4) (4) (4) (4) gnd vio (3) n.c. (1) (1) gnd msel2 v cc (6) 10 k (6) (2) (2) (6) (6) 11?18 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes ps configuration wi th a microprocessor in ps configuration with a microprocessor, a microprocessor transfers data from a storage device to the targ et stratix or stratix gx device. to initiate configuration in this scheme , the microprocessor must generate a low-to-high transition on the nconfig pin and the target device must release nstatus . the microprocessor or programming hardware then places the configuration data one bit at a time on the data0 pin of the stratix or stratix gx device. the leas t significant bit (l sb) of each data byte must be presented first. data is clocked continuously into the target device until conf_done goes high. after all configuration data is sent to the stratix or stratix gx device, the conf_done pin goes high to show successful configuration and the start of initialization. the conf_done pin must have an external 10-k pull- up resistor in order for the device to initialize. initialization, by default, uses an internal oscillat or, which runs at 10 mhz. after initialization, this internal oscillator is turned off. if you are using the clkusr option, after all data is transferred clkusr must be clocked an ad ditional 136 times for the stratix or stratix gx device to initialize properly. driving dclk to the device after configuration is complete does not affect device operation. handshaking signals are not used in ps configuration modes. therefore, the configuration clock speed must be below the specified frequency to ensure correct configuration. no maximum dclk period exists. you can pause configuration by halting dclk for an indefinite amount of time. if the target device detects an error during configuration, it drives its nstatus pin low to alert the microprocessor. the microprocessor can then pulse nconfig low to restart the configuration process. alternatively, if the auto-restart configuration on frame error option is turned on in the quartus ii software, the target device releases nstatus after a reset time-out period. after nstatus is released, the microprocessor can reconfigure the target device without needing to pulse nconfig low. the microprocessor can also monitor the conf_done and init_done pins to ensure successful configurat ion. if the microprocessor sends all data and the initialization clock starts but conf_done and init_done have not gone high, it must reconfigure the target device. by default the init_done output is disabled. you can enable the init_done output by turning on enable init_done output option in the quartus ii software. if you do not turn on the enable init_done output option in the quartus ii software, you are advised to wait for the maximum value of t cd2um (see table 11?8 ) after the conf_done signal goes high to ensure the device has been initialized properly and that it has entered user mode. altera corporation 11?19 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices during configuration and initialization, and before the device enters user mode, the microprocessor must not drive the conf_done signal low. 1 if the optional clkusr pin is used and nconfig is pulled low to restart configuration during device initialization, you need to ensure clkusr continues toggling during the time nstatus is low (maximum of 40 s). figure 11?8 shows the circuit for ps configuration with a microprocessor. figure 11?8. ps configuration ci rcuit with microprocessor ps configuration timing figure 11?9 shows the ps configuration ti ming waveform for stratix and stratix gx devices. table 11?8 shows the ps timing parameters for stratix and stratix gx devices. microprocessor conf_done nstatus nce data0 nconfig stratix device memory addr data0 gnd msel1 msel2 v cc v cc 10 k 10 k gnd dclk nceo n.c. msel0 v cc 11?20 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes table 11?8. ps timing parameters fo r stratix & stra tix gx devices symbol parameter min max units t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns t cf2st1 nconfig high to nstatus high 40 (2) s t cfg nconfig low pulse width 40 s t status nstatus low pulse width 10 40 (2) s t cf2ck nconfig high to first rising edge on dclk 40 s t st2ck nstatus high to first rising edge on dclk 1s t dsu data setup time before rising edge on dclk 7ns t dh data hold time after rising edge on dclk 0ns t ch dclk high time 4ns t cl dclk low time 4ns t clk dclk period 10 ns f max dclk maximum frequency 100 mhz t cd2um conf_done high to user mode (1) 620s notes to ta b l e 11 ? 8 : (1) the minimum and maximum numbers apply on ly if the internal oscillator is chos en as the clock source for starting up the device. if the clock source is clkusr , multiply the clock period by 136 to obtain this value. (2) this value is obtainable if users do not delay configuration by extending the nstatus low pulse width. altera corporation 11?21 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?9. ps timing waveform for stratix & stratix gx devices note (1) notes to figure 11?9 : (1) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) upon power-up, the stratix ii device holds nstatus low for the time of the por delay. (3) upon power-up, before and during configuration, conf_done is low. (4) dclk should not be left floating after co nfiguration. it should be driven high or low, whichever is convenient. data[] is available as user i/os after configuration and th e state of these pins depend s on the dual-purpose pin settings. fpp configuration parallel configuration of stratix and stratix gx devices meets the continuously increasing demand for faster configuration times. stratix and stratix gx devices can receive byte-wide configuration data per clock cycle, and guarantee a configuration time of less than 100 ms with a 100- mhz configuration clock. stratix and stratix gx devices support programming data bandwidth up to 800 megabits per second (mbps) in this mode. you can use parallel configuration with an epc16, epc8, or epc4 device, or a microprocessor. this section discusses the following schemes for fpp configuration in stratix and stratix gx devices: fpp configuration using an en hanced configuration device fpp configuration using a microprocessor nconfig nstatus (2) conf_done (3) dclk data user i/o init_done bit 0 bit 1 bit 2 bit 3 bit n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck hi g h-z user mode (4) (4) 11?22 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes fpp configuration using an enhanced configuration device when using fpp with an enhanced configuration device, it supplies data in a byte-wide fashion to the stratix or stratix gx device every dclk cycle. see figure 11?10 . figure 11?10. fpp configuration using enhanced configuration devices notes to figure 11?10 : (1) the pull-up resistors should be conne cted to the same supply voltage as the configuration device. (2) the enhanced configuration device s and epc2 devices have internal programmable pull-ups on oe and ncs . you should only use the internal pull-ups of the configuration device if the nstatus and conf_done signals are pulled up to 3.3 v or 2.5 v (not 1.8 v or 1.5 v). if external pull-ups are used, they should be 10 k . (3) the ninit_conf pin is available on epc16, epc8, epc4, and epc2 devices. if ninit_conf is not used, nconfig must be pulled to v cc through a resistor. the ninit_conf pin has an internal pull-up resistor that is always active in epc16, epc8, epc4, and epc2 devices. these devi ces do not need an external pull-up resistor on the ninit_conf pin. in the enhanced configuration device scheme, nconfig is tied to ninit_conf . on power up, the target strati x or stratix gx device senses the low-to-high transition on nconfig and initiates configuration. the target stratix or stratix gx device then drives the open-drain conf_done pin low, which in-turn drives the enhanced configur ation device?s ncs pin low. before configuration starts, there is a 2-ms por delay if the porsel pin is connected to v cc in the enhanced configuration device. if the porsel pin is connected to ground, the por de lay is 100 ms. when each device determines that its power is stable, it releases its nstatus or oe pin. because the enhanced co nfiguration device?s oe pin is connected to the target stratix or stratix gx device?s nstatus pin, configuration is delayed until both the nstatus and oe pins are released by each device. the nstatus and oe pins are pulled up by a re sistor on their respective stratix or stratix gx device enhanced configuration device dclk data[7..0] oe (2) ncs (2) ninit_conf (3) msel2 msel1 dclk data[7..0] nstatus conf_done nconfig v cc v cc gnd gnd (1) (1) nce nceo n.c. msel0 10 k (2) 10 k (2) altera corporation 11?23 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices devices once they are released. when configuring multiple devices, connect the nstatus pins together to ensure configuration only happens when all devices release their oe or nstatus pins. the enhanced configuration device then clocks data out in parallel to the stratix or stratix gx device using a 66-mhz internal oscillator, or drives it to the stratix or stratix gx device through the extclk pin. if there is an error during configurat ion, the stratix or stratix gx device drives the nstatus pin low, resetting itself internally and resetting the enhanced configuration device. the quartus ii software provides an auto-restart configuration after error option that automatically initiates the reconfiguration whenever an error occurs. see the software settings chapter in volume 2 of the configuration handbook for information on how to turn this option on or off. if this option is turned off, you must set monitor nstatus to check for errors. to initiate reconfiguration, pulse nconfig low. the external system can pulse nconfig if it is under system control rather than tied to v cc . therefore, nconfig must be connected to ninit_conf if you want to reprogram the stratix or stratix gx device on the fly. when configuration is complete, the stratix or stratix gx device releases the conf_done pin, which is then pulled up by a resistor. this action disables the epc16, epc8, or epc4 enhanced configuration device as ncs is driven high. initialization, by default, uses an internal oscillator, which runs at 10 mhz. after initialization, this internal oscillator is turned off. when initialization is complete, the stratix or stratix gx device enters user mode. the enhanced configuration device drives dclk low before and after configuration. 1 conf_done goes high one byte early in parallel synchronous (fpp) and asynchronous (ppa) modes using a microprocessor with .rbf , .hex , and .ttf file formats. this does not apply to fpp mode for enhanced configuration devices using .pof file format. this also does not apply to serial modes. if, after sending out all of its data, the enhanced configuration device does not detect conf_done going high, it recognizes that the stratix or stratix gx device has not configured successfully. the enhanced configuration device pulses its oe pin low for a few microseconds, driving the nstatus pin on the stratix or stratix gx device low. if the auto-restart configuration after error option is on, the stratix or stratix gx device resets and then pulses its nstatus low. when nstatus returns high, reconfiguration is restarted (see figure 11?11 on page 11?25 ). 11?24 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes do not drive conf_done low after device configuration to delay initialization. instead, use the enable user-supplied start-up clock (clkusr) option in the device & pin options dialog box. you can use this option to synchronize the initialization of multiple devices that are not in the same configuration chain. devices in the same configuration chain initialize together. after the first stratix or stratix gx device completes configuration during multi-device configuration, its nceo pin activates the second stratix or stratix gx device?s nce pin, prompting the se cond device to begin configuration. because conf_done pins are tied together, all devices initialize and enter user mode at the same time. because nstatus pins are tied together, configuration stops for the whole chain if any device (including enhanced config uration devices) detects an error. also, if the enhanced configuratio n device does not detect a high on conf_done at the end of configuration, it pulses its oe low for a few microseconds to reset the chain. the low oe pulse drives nstatus low on all stratix and stratix gx devices, causing them to enter an error state. this state is similar to a stratix or stratix gx device detecting an error. if the auto-restart configuration after error option is on, the stratix and stratix gx devices release their nstatus pins after a reset time-out period. when the nstatus pins are released and pulled high, the configuration device reconfigures the chain. if the auto-restart configuration after error option is off, nstatus stays low until the stratix and stratix gx devices are reset with a low pulse on nconfig . figure 11?11 shows the fpp configuration with a configuration device timing waveform for stratix and stratix gx devices. altera corporation 11?25 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?11. fpp configuration with a c onfiguration device timing waveform note (1) notes to figure 11?11 : (1) for timing information, see the enhanced configuration devices (epc4, epc8 & epc16) data sheet . (2) the configuration device drives data high after configuration. (3) stratix and stratix gx devices ente r user mode 136 clock cycles after conf_done goes high. fpp configuration using a microprocessor when using a microprocessor fo r parallel configuration, the microprocessor transfers data from a storage device to the stratix or stratix gx device through configuration hardware. to initiate configuration, the microprocessor needs to generate a low-to-high transition on the nconfig pin and the stratix or stratix gx device must release nstatus . the microprocessor then pl aces the configuration data to the data[7..0] pins of the stratix or stratix gx device. data is clocked continuously into the stra tix or stratix gx device until conf_done goes high. the configuration clock ( dclk ) speed must be below the specified frequency to ensure correct configuration. no maximum dclk period exists. you can pause configuration by halting dclk for an indefinite amount of time. after all configuration data is sent to the stratix or stratix gx device, the conf_done pin goes high to show successful configuration and the start of initialization. the conf_done pin must have an external 10-k pull- up resistor in order for the device to initialize. initialization, by default, uses an internal oscillat or, which runs at 10 mhz. after initialization, this internal oscillator is turned off. if you are using the clkusr option, after all data is transferred clkusr must be clocked an ad ditional 136 times for the stratix or stratix gx device to initialize properly. driving dclk to the device after configuration is complete does not affect device operation. by byte0 byte1 byte2 byte3 byten tri-state user mode (3) (2) t oezx t por t ch t cl t dsu t co t dh tri-state oe/nstatus ncs/conf_done dclk data[7..0] user i/o init_done ninit_conf or vcc/nconfig 11?26 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes default, the init_done output is disabled. you can enable the init_done output by turning on the enable init_done output option in the quartus ii software. if you do not turn on the enable init_done output option in the quartus ii software, you are advise d to wait for maximum value of t cd2um (see table 11?9 ) after the conf_done signal goes high to ensure the device has been initialized properly and that it has entered user mode. during configuration and initialization and before the device enters user mode, the microprocessor must not drive the conf_done signal low. 1 if the optional clkusr pin is used and nconfig is pulled low to restart configuration during device initialization, you need to ensure clkusr continues toggling during the time nstatus is low (maximum of 40 s). if the stratix or stratix gx device dete cts an error during configuration, it drives nstatus low to alert the microprocessor. the pin on the microprocessor connected to nstatus must be an input. the microprocessor can then pulse nconfig low to restart the configuration error. with the auto-restart configuration after error option on, the stratix or stratix gx device releases nstatus after a reset time-out period. after nstatus is released, the microprocessor can reconfigure the stratix or stratix gx device without pulsing nconfig low. the microprocessor can also monitor the conf_done and init_done pins to ensure successful configurat ion. if the microprocessor sends all the data and the initialization clock starts but conf_done and init_done have not gone high, it must reconfigure the stratix or stratix gx device. after waiting the specified 136 dclk cycles, the microprocessor should restart configuration by pulsing nconfig low. figure 11?12 shows the circuit for stratix and stratix gx parallel configuration using a microprocessor. altera corporation 11?27 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?12. parallel configura tion using a microprocessor note to figure 11?12 : (1) the pull-up resistors sho uld be connected to any v cc that meets the stratix high- level input voltage (v ih ) specification. for multi-device parallel configur ation with a microprocessor, the nceo pin of the first stratix or stratix gx device is cascaded to the second device?s nce pin. the second device in the chain begins configuration within one clock cycle; therefore, th e transfer of data destinations is transparent to the microprocessor. because the conf_done pins of the devices are connected together, all devices initialize and enter user mode at the same time. because the nstatus pins are also tied together, if any of the devices detects an error, the entire chain halts configuration and drives nstatus low. the microprocessor can then pulse nconfig low to restart configuration. if the auto-restart config uration after error option is on, the stratix and stratix gx devices release nstatus after a reset time-out period. the microprocessor can then reconfigure the devices once nstatus is released. figure 11?13 shows multi-device configuration using a microprocessor. figure 11?14 shows multi-device configuration when both stratix and stratix gx devices are receiving the same data. in this case, the microprocessor sends the data to both devices simultaneously, and the device s configure simultaneously. microprocessor conf_done nstatus nce data[7..0] nconfig stratix device memory addr data[7..0] gnd msel1 msel2 v cc (1) v cc (1) gnd dclk nceo n.c. msel0 10 k 10 k 11?28 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes figure 11?13. parallel data transfer in seri al configuration with a microprocessor note to figure 11?13 : (1) you should connect the pull-up resistors to any v cc that meets the stratix high-level input voltage (v ih ) specification. figure 11?14. multiple device parallel configurati on with the same data using a microprocessor notes to figure 11?14 : (1) you should connect the pull-up resistors to any v cc that meets the stratix high-level input voltage (v ih ) specification. (2) the nceo pins are left unconnected when configuring the same data into multiple stratix or stratix gx devices. f for more information on configuring multiple altera devices in the same configuration chain, see the configuring mixed altera fpga chains chapter in the configuration handbook, volume 2 . microprocessor conf_done nstatus nce data[7..0] nconfig stratix device memory addr data[7..0] gnd v cc (1) v cc (1) dclk nceo conf_done nstatus nce data[7..0] nconfig stratix device msel1 msel2 dclk nceo n.c. gnd msel0 msel1 msel2 msel0 gnd 10 k 10 k microprocessor conf_done nstatus nce data[7..0] nconfig stratix device memory addr data[7..0] gnd v cc (1) v cc (1) dclk conf_done nstatus nce data[7..0] nconfig stratix device msel1 msel2 dclk nceo n.c. (2) gnd msel0 msel1 msel2 gnd msel0 nceo n.c. (2) gnd 10 k 10 k altera corporation 11?29 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices fpp configuration timing figure 11?15 shows fpp timing waveforms for configuring a stratix or stratix gx device in fpp mode. table 11?9 shows the fpp timing parameters for stratix or stratix gx devices. figure 11?15. timing waveform for configuring devices in fpp mode note (1) notes to figure 11?15 : (1) the beginning of this waveform shows the device in user-mode. in user-mode, nconfig , nstatus , and conf_done are at logic high levels. when nconfig is pulled low, a reconfiguration cycle begins. (2) upon power-up, the stratix ii device holds nstatus low for the time of the por delay. (3) upon power-up, before and during configuration, conf_done is low. (4) dclk should not be left floating after co nfiguration. it should be driven high or low, whichever is convenient. data[] is available as user i/os after configuration and th e state of these pins depend s on the dual-purpose pin settings. table 11?9. fpp timing parameters for stra tix & stratix gx de vices (part 1 of 2) symbol parameter min max units t cf2ck nconfig high to first rising edge on dclk 40 s t dsu data setup time before rising edge on dclk 7ns t dh data hold time after rising edge on dclk 0ns t cfg nconfig low pulse width 40 s t ch dclk high time 4ns t cl dclk low time 4ns t clk dclk period 10 ns nconfig nstatus (2) conf_done (3) dclk data[7..0} user i/o init_done byte 0 byte 1 byte 2 byte 3 byte n t cd2um t cf2st1 t cf2cd t cfg t ch t cl t dh t dsu t cf2ck t status t clk t cf2st0 t st2ck hi g h-z user mode (4) (4) user mode 11?30 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes ppa configuration in ppa schemes, a microprocessor driv es data to the stratix or stratix gx device through a download cable. when using a ppa scheme, use a 1-k pull-up resistor to pull the dclk pin high to prevent unused configuration pins from floating. to begin configuration, the microprocessor drives nconfig high and then asserts the target device?s ncs pin low and cs pin high. next, the microprocessor places an 8-bit config uration word on the target device?s data inputs and pulses nws low. on the rising edge of nws , the target device latches a byte of configur ation data and then drives its rdynbsy signal low, indicating that it is proc essing the byte of configuration data. the microprocessor then performs other system func tions while the stratix or stratix gx device is processing the byte of configuration data. next, the microprocessor checks nstatus and conf_done . if nstatus is high and conf_done is low, the microprocessor sends the next data byte. if nstatus is low, the device is signaling an error and the microprocessor should restart configuration. however, if nstatus is high and all the configuration data is received, the device is ready for initialization. at the beginning of initialization, conf_done goes high to indicate that configuration is complete. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. initialization, by default, uses an internal oscillator, which runs at 10 mhz. after initialization, this inte rnal oscillator is turned off. when initialization is complete, the stratix or stratix gx device enters user mode. f max dclk frequency 100 mhz t cd2um conf_done high to user mode (1) 620s t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns t cf2st1 nconfig high to nstatus high 40 (2) s t status nstatus low pulse width 10 40 (2) s t st2ck nstatus high to firstrising edge of dclk 1s notes to ta b l e 11 ? 9 : (1) the minimum and maximum numbers apply on ly if the internal oscillator is chos en as the clock source for starting up the device. if the clock source is clkusr , multiply the clock period by 136 to obtain this value. (2) this value is obtainable if users do not delay configuration by extending the nstatus low pulse width. table 11?9. fpp timing parameters for stra tix & stratix gx de vices (part 2 of 2) symbol parameter min max units altera corporation 11?31 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?16 shows the ppa configuration ci rcuit. an optional address decoder controls the device?s ncs and cs pins. this decoder allows the microprocessor to select the stratix or stratix gx device by accessing a particular address, simplifying the configuration process. figure 11?16. ppa confi guration circuit note to figure 11?16 : (1) the pull-up resistor should be connected to the sa me supply voltage as the stratix or stratix gx device. the device?s ncs or cs pins can be toggled during ppa configuration if the design meets the specifications for t cssu , t wsp , and t csh given in table 11?10 on page 11?36 . the microprocessor can also directly control the ncs and cs signals. you can tie one of the ncs or cs signals to its active state (i.e., ncs may be tied low) and toggle the other signal to control configuration. stratix and stratix gx devices can se rialize data internally without the microprocessor. when the stratix or stratix gx device is ready for the next byte of configuration data, it drives rdynbsy high. if the microprocessor senses a high signal when it polls rdynbsy , the microprocessor strobes the next byte of configuration data into the device. alternatively, the nrs signal can be strobed, causing the rdynbsy signal to appear on data7 . because rdynbsy does not need to msel2 msel1 msel0 stratix device dclk 10 k 10 k 10 k 10 k ncs cs conf_done nstatus nce data[7..0] nws nrs nconfig rdynbsy address decoder v cc v cc v cc addr microprocessor v cc v cc memory addr data[7..0] gnd nceo n.c. (1) (1) (1) (1) gnd 11?32 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes be monitored, reading the state of the configuration data by strobing nrs low saves a system i/o po rt. do not drive data on to the data bus while nrs is low because it causes contention on data7 . if the nrs pin is not used to monitor configuration, you should tie it high. to simplify configuration, the microprocessor can wait for the total time of t bus y (max) + t rdy2ws + t w2sb before sending the next data bit. after configuration, the ncs , cs , nrs , nws , and rdynbsy pins act as user i/o pins. however, if the ppa sche me is chosen in the quartus ii software, these i/o pins are tri-stated by default in user mode and should be driven by the microprocessor. to change the default settings in the quartus ii software, select device & pin option (compiler setting menu). if the stratix or stratix gx device dete cts an error during configuration, it drives nstatus low to alert the microproce ssor. the microprocessor can then pulse nconfig low to restart the configuration process. alternatively, if the auto-restart configuration on frame error option is turned on, the stratix or stratix gx device releases nstatus after a reset time-out period. after nstatus is released, the microprocessor can reconfigure the stratix or stratix gx device. at this point, the microprocessor does not need to pulse nconfig low. the microprocessor can also monitor the conf_done and init_done pins to ensure successful configuration. the microprocessor must monitor the nstatus pin to detect errors and the conf_done pin to determine when programming completes ( conf_done goes high one byte early in parallel mode). if the microprocessor sends all configuration data and starts initialization but conf_done is not asserted, the microprocessor must reconfigure the stratix or stratix gx device. by default, the init_done is disabled. you can enable the init_done output by turning on the enable init_done output option in the quartus ii software. if you do not turn on the enable init_done output option in the quartus ii software, you are advised to wait for the maximum value of t cd2um (see table 11?10 ) after the conf_done signal goes high to ensure the device has been initialized properly and that it has entered user mode. during configuration and initialization, and before the device enters user mode, the microprocessor must not drive the conf_done signal low. 1 if the optional clkusr pin is used and nconfig is pulled low to restart configuration during device initialization, you need to ensure that clkusr continues toggling during the time nstatus is low (maximum of 40 s). altera corporation 11?33 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices you can also use ppa mode to config ure multiple stratix and stratix gx devices. multi-device ppa configuration is similar to single-device ppa configuration, except that the stratix and stratix gx devices are cascaded. after you configure the first stratix or stratix gx device, nceo is asserted, which asserts the nce pin on the second device, initiating configuration. because the second stratix or strati x gx device begins configuration within one write cycle of the first devi ce, the transfer of data destinations is transparent to the microprocessor. all stratix and stratix gx device conf_done pins are tied together; therefore, all devices initialize and enter user mode at the same time. see figure 11?17 . figure 11?17. ppa multi-device configuration circuit notes to figure 11?17 : (1) if not used, you can connect the cs pin to v cc directly. if not used, the ncs pin can be connected to gnd directly. (2) connect the pull-up resistor to the same su pply voltage as the stratix or stratix gx device. gnd address decoder addr addr memory data[7..0] ncs cs (1) conf_done nstatus nce nws nrs nconfig rdynbsy ncs cs (1) conf_done nstatus nce nws nrs nconfig rdynbsy microprocessor data[7..0] data[7..0] nceo n.c. nceo (2) (3) dclk (2) dclk (2) 10 k 10 k 10 k 10 k stratix device 1 stratix device 2 msel2 msel1 msel0 v cc gnd v cc gnd v cc v cc v cc v cc (2) 10 k v cc msel2 msel1 msel0 11?34 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes ppa configuration timing figure 11?18 shows the stratix and stratix gx device timing waveforms for ppa configuration. figure 11?18. ppa timing waveforms for stratix & stratix gx devices notes to figure 11?18 : (1) upon power-up, nstatus is held low for the time of the por delay. (2) upon power-up, before and during configuration, conf_done is low. (3) after configuration, the state of cs , ncs , nws , and rdynbsy depends on the design prog rammed into th e stratix or stratix gx device. (4) device i/o pins are in user mode. byte 0 byte 1 t dh t wsp t cf2ws nconfig nstatus ( 1) conf_done ( 2) data[7..0] cs ( 3) ncs ( 3) nws ( 3) rdynbsy ( 3) byte n e 1 byte n t busy t ws2b t rdy2ws t cfg t status user i/os init_done hi g h-z t cf2st0 t cf2cd ( 4) ( 4) ( 4) ( 4) ( 4) t cf2st1 t dsu t cssu t csh t cd2um t cssu altera corporation 11?35 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?19 shows the stratix and strati x gx timing waveforms when using strobed nrs and nws signals. figure 11?19. ppa timing waveforms using strobed nrs & nws signals notes to figure 11?19 : (1) the user can toggle ncs or cs during configuration if the design meets the specification for t cssu , t wsp , and t csh . (2) device i/o pins are in user mode. (3) the data[7..0] pins are available as user i/os after configur ation and the state of theses pins depends on the dual-purpose pin settings. do not leave data[7..0] floating. if these pins are not used in user-mode, you should drive them high or low, wh ichever is more convenient. (4) data7 is a bidirectional pin. it represents an input for data input, but represents an ou tput to show the status of rdynbsy . byte 0 byte 1 byte n nconfig nstatus conf_done ncs (1) cs (1) data[7..0] nws nrs init_done user i/o data7/rdynbsy (4) t cssu t cfg t wsp t ws2rs t rsd7 t rdy2ws t dh t busy t csh t dsu t cf2ws (2) (2) (3) (2) (2) (2) (2) t cd2um t rs2ws t cf2st1 t cf2scd t cf2st0 t status t ws2rs t ws2b 11?36 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes table 11?10 defines the stratix and stratix gx timing parameters for ppa configuration f for information on how to create configuration and programming files for this configuration scheme, see the software settings section in the configuration handbook, volume 2 . jtag programming & configuration the jtag has developed a specification for boundary-scan testing. this boundary-scan test (bst) architecture offers the capability to efficiently test components on printed circuit boar ds (pcbs) with ti ght lead spacing. the bst architecture can test pin conn ections without usin g physical test table 11?10. ppa timing parameters for stratix & stratix gx devices symbol parameter min max units t cf2ws nconfig high to first rising edge on nws 40 s t dsu data setup time before rising edge on nws 10 ns t dh data hold time after rising edge on nws 0ns t cssu chip select setup time before rising edge on nws 10 ns t csh chip select hold time after rising edge on nws 0ns t wsp nws low pulse width 15 ns t cfg nconfig low pulse width 40 s t ws2b nws rising edge to rdynbsy low 20 ns t busy rdynbsy low pulse width 745ns t rdy2ws rdynbsy rising edge to nws rising edge 15 ns t ws2rs nws rising edge to nrs falling edge 15 ns t rs2ws nrs rising edge to nws rising edge 15 ns t rsd7 nrs falling edge to data7 valid with rdynbsy signal 20 ns t cd2um conf_done high to user mode (1) 620s t status nstatus low pulse width 10 40 (2) s t cf2cd nconfig low to conf_done low 800 ns t cf2st0 nconfig low to nstatus low 800 ns t cf2st1 nconfig high to nstatus high 40 (2) s notes to table 11?10 : (1) the minimum and maximum numbers apply on ly if the internal oscillator is chos en as the clock source for starting up the device. if the clock source is clkusr , multiply the clock period by 136 to obtain this value. (2) this value is obtained if you do not delay configuration by extending the nstatus to low pulse width. altera corporation 11?37 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices probes and capture functional data wh ile a device is operating normally. you can also use the jtag circuitry to shift configuration data into the device. f for more information on jtag boundary-scan testing, see an 39: ieee 1149.1 (jtag) boundary-scan t esting in altera devices . to use the signaltap ? ii embedded logic analyzer, you need to connect the jtag pins of your stratix device to a download cable header on your pcb. f for more information on signaltap ii, see the design debugging using signaltap ii embedded logic analyzer chapter in the quartus ii handbook, volume 2. a device operating in jtag mode uses four required pins, tdi , tdo , tms , and tck , and one optional pin, trst . the four jtag input pins ( tdi , tms , tck and trst ) have weak, internal pull-u p resistors, whose values range from 20 to 40 k . all other pins are tri-stated during jtag configuration. do not begin jtag configuration until all other configuration is complete. table 11?11 shows each jtag pin?s function. table 11?11. jtag pin descriptions pin description function tdi test data input serial input pin for instructions as well as test and programming data. data is shifted in on the rising edge of tck . the vccsel pin controls the input buffer selection. tdo test data output serial data output pin for instruct ions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. the high level output voltage is determined by vccio. tms test mode select input pin that provides the contro l signal to determine the transitions of the test access port ( tap) controller state machine. tr ansitions within the state machine occur on the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . the vccsel pin controls the input buffer selection. tck test clock input the clock input to the bst circ uitry. some operations occur at the rising edge, while others occur at the falling edge. the vccsel pin controls the input buffer selection. trst test reset input (optional) active-low input to asynchronously reset the boundary-scan circuit. the trst pin is optional according to ieee std. 1149.1. the vccsel pin controls the input buffer selection. 11?38 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes during jtag configuration, data is downloaded to the device on the pcb through the masterblaster or bytebl astermv header. configuring devices through a cable is similar to prog ramming devices in-system. one difference is to connect the trst pin to v cc to ensure that the tap controller is not reset. see figure 11?20 . figure 11?20. jtag configurat ion of a single device notes to figure 11?20 : (1) you should connect the pull-up resist or to the same supply voltage as the download cable. (2) you should connect the nconfig , msel0 , and msel1 pins to support a non-jtag configuration scheme. if you only use jtag configuration, connect nconfig to v cc , and msel0 , msel1 , and msel2 to ground. pull data0 and dclk to high or low. (3) v io is a reference voltage for the masterblaster output driver. v io should match the device?s v ccio . see the masterblaster serial/usb communications cable data sheet for this value. to configure a single device in a jt ag chain, the programming software places all other devices in bypass mode. in bypass mode, devices pass programming data from the tdi pin to the tdo pin through a single bypass register without being affected internally. this scheme enables the programming software to program or verify the target device. configuration data driven into the device appears on the tdo pin one clock cycle later. nce msel0 msel1 nconfig conf_done v cc (1) v cc (1) gnd v cc v cc gnd v cc (2) (2) (2) v cc (1) 1 k 10 k 10 k 1 k nstatus pin 1 m asterblaster or byteblaster m v 1 0 -pin m ale header (top view) gnd trst tck tdo tms tdi 1 k gnd vio (3) stratix or stratix gx device msel2 data0 dclk (2) (2) (2) altera corporation 11?39 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices stratix and stratix gx devices have dedicated jtag pins. you can perform jtag testing on stratix and stratix gx devices before and after, but not during configuration. the chip -wide reset and output enable pins on stratix and stratix gx devices do not affect jtag boundary-scan or programming operations. toggling th ese pins does not affect jtag operations (other than the usual boundary-scan operation). when designing a board for jtag configuration of stratix and stratix gx devices, you should consider the regular configuration pins. table 11?12 shows how you should connect these pins during jtag configuration. jtag programming & configuration of multiple devices when programming a jtag device ch ain, one jtag-compatible header, such as the byteblastermv header, is connected to several devices. the number of devices in the jtag chain is limited only by the drive capacity of the download cable. however, when more than five devices are connected in a jtag chain, altera recommends buffering the tck , tdi , and tms pins with an on-board buffer. table 11?12. dedicated configuration pin connections during jtag configuration signal description nce on all stratix and stratix gx devices in the chain, nce should be driven low by connecting it to ground, pulling it low via a resistor, or driving it by some control circuitry. for devices that are also in multi-device ps, fpp or ppa configuration chains, the nce pins should be connected to gnd during jtag configuration or jtag configured in the same or der as the configuration chain. nceo on all stratix and stratix gx devices in the chain, nceo can be left floating or connected to the nce of the next device. see nce pin description above. msel these pins must not be left floating. these pi ns support whichever non-jtag configuration is used in production. if only jtag configuration is used, you should tie both pins to ground. nconfig nconfig must be driven high through the jtag programming process. driven high by connecting to v cc , pulling high via a resistor, or dr iven by some control circuitry. nstatus pull to v cc via a 10-k resistor. when configuring multiple devices in the same jtag chain, each nstatus pin should be pulled up to v cc individually. nstatus pulling low in the middle of jtag configuration indicates that an error has occurred. conf_do ne pull to v cc via a 10-k resistor. when configuring multiple devices in the same jtag chain, each conf_done pin should be pulled up to v cc individually. conf_done going high at the end of jtag configuration indicates successful configuration. dclk should not be left floating. drive low or high, whichever is more convenient on your board. data0 should not be left floating. drive low or high, whichever is more convenient on your board. 11?40 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes jtag-chain device programming is ideal when the pcb contains multiple devices, or when testing the pcb using jtag bst circuitry. figure 11?21 shows multi-device jtag configuration. figure 11?21. multi-device jtag configuration notes (1) , (2) notes to figure 11?21 : (1) stratix, stratix gx, apex tm ii, apex 20k, mercury tm , acex ? 1k, and flex ? 10k devices can be placed within the same jtag chain for device programming and configuration. (2) for more information on all configur ation pins connected in this mode, see table 11?11 on page 11?37 . (3) connect the nconfig , msel0 , msel1 , and msel2 pins to support a non-jtag conf iguration scheme. if only jtag configuration is used, connect nconfig to v cc , and msel0 , msel1 , and msel2 to ground. pull data0 and dclk to either high or low. (4) v io is a reference voltage for the masterblaster output driver. v io should match the device?s v ccio . see the masterblaster serial/usb communications cable data sheet for this value. (5) nce must be connected to gnd or driven low for successful jtag configuration. the nce pin must be connected to gnd or driven low during jtag configuration. in multi-device ps, fpp and ppa configuration chains, the first device's nce pin is connected to gnd while its nceo pin is connected to nce of the next device in the chain. the last device's nce input comes from the previous device, while its nceo pin is left floating. after the first device completes configuration in a multi-device configuration chain, its nceo pin drives low to activa te the second device's nce pin, which prompts the second device to begin configuration. therefore, if these devices are also in a jtag chain, you should make sure the nce pins are connected to gnd during jtag configuration or that the devices are jtag configured in the same order as the configuration chain. as long as the devices are jtag configured in the same order as the multi-device configuration chain, the nceo of the previous device drives nce of the next device low when it has succ essfully been jtag configured. tms tck m asterb l aster o r b y teb l aster mv 10- p in m a l e h eader tdi tdo vcc v cc v cc p in 1 nstatus nconfig msel2 msel1 nce v cc conf_done v cc tms tck tdi tdo nconfig msel2 msel1 nce v cc conf_done v cc tms tck tdi tdo nconfig msel2 msel1 nce v cc conf_done v cc 1 k (3) (3) (3) msel0 (3) (3) (3) (3) msel0 (3) (3) dclk dclk dclk (3) (3) (3) data 0 data0 data0 (3) (3) (3) (3) (3) msel0 (3) vio (4) stratix device stratix device stratix device 1 k nstatus nstatus 10 k 10 k 10 k 10 k 10 k 10 k (5) (5) (5) 1 k altera corporation 11?41 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices the quartus ii software verifies su ccessful jtag configuration upon completion. the software checks the state of conf_done through the jtag port. if conf_done is not in the correct state, the quartus ii software indicates that configuration has failed. if conf_done is in the correct state, the software indicate s that configuration was successful. 1 if vccio is tied to 3.3 v, both the i/o pins and jtag tdo port drive at 3.3-v levels. do not attempt jtag and non-jtag configuration simultaneously. when configuring through jtag, allow any non-jtag configuration to complete first. figure 11?22 shows the jtag configuration of a stratix or stratix gx device with a microprocessor. figure 11?22. jtag configurat ion of stratix & strati x gx devices with a microprocessor notes to figure 11?22 : (1) connect the nconfig , msel2 , msel1 , and msel0 pins to support a non-jtag configuration scheme. if your design only uses jtag configuration, connect the nconfig pin to v cc and the msel2 , msel1 , and msel0 pins to ground. (2) pull data0 and dclk to either high or low. configuration with jrunner software driver jrunner is a software driver that allows you to configure altera fpgas through the byteblastermv download cable in jtag mode. the programming input file supported is in raw binary file ( .rbf ) format. jrunner also requires a chain description file ( .cdf ) generated by the quartus ii software. jrunner is targeted for embedded jtag configuration. the source code has been developed for the windows nt operating system. you can customize the code to make it run on other platforms. nconfig data0 dclk tdi tck tms microprocessor memory addr data tdo stratix or stratix gx device nstatus conf_done v cc v cc 10 k 10 k (2) (1) (2) (1) (1) (1) msel2 msel1 msel0 11?42 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes f for more information on the jrunner software driver, see the jrunner software driver: an embedded soluti on to the jtag configuration white paper and zip file. jam stapl programming & test language the jam tm standard test and programming language (stapl), jedec standard jesd-71, is a standa rd file format for in-system programmability (isp) pu rposes. jam stapl supports programming or configuration of programmable devices and testing of electronic systems, using the ieee 1149.1 jtag interface. jam stapl is a freely licensed open standard. connecting the jtag chain to the embedded processor there are two ways to connect the jt ag chain to the embedded processor. the most straightforward method is to connect the embedded processor directly to the jtag chain. in this method, four of the processor pins are dedicated to the jtag interface, sa ving board space but reducing the number of available embedded processor pins. figure 11?23 illustrates the second method , which is to connect the jtag chain to an existing bus through an interface pld. in this method, the jtag chain becomes an address on th e existing bus. the processor then reads from or writes to the addr ess representing the jtag chain. altera corporation 11?43 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?23. embedded system block diagram notes to figure 11?23 : (1) connect the nconfig , msel2 , msel1 , and msel0 pins to support a non-jtag conf iguration scheme. if your design only uses jtag configuration, connect the nconfig pin to v cc and the msel2 , msel1 , and msel0 pins to ground. (2) pull data0 and dclk to either high or low. both jtag connection methods should include space for the masterblaster or byteblastermv header connection. the header is useful during prototyping because it allows you to verify or modify the stratix or stratix gx device?s contents. du ring production, you can remove the header to save cost. tdi tms tck tdo tdi tms tck tdo tdi tms tck tdo tdi tms tck tdo tdi tms tck tdo control control d[3..0] d[7..0] adr[19..0] control d[7..0] adr[19..0] adr[19..0] interface logic (optional) any jtag device eprom or system memory to/from byteblaster m v embedded processor embedded system 8 8 4 20 20 20 m ax ? 9 000, m ax 9 000 a , m ax 7 000 s , m ax 7 000 a , m ax 7 000 ae , or m ax 3 000 device cyclone fpga tdi tms trst conf_done nstatus nconfig msel0 msel1 nce tck tdo any cyclone , flex 1 0 k , flex 1 0 ka , flex1 0 ke , apex 2 0 k , or apex 2 0 ke device 10 k 10 k v cc v cc v cc gnd data0 dclk nconfig (2) (2) (1) (1) (1) msel1 msel0 11?44 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes program flow the jam player provides an inte rface for manipulating the ieee std. 1149.1 jtag tap state machine. th e tap controller is a 16-state state machine that is clocked on the rising edge of tck , and uses the tms pin to control jtag operation in a device. figure 11?24 shows the flow of an ieee std. 1149.1 tap co ntroller state machine. altera corporation 11?45 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?24. jtag tap controller state machine while the jam player provides a driver that manipulates the tap controller, the jam byte-code file ( .jbc ) provides the high-level intelligence needed to program a given device. all jam instructions that select_dr_scan capture_dr shift_dr exit1_dr pause_dr exit2_dr update_dr shift_ir exit1_ir pause_ir exit2_ir update_ir tms = 0 tms = 0 tms = 0 tms = 1 tms = 0 tms = 1 tms = 1 tms = 0 tms = 1 tms = 0 tms = 1 tms = 1 tms = 0 tms = 0 tms = 1 tms = 1 tms = 0 tms = 1 tms = 0 tms = 0 tms = 1 tms = 0 tms = 0 tms = 1 tms = 0 run_test/ idle tms = 0 test_logic/ reset tms = 1 tms = 0 tms = 1 tms = 1 tms = 1 tms = 1 capture_ir select_ir_scan 11?46 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes send jtag data to the device involve moving the tap controller through either the data register leg or the instruction register leg of the state machine. for example, loading a jtag instruction involves moving the tap controller to the shift_ir state and shifting the instruction into the instruction register through the tdi pin. next, the tap controller is moved to the run_test/idle state where a delay is implemented to allow the instruction time to be latched. this process is identical for data register scans, except that the data register leg of the state machine is traversed. the high-level jam instructions are the drscan instruction for scanning the jtag data register, the irscan instruction for scanning the instruction register, and the wait command that causes the state machine to sit idle for a specified period of ti me. each leg of the tap controller is scanned repeatedly, according to instructions in the jbc file, until all of the target devices are programmed. figure 11?25 illustrates the functional behavi or of the jam player when it parses the jbc file. when th e jam player encounters a drscan , irscan , or wait instruction, it generates the proper data on tck , tms , and tdi to complete the instruction. the flow diagram shows branches for the drscan , irscan , and wait instructions. although the jam player supports other instructions, they are omitted from the flow diagram for simplicity. altera corporation 11?47 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices figure 11?25. jam player flow diagram (part 1 of 2) set tms to 1 and pulse tck twice set tms to 0 and pulse tck twice switch case[] eof start switch end eof? test-logic-reset run-test/idle set tms to 1 and pulse tck five times set tms to 0 and pulse tck read instruction from the jam file set tms to 1 and pulse tck three times f t test-logic-reset parse argument irscan drscan switch set tms to 0 and pulse tck delay wait run-test/idle select-ir-scan shift-ir set tms to 0 and pulse tck and write tdi set tms to 0 and pulse tck and write tdi set tms to 1 and pulse tck set tms to 0 and pulse tck set tms to 1 and pulse tck twice set tms to 0 and pulse tck shift-ir exit1-ir pause-ir update-ir run-test/idle shift-dr set tms to 0 and pulse tck and write tdi set tms to 0 and pulse tck twice set tms to 1 and pulse tck parse argument shift-dr select-dr-scan continued on part 2 of flow diagram f t shift-ir 11?48 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes figure 11?26. jam player flow diagram (part 2 of 2) execution of a jam program starts at the beginning of the program. the program flow is controlled using goto , call/return , and for/next structures. the goto and call statements see labels that are symbolic names for program statements located elsewhere in the jam program. the language itself enforces almost no constraints on the organizational structure or control flow of a program. 1 the jam language does not support linking multiple jam programs together or including th e contents of another file into a jam program. switch update-ir run-test/idle set tms to 1 and pulse tck set tms to 0 and pulse tck switch update-ir run-test/idle set tms to 1 and pulse tck set tms to 0 and pulse tck set tms to 1 and pulse tck and store tdo set tms to 0 and pulse tck, write tdi, and store tdo shift-dr exit1-dr f f t report error default case[] loop< dr length set tms to 1 and pulse tck and store tdo set tms to 0 and pulse tck, write tdi, and store tdo compare capture exit1-dr switch update-ir run-test/idle set tms to 1 and pulse tck set tms to 0 and pulse tck loop< dr length set tms to 1 and pulse tck and store tdo set tms to 0 and pulse tck and write tdi exit1-dr continued from part 1 of flow diagram correct tdo value t f f t t loop< dr length altera corporation 11?49 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices jam instructions each jam statement begins with one of the instruction names listed in table 11?13 . the instruction names, includ ing the names of the optional instructions, are reserved keywords that you cannot use as variable or label identifiers in a jam program. table 11?14 shows the state names that are reserved keywords in the jam language. these keywords correspond to the state names specified in the ieee std. 1149.1 jtag specification. table 11?13. instruction names boolean integer preir call irscan print crc irstop push drscan let return drstop next state exit note wait export pop vector (1) for postdr vmap (1) goto postir ? if predr ? note to table 11?13 : (1) this instruction name is an optional language extension. table 11?14. reserved keywords (part 1 of 2) ieee std. 1149.1 jtag state na mes jam reserved state names test-logic-reset reset run-test-idle idle select-dr-scan drselect capture-dr drcapture shift-dr drshift exit1-dr drexit1 pause-dr drpause exit2-dr drexit2 update-dr drupdate select-ir-scan irselect 11?50 altera corporation stratix device handbook, volume 2 july 2005 configuration schemes example jam file that reads the idcode figure 11?27 illustrates the flexibility and utility of the jam stapl. the example reads the idcode out of a single device in a jtag chain. 1 the array variable, i_idcode , is initialized with the idcode instruction bits ordered the lsb first (on the left) to most significant bit (msb) (on the ri ght). this order is important because the array field in the irscan instruction is always interpreted, and sent, msb to lsb. figure 11?27. example jam file reading idcode capture-ir ircapture shift-ir irshift exit1-ir irexit1 pause-ir irpause exit2-ir irexit2 update-ir irupdate table 11?14. reserved keywords (part 2 of 2) ieee std. 1149.1 jtag state na mes jam reserved state names boolean read_data[32]; boolean i_idcode[10] = bin 1001101000; ?assumed boolean ones_data[32] = hex ffffffff; integer i; ?set up stop state for irscan irstop irpause; ?initialize device state reset; irscan 10, i_idcode[0..9]; ?load idcode instruction state idle; wait 5 usec, 3 cycles; drscan 32, ones_data[0..31], capture read_data[0..31]; ?capture idcode print ?idcode:?; for i=0 to 31; print read_data[i]; next i; exit 0; altera corporation 11?51 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices configuring using the microblaster driver the microblaster tm software driver allows you to configure altera devices in an embedded environment using ps or fpp mode. the microblaster software driver supports a raw binary file ( .rbf ) programming input file. the source code is developed for the windows nt operating system, although you can customize it to run on other operating systems. for more information on the microblaster software driver, go to the altera web site ( www.altera.com ). device configuration pins the following tables describe the conne ctions and functionality of all the configuration related pins on the stratix or stratix gx device. table 11?15 describes the dedicated configuration pins, which are required to be connected properly on your board for successful configuration. some of these pins may not be required for your configuration schemes. table 11?15. dedicated configuration pins on the stratix or stratix gx device (part 1 of 8) pin name user mode configuration scheme pin type description vccsel n/a all input dedicated input that selects which input buffer is used on the configuration input pins; nconfig , dclk , runlu , nce , nws , nrs , cs , ncs and clkusr . the vccsel input buffer is powered by v ccint and has an internal 2.5 k pull-down resistor that is always active. a logic high (1.5-v, 1.8-v, 2.5-v, 3.3-v) selects the 1.8-v/1.5-v input buffer, and a logic low selects the 3.3-v/2.5-v input buffer. see the ?v ccsel pins? section for more details. porsel n/a all input dedicated input which selects between a por time of 2 ms or 100 ms. a logic high (1.5-v, 1.8- v, 2.5-v, 3.3-v) selects a por time of about 2 ms and a logic low selects por time of about 100 ms. the porsel input buffer is powered by v ccint and has an internal 2.5 k pull-down resistor that is always active. 11?52 altera corporation stratix device handbook, volume 2 july 2005 device configuration pins nio_pullup n/a all input dedicated input that chooses whether the internal pull-ups on the user i/os and dual- purpose i/os ( data[7..0] , nws , nrs , rdynbsy , ncs , cs , runlu , pgm[] , clkusr , init_done , dev_oe , dev_clr ) are on or off before and during configuration. a logic high (1.5-v, 1.8-v, 2.5-v, 3.3-v) turns off the weak internal pull-ups, while a logic low turns them on. the nio_pullup input buffer is powered by v ccint and has an internal 2.5 k pull-down resistor that is always active. msel [2..0] n/a all input 3-bit configuration input that sets the stratix or stratix gx device configuration scheme. see table 11?2 for the appropriate connections. these pins can be connected to v ccio of the i/o bank they reside in or ground. this pin uses schmitt trigger input buffers. nconfig n/a all input configuration control input. pulling this pin low during user-mode causes the fpga to lose its configuration data, enter a reset state, tri-state all i/o pins. returning th is pin to a logic high level initiates a reconfiguration. if your configuration scheme uses an enhanced configuration device or epc2 device, nconfig can be tied directly to v cc or to the configuration device?s ninit_conf pin. this pin uses schm itt trigger input buffers. table 11?15. dedicated configuration pins on the stratix or stratix gx device (part 2 of 8) pin name user mode configuration scheme pin type description altera corporation 11?53 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices nstatus n/a all bidirectional open-drain the device drives nstatus low immediately after power-up and releases it after the por time. status output. if an error occurs during configuration, nstatus is pulled low by the target device. status input. if an external source drives the nstatus pin low during configuration or initialization, the target device enters an error state. driving nstatus low after configuration and initialization does not affect the configured device. if a configuration device is used, driving nstatus low causes the configuration device to attempt to configure the fpga, but since the fpga ignores transitions on nstatus in user- mode, the fpga does not reconfigure. to initiate a reconfiguration, nconfig must be pulled low. the enhanced configuration devices? and epc2 devices? oe and ncs pins have optional internal programmable pull-up resistors. if internal pull-up resistors on the enhanced configuration device are used, external 10-k pull-up resistor s should not be used on these pins. when using epc2 de vices, only external 10-k pull-up resistors should be used. this pin uses schmitt trigger input buffers. table 11?15. dedicated configuration pins on the stratix or stratix gx device (part 3 of 8) pin name user mode configuration scheme pin type description 11?54 altera corporation stratix device handbook, volume 2 july 2005 device configuration pins conf_done n/a all bidirectional open-drain status output. the target fpga drives the conf_done pin low before and during configuration. once al l configuration data is received without error and the initialization cycle starts, the target device releases conf_done . status input. after all data is received and conf_done goes high, the target device initializes and enters user mode. the conf_done pin must have an external 10-k pull-up resistor in order for the device to initialize. driving conf_done low after configuration and initialization does not affect the configured device. the enhanced configuration devices? and epc2 devices? oe and ncs pins have optional internal programmable pull-up resistors. if internal pull-up resistors on the enhanced configuration device are used, external 10-k pull-up resistor s should not be used on these pins. when using epc2 de vices, only external 10-k pull-up resistors should be used. this pin uses schmitt trigger input buffers. nce n/a all input active-low chip enable. the nce pin activates the device with a low signal to allow configuration. the nce pin must be held low during configuration, initialization, and user mode. in single device configuration, it should be tied low. in multi-device configuration, nce of the first device is tied low while its nceo pin is connected to nce of the next device in the chain. the nce pin must also be held low for successful jtag programming of the fpga. this pin uses schmitt trigger input buffers. table 11?15. dedicated configuration pins on the stratix or stratix gx device (part 4 of 8) pin name user mode configuration scheme pin type description altera corporation 11?55 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices nceo n/a all multi- device schemes output output that drives low when device configuration is complete. in single device configuration, this pin is left floating. in multi- device configuration, this pin feeds the next device?s nce pin. the nceo of the last device in the chain is left floating. the voltage levels driven out by this pin are dependent on the v ccio of the i/o bank it resides in. dclk n/a synchronous configuration schemes (ps, fpp) input (ps, fpp) in ps and fpp configuration, dclk is the clock input used to clock data from an external source into the target device. data is latched into the fpga on the rising edge of dclk . in ppa mode, dclk should be tied high to v cc to prevent this pin from floating. after configuration, this pin is tri-stated. in schemes that use a configuration device, dclk is driven low after configuration is done. in schemes that use a control host, dclk should be driven either high or low, whichever is more convenient. toggling this pin after configuration does not affect the configured device. this pin uses schmitt trigger input buffers. data0 i/o ps, fpp, ppa input data input. in serial configuration modes, bit- wide configuration data is presented to the target device on the data0 pin. the v ih and v il levels for this pin are dependent on the v ccio of the i/o bank that it resides in. after configuration, data0 is available as a user i/o and the state of this pin depends on the dual-purpose pin settings. after configuration, epc1 and epc1441 devices tri-state this pin, while enhanced configuration and epc2 devices drive this pin high. table 11?15. dedicated configuration pins on the stratix or stratix gx device (part 5 of 8) pin name user mode configuration scheme pin type description 11?56 altera corporation stratix device handbook, volume 2 july 2005 device configuration pins data[7..1] i/o parallel configuration schemes (fpp and ppa) inputs data inputs. byte-wide configuration data is presented to the target device on data[7..0] . the v ih and v il levels for these pins are dependent on the v ccio of the i/o banks that they reside in. in serial configuration schemes, they function as user i/os during configuration, which means they are tri-stated. after ppa or fpp configuration, data[7..1] are available as a user i/os and the state of these pin depends on the dual-purpose pin settings. data7 i/o ppa bidirectional in the ppa configuration scheme, the data7 pin presents the rdynbsy signal after the nrs signal has been strobed low. the v il and v il levels for this pin are dependent on the v ccio of the i/o bank that it resides in. in serial configuration schemes, it functions as a user i/o during configur ation, which means it is tri-stated. after ppa configuration, data7 is available as a user i/o and the state of this pin depends on the dual-purpose pin settings. nws i/o ppa input write strobe input. a low-to-high transition causes the device to latch a byte of data on the data[7..0] pins. in non-ppa schemes, it functions as a user i/o during configuration, which means it is tri- stated. after ppa configuration, nws is available as a user i/o and the state of this pin depends on the dual-purpose pin settings. table 11?15. dedicated configuration pins on the stratix or stratix gx device (part 6 of 8) pin name user mode configuration scheme pin type description altera corporation 11?57 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices nrs i/o ppa input read strobe input. a low input directs the device to drive the rdynbsy signal on the data7 pin. if the nrs pin is not used in ppa mode, it should be tied high. in non-ppa schemes, it functions as a user i/o during configuration, which means it is tri-stated. after ppa configuration, nrs is available as a user i/o and the state of this pin depends on the dual-purpose pin settings. rdynbsy i/o ppa output ready output. a high output indicates that the target device is ready to accept another data byte. a low output indicates that the target device is busy and not ready to receive another data byte. in ppa configuration schemes, this pin drives out high after power-up, before configuration and after configuration before entering user- mode. in non-ppa schemes, it functions as a user i/o during configurat ion, which means it is tri-stated. after ppa configuration, rdynbsy is available as a user i/o and the state of this pin depends on the dual-purpose pin settings. table 11?15. dedicated configuration pins on the stratix or stratix gx device (part 7 of 8) pin name user mode configuration scheme pin type description 11?58 altera corporation stratix device handbook, volume 2 july 2005 device configuration pins ncs/cs i/o ppa input chip-select inputs. a low on ncs and a high on cs select the target device for configuration. the ncs and cs pins must be held active during configuration and initialization. during the ppa configuration mode, it is only required to use either the ncs or cs pin. therefore, if only one chip-select input is used, the other must be tied to the active state. for example, ncs can be tied to gnd while cs is toggled to control conf iguration.in non-ppa schemes, it functions as a user i/o during configuration, which means it is tri-stated. after ppa configuration, ncs and cs are available as a user i/os and the state of these pins depends on the dual-purpose pin settings. runlu n/a if using remote configuration; i/o if not remote configuration in fpp, ps or ppa input input that selects between remote update and local update. a logic high (1.5-v, 1.8-v, 2.5-v, 3.3-v) selects remote update and a logic low selects local update. when not using remote update or local update configuration modes, this pins is available as general-purpose user i/o pin. pgm[2..0] n/a if using remote configuration; i/o if not using remote configuration in fpp, ps or ppa input these output pins select one of eight pages in the memory (either flash or enhanced configuration device) when using a remote configuration mode. when not using remote update or local update configuration modes, these pins are available as general-purpose user i/o pins. table 11?15. dedicated configuration pins on the stratix or stratix gx device (part 8 of 8) pin name user mode configuration scheme pin type description altera corporation 11?59 july 2005 stratix device handbook, volume 2 configuring stratix & stratix gx devices table 11?16 describes the option al configuration pins. if these optional configuration pins are not enabled in the quartus ii software, they are available as general-purpose us er i/o pins. therefore during configuration, these pins function as user i/o pins and are tri-stated with weak pull-ups. table 11?16. optional configuration pins pin name user mode pin type description clkusr n/a if option is on. i/o if option is off. input optional user-supplied cl ock input. synchronizes the initialization of one or more de vices. this pin is enabled by turning on the enable user-supplied start-up clock (clkusr) option in the quartus ii software. init_done n/a if option is on. i/o if option is off. output open- drain status pin. can be used to indicate when the device has initialized and is in user mode. when nconfig is low and during the beginning of configuration, the init_done pin is tri-stated and pulled high due to an external 10-k pull-up. once the option bit to enable init_done is programmed into the device (during the firs t frame of configuration data), the init_done pin goes low. when initialization is complete, the init_done pin is released and pulled high and the fpga enters user mode. thus, the monitoring circuitry must be able to detect a low-to-high transition. this pin is enabled by turning on the enable init_done output option in the quartus ii software. dev_oe n/a if option is on. i/o if option is off. input optional pin that allows the us er to override al l tri-states on the device. when this pin is driv en low, all i/os are tri-stated. when this pin is driven high, all i/os behave as programmed. this pin is enabled by turning on the enable device-wide output enable (dev_oe) option in the quartus ii software. dev_clrn n/a if option is on. i/o if option is off. input optional pin that allows y ou to override all clears on all device registers. when this pin is driven low, all registers are cleared. when this pin is driven high, all registers behave as programmed. this pin is enabled by turning on the enable device-wide reset (dev_clrn) option in the quartus ii software. 11?60 altera corporation stratix device handbook, volume 2 july 2005 device configuration pins table 11?17 describes the dedicated jtag pins. jtag pins must be kept stable before and during configuratio n to prevent accidental loading of jtag instructions. if you plan to use the signaltap ii embedded logic analyzer, you will need to connect the jtag pins of your device to a jtag header on your board. table 11?17. dedicated jtag pins pin name user mode pin type description tdi n/a input serial input pin for inst ructions as well as test and programming data. data is shifted in on the rising edge of tck . if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc . this pin uses schmi tt trigger input buffers. tdo n/a output serial data output pin for instructions as well as test and programming data. data is shifted out on the falling edge of tck . the pin is tri-stated if data is not being shifted out of the device. if the jtag interface is not required on the board, the jtag circuitry can be disabled by leaving this pin unconnected. tms n/a input input pin that provides the control signal to determine the transitions of the tap controll er state machine. transitions within the state machine occur on the rising edge of tck . therefore, tms must be set up before the rising edge of tck . tms is evaluated on the rising edge of tck . if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to v cc . this pin uses schmitt trigger input buffers. tck n/a input the clock input to the bst circuitry. some operations occur at the rising edge, while others occur at the falling edge. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to gnd. this pin uses schmitt trigger input buffers. trst n/a input active-low input to asynchronously reset the boundary- scan circuit. the trst pin is optional according to ieee std. 1149.1. if the jtag interface is not required on the board, the jtag circuitry can be disabled by connecting this pin to gnd. this pin uses schmitt trigger input buffers. altera corporation 12?1 september 2004 12. remote system configuration with stratix & stratix gx devices introduction altera ? stratix ? and stratix gx devices are the first programmable logic devices (plds) featuring dedicated support for remote system configuration. using remote system configuration, a stratix or stratix gx device can receive new configuration data from a remote source, update the flash memory content (through enhanced configuration devices or any other storage device), and then reconfigure itself with the new data. like all altera sram-based devices, stratix and stratix gx devices support standard configuration modes such as passive serial (ps), fast passive parallel (fpp), and passive pa rallel asynchronous (ppa). you can use the standard configuration modes with remote system configuration. this chapter discusses remote system configuration of stratix and stratix gx devices, and how to interface th em with enhanced configuration devices to enable this capability. this document also explains some related remote system configuration topics, such as the watchdog timer, remote system configuration regist ers, and factory or application configurations files. the quartus ? ii software (version 2.1 and later) supports remote system configuration. remote configuration operation remote system configuration has three major parts: the stratix or stratix gx device receives updated or new data from a remote source over a network (or through any other source that can transfer data). you can implemen t a nios? (16-bit isa) or nios ? ii (32-bit isa) embedded processor with in either a stratix or stratix gx device or an external processo r to control the read and write functions of configuration files from the remote source to the memory device. the new or updated information is stored into the memory device, which can be an enhanced config uration device, industry-standard flash memory device, or any other storage device (see figure 12?2 ). the stratix or stratix gx device updates itself with the new data from the memory. figure 12?1 shows the concept of remote sy stem configuration in stratix and stratix gx devices. s52015-3.1 12?2 altera corporation stratix device handbook, volume 2 september 2004 remote configuration operation figure 12?1. remote system configuration with stratix & stratix gx devices figure 12?2. different options for remote system configuration development location stratix or stratix gx device control module memory stratix device configuration network data data data external processor stratix or stratix gx device processor flash enhanced configuration device stratix or stratix gx device enhanced configuration device max device flash memory nios max device & flash memory stratix or stratix gx device processor nios processor altera corporation 12?3 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices remote system configuration modes stratix and stratix gx device remote system configuration has two modes: remote configuration mode and local configuration mode. table 12?1 shows the pin selection settings for each configuration mode. remote configuration mode using remote configuration mode, you can manage up to seven different application configurations for stratix and stratix gx devices. the seven- configuration-file limit is due to the number of pages that the pgm[] pins in the stratix or stratix gx device and enhanced configuration devices can select. 1 if more than seven files are sent to a system using remote configuration mode, previous files are overwritten. stratix and stratix gx devices support remote configuration mode for ps, fpp, and ppa modes. specify remote configuration mode by setting the msel2 and runlu pins to high. (see table 12?1 ). on power-up in remote configuration mode, the stratix or stratix gx device loads the user-specified factory configuration file, located in the default page address 000 in the enhanced configuration device. after the device configures, the remote configur ation control register points to the table 12?1. standard, remote & local configuration options note (1) runlu (2) msel[2] (3) msel[1..0] system configuration mode configuration mode ? 0 00 standard fpp ? 0 01 standard ppa ? 0 10 standard ps 1100 remote fpp 1101 remote ppa 1110 remote ps 0 1 00 local fpp 0 1 01 local ppa 0 1 10 local ps notes to table 12?1 : (1) for detailed information on standa rd ps, fpp, and ppa models, see the configuring stratix & stratix gx devices chapter of the stratix device handbook, volume 2 . (2) in stratix and stratix gx devices, the runlu (remote update/local update) pin, selects between local or remote configuration mode. (3) the msel[2] select mode selects between standard or remote system configuration mode. 12?4 altera corporation stratix device handbook, volume 2 september 2004 remote configuration operation page address of the application config uration that should be loaded into the stratix or stratix gx device. if an error occurs during user mode of an application configuration, the de vice reloads the default factory configuration page. figure 12?3 shows a diagram of remote configuration mode. figure 12?3. remote configuration mode local configuration mode local configuration mode?a simplified version of remote configuration mode?is suitable for systems that lo ad an application immediately upon power-up. in this mode you can only use one application configuration, which you can update either remotely or locally. in local configuration mode, upon power-up, or when nconfig is asserted, the stratix or stratix gx device loads the application configuration immediately. factory co nfiguration loads only if an error occurs during the application config uration?s user mode. if you use an enhanced configuration device, page address 001 is the location for the application configuration data, and page address 000 is the location for the factory configuration data. if the configuration data at page address 001 does not load correctly due to cyclic redundancy code (crc) failur e, or it times-ou t of the enhanced configuration device, or the external processor times-out, then the factory configuration located at the default page (page address 000 ) loads into the stratix or stratix gx device. in local configuration mode (shown in figure 12?4 ), the user watchdog timer is disabled. for more inform ation on the watchdog timer, see ?watchdog timer? on page 12?7 . power up configuration error errors reconfigure errors reconfigure application 7 configuration pgm [111] factory configuration page (000) application 1 configuration pgm [001] altera corporation 12?5 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices figure 12?4. local configuration mode in local configuration mode, one appl ication configuration is available to the device. for remote or local configuration mode selection, see table 12?1 . remote system configuration components the following components are used in stratix and stratix gx devices to support remote and local configuration modes: page mode feature factory configuration application configuration watchdog timer remote update sub-block remote configuration registers a description of each component follows. page mode feature the page mode feature enables stratix and stratix gx devices to select a location to read back data for conf iguration. the enha nced configuration device can receive and store up to eigh t different configuration files (one factory and seven application files). selection of pages to read from is performed through the pgm[2..0] pins on the stratix or stratix gx device and enhanced configuration devices. these pins in the stratix or stratix gx device can be designated user i/o pins during standard configuration mode, but in remote system configuration mode, they are dedicated output pins. figure 12?5 shows the page mode feature in stratix or stratix gx devices and enhanced configuration devices. power up or nconfig assertion nconfig nconfig configuration error configuration error application configuration pgm[001] factory configuration pgm[000] 12?6 altera corporation stratix device handbook, volume 2 september 2004 remote configuration operation figure 12?5. page mode feature in stratix or stratix gx devices & enhanced configuration devices upon power-up in remote configurat ion mode, the factory configuration (see description below) selects the us er-specified page address through the stratix or stratix gx pgm[2..0] output pins. these pins drive the pgm[2..0] input pins of the enhanced co nfiguration device and select the requested page in the memory. if an intelligent host is used instea d of an enhanced configuration device, you should create logic in the intelligent host to support page mode settings similar to that in e nhanced configuration devices. factory configuration factory configuration is the default co nfiguration data setup. in enhanced configuration devices, this default page address is 000 . factory configuration data is written into th e memory device only once by the system manufacturer and should not be remotely updated or altered. in remote configuration mode, the fa ctory configuration loads into the stratix or stratix gx device upon power-up. the factory configuration specifications are as follows: receives new configuration data and writes it to the enhanced configuration or other memory devices determines the page address for the next application configuration that should be loaded to the stratix or stratix gx device upon an error in the application configuration, the system reverts to the factory configuration determines the reason for any application configuration error determines whether to enable or di sable the user watchdog timer for application configurations enhanced configuration device stratix or stratix gx device page select pof 8 pof 1 stratix 1 page0 tix7 altera corporation 12?7 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices determines the user watc hdog timer?s settings if the timer is enabled (remote configuration mode) if the user watchdog timer is not reset after a predetermined amount of time, it times-out and the syst em loads the factory configuration data back to the stratix or stratix gx device if a system encounters an error wh ile loading application configuration data, or if the device re-configures due to nconfig assertion, the stratix or stratix gx device loads the factor y configuration. the remote system configuration register determines the reason for factory re-configuration. based on this information, the factory configuration determines which application configuratio n needs to be loaded. application configuration the application configuration is the co nfiguration data received from the remote source and updated into diff erent locations or pages of the memory storage device (excludi ng the factory default page). watchdog timer a watchdog timer is a circuit th at determines whether another mechanism functions properly. the watc hdog timer functions like a time- delay relay that remains in the reset state while an application runs properly. this action periodically sends a reset command from the working application to the watchdog timer. stratix and stratix gx devices are equipped with a built-in watchdog timer for remote system configuration. a user watchdog timer prevents a fa ulty application co nfiguration from indefinitely stalling the stratix or stratix gx device. the timer functions as a counter that counts down from an initial value, which is loaded into the device from the factory configuratio n. this is a 29-bit counter, but you use only the upper 12 bits to set th e value for the watchdog timer. you specify the counter value acco rding to your design needs. the timer begins counting once the st ratix or stratix gx device goes into user mode. if the application configuration does not reset the user watchdog timer after the specified time, the timer times-out. at this point, the stratix or stratix gx device is re-configured by lo ading the factory configuration and resetting the user watchdog timer. 1 the watchdog timer is disabled in local configuration mode. 12?8 altera corporation stratix device handbook, volume 2 september 2004 remote configuration operation remote update sub-block the remote update sub-block is respon sible for administrating the remote configuration feature. this sub-block, which is controlled by a remote configuration state machine, generate s the control signals required to control different remote configuration registers. remote configuration registers remote configuration registers are a series of registers required to keep track of page addresses and the cause of configuration errors. table 12?2 gives descriptions of the registers? functions. you can control both the update and shift registers; the status and control registers are controlled by internal logic, but can be read via the shift register. figure 12?6 shows the control, update, shif t, and status registers and the data path used to control remote system configuration. table 12?2. remote configuration registers register description control register this register contains the current page address, the watchdog timer setting, and one bit specifying if the current confi guration is a factory or application configuration. during a capture in an applic ation configuration, this register is read into the shift register. update register this register cont ains the same data as the control register, except that it is updated by the factory configuration. the factory configuration updates the register with the values to be used in the control register on the next re- configuration. during capture in a factory c onfiguration, this r egister is read into the shift register. shift register this register is accessible by the core logic and allows the update, status, and control registers to be written and sample d by the user logic. the update register can only be updated by the factory configur ation in remote configuration mode. status register this register is written into by the remote configuration block on every re- configuration to record the cause of the re-configuration. this information is used by factory configuration to determine the appropriate action following a re- configuration. altera corporation 12?9 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices figure 12?6. remote configuration registers & related data path table 12?3 describes the user configuration signals that are driven to/from the device logic array. the remote configuration logic has one input signal to the device logic ar ray and six output signals from the device logic array. status register control register update register logic shift register control logic to reconfig logic user watchdog timer ru_dout ru_shftnhld ru_captnupdt ru_din ru_clk ru_timer ru_nconfig device core bit4...bit10 bit16...bit0 bit0...bit16 table 12?3. user configuration signals to/from device core (part 1 of 2) signal name to/from device core description ru_timer output from the core to the remote update block request from the application to reset the user watchdog timer with its initial count. a falling edge of this signal triggers a reset of the user watchdog timer. ru_nconfig output from the core to the remote update block when driven low, this signal triggers the device to reconfigure. if requested by the factory configuration, the application configuration spec ified in the remote update control register is loaded. if requested by the application configuration, the factory configuration is loaded. ru_clk output from the core to the remote update block clocks the remote configuration shift register so that the contents of the status and control registers can be read out, and the contents of update register can be loaded. the shift register latches data on the rising edge of the ru_clk . 12?10 altera corporation stratix device handbook, volume 2 september 2004 remote configuration operation all of the seven device core signals (see figure 12?6 ), are enabled for both remote and local configuration for both factory and application configuration, except ru_timer and ru_captnupdt . figure 12?7 and table 12?4 specify the content of control register upon power-on reset (por). the difference between local configuration and remote configuration is how the control register is updated during a re-configuration and which core signals are enabled. ru_shftnhld output from the core to the remote update block if its value is ?1?, the remote configuration shift register shifts data on the rising edge of ru_clk . it its value is ?0? and ru_captnupdt is ?0?, the shift register updates the update register. if its value is ?0?, and ru_captnupdt is ?1?, the shift register captures the status register and either the control or update register (depending on whether the configuration is factory or application). ru_captnupdt output from the core to the remote update block when ru_captnupdt is at value ?1? and ru_shftnhld is at value?0?, the system specifies that the remote configuration shift register should be written with the content of the stat us register and either the update register (in a factory c onfiguration) or the control register (in an application configuration). this shift register is loaded on the rising edge of ru_clk . when ru_captnupdt is at value ?0? and ru_shftnhld is at value?0?, the system specifies that the remote configuration update register should be written with the content of the shift register in a factory configuration. the update register is loaded on the rising edge of ru_clk . this pin is enabled only fo r factory configuration in remote configuration mode (it is disabled for the application configuration in re mote configuration or for local configuration modes). if ru_shftnhld is at value ?1?, ru_captnupdt has no function. ru_din output from the core to the remote update block data to be written into the remote configuration shift register on the rising edge of ru_clk . to load into the shift register, ru_shftnhld must be asserted. ru_dout input to the core from the remote update block output of the remote confi guration shift register to be read by core logic. new data arrives on each rising edge of ru_clk . table 12?3. user configuration signals to/from device core (part 2 of 2) signal name to/from device core description altera corporation 12?11 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices figure 12?7. remote system conf iguration control register table 12?4 shows the content of the control register upon por. the status register specifies the reas on why re-configuration has occurred and determines if the re-configuration was due to a crc error, nstatus pulled low due to an error, the device core caused an error, nconfig was reset, or the watchdog timer timed-out. figure 12?8 and table 12?5 specify the content of the status register. figure 12?8. remote system conf iguration status register table 12?4. control register contents parameter definition por reset value comment anf current configuration is factory or applications 1 bit ?1? applications 1 bit ?0? factory pgm[2..0] page mode selection 3 bits ?001? local configuration 3 bits ?000? remote configuration wd_en user watchdog timer enable 1 bit ?0? ? wd_timer [11..0] user watchdog timer time-out value 12 bits ?0? high order bits of 29 bit counter wd nconfig core nstatus crc 43210 12?12 altera corporation stratix device handbook, volume 2 september 2004 quartus ii software support table 12?5 shows the content of the status register upon por. quartus ii software support the quartus ii software supports impl ementation of both remote and local configuration modes in your stratix or stratix ii device. to include the remote or local configuration feat ure to your design, select remote or local as the configuration mode under the device & pin options compiler settings (prior to compilation). this selection reserves the dual- purpose runlu and pgm[2:0] pins for use as dedicated inputs in remote/local configuration modes. to set the configuration mode as remo te or local, follow these steps (see figure 12?9 ): 1. open the device & pin options settings window under the assignments menu. 2. select device & pin options dialog box. the device & pin options dialog box is displayed. 3. click the configuration tab. 4. in the configuration mode list, select remote or local . the standard mode selection disables the remote system configuration feature. in addition to the mode selection, you can specify the configuration scheme and configuration device (if any) used by your setup. table 12?5. status register contents parameter definition por reset value crc (from configuration) crc caused re-configuration 1 bit ?0? nstatus nstatus caused re-configuration 1 bit ?0? core (1) device core caused re-configuration 1 bit ?0? nconfig nconfig caused re-configuration 1 bit ?0? wd watchdog timer caused re-configuration 1 bit ?0? note to table 12?5 : (1) core re-configuration enforces the syst em to load the application configuration data into the stratix or stratix gx device . this occurs after factory configuration specifies the appropriate application configuration data. altera corporation 12?13 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices figure 12?9. device & pin options dialog box additionally, the remote configuration mode requires you to either instantiate the altremote_update megafunction or the wysiwyg (what-you-see-is-what-you-get) atom into your design. without this atom or megafunction, you are not be able to access the dedicated remote configuration circuitry or registers wi thin the stratix or stratix gx device. see figure 12?10 for a symbol of the altremote_update megafunction. the local configuration mode, however, can be enabled with only the device configuration options compiler setting. 12?14 altera corporation stratix device handbook, volume 2 september 2004 quartus ii software support figure 12?10. altremote_update megafunction symbol altremote_update megafunction a remote update megafunction, altremote_update , is provided in the quartus ii software to provide a memory-like interface to allow for easy control of the remote update parameters. tables 12?6 and 12?7 describe the input and output ports available on the altremote_update megafunction. table 12?8 shows the param[2..0] bit settings. table 12?6. input ports of the altr emote_update megafunction (part 1 of 2) port name required source description clock y logic array clock input to the altremote_update block. all operations are performed with respects to the rising edge of this clock. reset y logic array asynchronous reset, which is used to initialize the remote update block. to ensure proper operation, the remote update block must be reset before first accessing the remote update block. this signal is not affected by the busy signal and will reset the remote update block even if busy is logic high. this means that if the reset signal is driven logic high during writing of a par ameter, the parameter will not be properly written to the remote update block. reconfig y logic array when driven logic high, reconfigur ation of the device is initiated using the current parameter settings in the remote update block. if busy is asserted, this signal is ignored. th is is to ensure all parameters are completely written before reconfiguration begins. reset_timer n logic array this signal is required if y ou are using the watchdog timer feature. a logic high resets the internal wa tchdog timer. this signal is not affected by the busy signal and can reset the timer even when the remote update block is busy. if this port is left connected, the default value is 0. altera corporation 12?15 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices read_param n logic array once read_param is sampled as a logic high, the busy signal is asserted. while the parameter is being read, the busy signal remains asserted, and inputs on param[] are ignored. once the busy signal is deactivated, the next parameter can be read. if this port is left unconnected, the default value is 0. write_param n logic array this signal is required if y ou intend on writing parameters to the remote update block. when driven lo gic high, the parameter specified on the param[] port should be written to the remote update block with the value on data_in[] . the number of valid bits on data_in[] is dependent on the parameter type. this signal is sampled on the rising edge of clock and should only be asserted for one clock cycle to prevent the parameter from being re-read on subsequent clock cycles. once write_param is sampled as a logic high, the busy signal is assert ed. while the parameter is being written, the busy signal remains asserted, and inputs on param[] and data_in[] are ignored. once the busy signal is deactivated, the next parameter can be written. this signal is only valid when the current_configuration parameter is factory since parameters cannot be written in application conf igurations. if this port is left unconnected, the default value is 0. param[2..0] n logic array 3-bit bus that selects which par ameter should be read or written. if this port is left unconnected, the default value is 0. data_in[11..0] n logic array this signal is required if y ou intend on writing parameters to the remote update block 12-bit bus used when writing parameters, which specifies the parameter value. the parameter value is requested using the param[] input and by driving the write_param signal logic high, at which point the busy signal goes logic high and the value of the parameter is captured from this bus. for some parameters, not all 12-bits will be used in which case only the least significant bits will be used. this port is ignored if the current_configuration parameter is set to an applicatio n configuration since writing of parameters is only allowed in the factory configuration. if this port is left unconnected, the default values is 0. note to ta b l e 1 2 ? 6 : (1) logic array source means that you can drive the port from internal logic or any general-purpose i/o pin. table 12?6. input ports of the altr emote_update megafunction (part 2 of 2) port name required source description 12?16 altera corporation stratix device handbook, volume 2 september 2004 quartus ii software support table 12?7. output ports of th e altremote_update megafunction port name required destination description busy y logic array when this signal is a logic high, the remote update block is busy either reading or writing a param eter. when the remote update block is busy, it ignores its data_in[] , param[] , and reconfig inputs. this signal will go high when read_param or write_param is asserted and will remain asserted until the operation is complete. pgm_out[2..0] y pgm[2..0] pins 3-bit bus that specifies the page poin ter of the configuration data to be loaded when the device is reconfigured. this port must be connected to the pgm[] output pins, which should be connected to the external configuration device data_out[11..0] n logic array 12-bit bus used when readi ng parameters, which reads out the parameter value. the parameter value is requested using the param[] input and by driving the read_param signal logic high, at which point the busy signal will go logic high. when the busy signal goes low, the value of the parameter will be driven out on this bus. the data_out[] port is only valid after a read_param has been issued and once the busy signal is de- asserted. at any other time, its output values are invalid. for example, even though the data_out[] port may toggle during a writing of a parameter, these values are not a valid representation of what was actually written to the remote update block. for some parameters, not all 12-bits will be used in which case only the least significant bits will be used. note to table 12?7 : (1) logic array destination means that you can drive the port to internal logic or any general-purpose i/o pin. table 12?8. parameter settings for the altremote_update megafun ction (part 1 of 2) selected parameter param[2..0] bit setting width of parameter value por reset value description status register contents 000 5 5 bit '0 specifies the reason for re-configuration, which could be caused by a crc error during configuration, nstatus being pulled low due to an error, the device core caused an error, nconfig pulled low, or the watchdog timer timed-out. this parameter can only be read. watchdog timeout value 010 12 12 bits '0 user watchdog timer time-out value. writing of this parameter is only allowed when in the factory configuration. watchdog enable 011 1 1 bit '0 user watchdog timer enable. writing of this parameter is only allowed when in the factory configuration altera corporation 12?17 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices remote update wysiwyg atom an alternative to using the altremote_update megafunction is to directly instantiate the remote upda te wysiwyg atom. this atom should be included in the factory configuration and any application configuration image to access the re mote configuration shift registers. when implementing the atom, yo u should consider following: 1. only one atom can be used in the circuit; more than one gives a no-fit. 2. all signals for the cell must be connected. the clock port ( clk ) must be connected to a live cell. the others can be constant v cc or gnd. 3. the pgmout port must be connected and must feed pgm[2.0] output pins (it cannot be connec ted to anything else but output pins). 4. the quartus ii software reserves runlu as an input pin, and you must connect it to v cc . page select 100 3 3 bit '001' - local configuration page mode selection. writing of this parameter is only allowed when in the factory configuration. 3 bit '000' - remote configuration current configuration (anf) 101 1 1 bit '0' - factory specifies whether the current configuration is factory or and application configuration. this parameter can only be read. 1 bit '1' - application illegal values 001 110 111 table 12?8. parameter settings for the altremote_update megafun ction (part 2 of 2) selected parameter param[2..0] bit setting width of parameter value por reset value description 12?18 altera corporation stratix device handbook, volume 2 september 2004 quartus ii software support the stratix and stratix gx remote update atom ports are: stratix_rublock < rublock_name > ( .clk( < clock source > ), .shiftnld( < shiftnld source > ), .captnupdt( < shiftnld source > ), .regin( < regin input source from the core> ) , .rsttimer ( ) , .config ( ) , .regout( < data output destination to core > ), .pgmout( < program output destinations to pins> ) table 12?9 shows the remote update block input and output port names and descriptions. table 12?9. remote update block input & output ports ports definition < rublock_name > the unique identifier for the instance. this identifier name can be anything as long as it is legal for the given description language (i.e., verilog, vhdl, ahdl, etc.). this field is required. .clk (< clock source >) designates the clock input of this cell. all operation is with respect to the rising edge of this clock. this field is required. .shiftnld (< shiftnld source >) an input into the remote configuration block. when . shiftnld = 1, the data shifts from the internal shift registers to the regout port at each rising edge of clk , and the data also shifts into the internal shift registers from regin port. this field is required. .captnupdt (< shiftnld source >) an input into the remote configuration bl ock. this controls the protocol of when to read the configuration mode or when to wr ite into the register s that control the configuration. this field is required. .regin ( altera corporation 12?19 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices f for more information on the control signals for the re mote block, see table 12?3 on page 12?9 . using enhanced configuration devices this section describes remote system configuration of stratix and stratix gx devices with the nios em bedded processor using enhanced configuration devices. e nhanced configuration de vices are composed of a standard flash memory and a cont roller. the flash memory stores configuration data, and the controller reads and writes to the flash memory. in remote system configuration, only ps and fpp modes are supported using an enhanced configuration device. a stratix or stratix gx device running a nios embedded processor can receive data from a remote source through a network or any oth er appropriate media. a specific page of the enhanced configuration device stores the received data. this scheme uses the page mode option in stratix and strati gx devices. up to eight pages can be stored in each enhanced configuration device, each of which can store a configuration file. in enhanced configuratio n devices, a page is a section of the flash memory space. its boundary is dete rmined by the quartus ii software (the page size is programmable). in the software, you can specify which configuration file should be stored in which page within the flash memory. to access the configuration fi le on each page, set the three input pins ( pgm[2..0] ), which provide access to all eight pages. because the pgm[2..0] pins of an enhanced config uration device connect to the same pins of the stratix or stratix gx device, the stratix or stratix gx device selects one of the eight memory pages as a target location to read from. figure 12?11 shows the allocation of different pages in the enhanced config uration device. f for more information on enhanced configuration devices, see the enhanced configuration devices (e pc4, epc8 & epc16) data sheet and the altera enhanced configuration devices chapter. 12?20 altera corporation stratix device handbook, volume 2 september 2004 using enhanced configuration devices figure 12?11. memory map in enhanced configuration device when the stratix or stratix gx device powers-up in remote configuration mode, the devices loads configuration data located at page address 000 . you should always load the factory default configuration data at this location and make sure this information is not altered. the factory configuration contains information to determine the next application configuration to load into the stratix or stratix gx device. when the stratix or stratix gx device successfully loads the application configuration from the page selected by the pgm[2..0] pins, it enters user mode. in user mode, the nios embedded pr ocessor (or any other logic) assists the stratix or stratix gx device in detecting remote system configuration information. in remote system configuration, the nios embedded processor receives the incoming data from the remote source via the network, writes it to the ecp16 enhanced configuration device, and then initiates loading of the factory config uration into the stratix or stratix gx device. factory configuration reads the remote configuration status register and determines the appropriate application configuration to load into the stratix or stratix gx device. figure 12?12 shows the remote system configuration. unused memory processor space enhanced configuration devices page7 configuration space page1 page0 option bits boot & parameter block altera corporation 12?21 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices figure 12?12. remote system configurati on using enhanced configuration devices the user watchdog timer in stratix an d stratix gx devices ensures that an application configuration has loaded successfully and checks if the application configuration is operating correctly in user mode. the watchdog timer must be continually re set by the user logic. if an error occurs while the application configuration loads, or if the watchdog timer times-out during user mode, the fa ctory configuration is reloaded to prevent the system from halting in an erroneous state. figure 12?3 on page 12?4 illustrates the remote configuration mode. upon power-up in local config uration scheme, the application configuration at page 001 ( pgm[001] of the enhanced configuration device) loads into the stratix or stratix gx device. this application can be remotely or locally updated. if an error occurs during loading of the configuration data, the factory conf iguration loads au tomatically (see figure 12?4 on page 12?5 ). the rest is identical to remote configuration mode. local update programming file generation this section describes the programmi ng file generation process for performing remote system upgrades. the quartus ii convert programming files (cpf) utility ge nerates the initial and partial programming files for configuration memory within the enhanced configuration devices. the two pages that local configur ation mode uses are a factory configuration stored at page 000, and an application configuration stored at page 001. the factory configuration cannot be updated after initial production programming. however, th e application conf iguration can be erased and reprogrammed after initial system deployment. remote source application configuration data (network) stratix or stratix gx device nios processor configuration control signals application/factory configuration data pgm[2..0] application configuration data enhanced configuration device application data 1 application data 7 factory data selecting next application from factory data watchdog circuitry 12?22 altera corporation stratix device handbook, volume 2 september 2004 using enhanced configuration devices in local update mode, you would first create the initial programming file with the factory configuration imag e and a version of the application configuration. subsequently, you can generate partial programming files to update the application configuration (stored in page 001). quartus ii cpf can create partial programming files in . hex (hexadecimal file), jam, .jbc (jam byte-code file), and pof formats. in addition to the two configuration pa ges, user data or processor code can also be pre-programmed in the bottom boot and main data areas of the enhanced configuration device memory. the cpf utility accepts a hex input file for the bottom and main data areas, and includes this data in the pof output file. however, this is only supported for initial programming file generation. partia l programming file generation for updating user hex data is not suppo rted, but can be performed using the enhanced configuration device external flash interface. initial programming file generation the initial programming file includes configuration data for both factory and application configuration pages. the enhanced configuration device option?s bits are always lo cated between byte addresses 0x00010000 and 0x0001003f . also, page 0 always starts at 0x00010040 while its end address is dependent on the size of the factory configuration data. the two memory allocation option s that exist for the application configuration are auto addressing and block addressing. in auto addressing mode, quartus ii automa tically allocates memory for the application configuration. all the configuration memory sectors that are not used by the page 0 factory configuration are allocated for page 1. the memory allocated is maximized to allow future versions of the application configuration to grow an d have bigger configuration files (when the compression feature is enabled). processor or user data storage (hex input file) is only supported by the bottom boot area in auto addressing mode. the following steps and screen shot (see figure 12?13 ) describe initial programming file generation with auto addressing mode. 1. open the convert progra mming files window from the file menu. 2. select programmer object file (*.pof) from the drop-down list titled programming file type . altera corporation 12?23 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices 3. select the enhanced configurat ion device used (epc4, epc8, epc16), and the mode used (1-bit passive serial or fast passive parallel). only during the initial programming file generation can you specify the options , configuration device , or mode settings. while generating the partial progra mming file, all of these settings are grayed out and inaccessible. 4. in the input files to convert box, highlight sof data at page 0 and click add file . select input sof file(s) for this configuration page and insert them. 5. repeat step 4 for the page 1 application configuration page. 6. check the memory map file box to generate a memory map output file that specifies the start/end addresses of each configuration page and user data blocks. 7. save the cpf setup (optionally), by selecting save conversion setup ? and specifying a name for the .cof output file. 8. click ok to generate initial programming and memory map files. 12?24 altera corporation stratix device handbook, volume 2 september 2004 using enhanced configuration devices figure 12?13. cpf setup for initial pr ogramming file (auto addressing) a sample memory map output file for the preceding setup is shown below. configuration opti on bits and page 0 da ta occupy main flash sectors 0 through 4. see the sharp lhf16j06 flash me mory used in epc16 devices data sheet at www.altera.com to correlate memory addresses to the epc16 flash sectors. in auto addr essing mode, page 1 allocates all unused flash sectors. for this example, this unused area includes main sectors 5 through 30, and all of the bo ttom boot sectors. while this large portion of memory is allocated for page 1, the real application configuration data is top justified within this region with filler 1'b1 bits in lower memory addresses. notice that the page 1 configuration data altera corporation 12?25 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices wraps around the top of the memory and fills up the bottom boot area. the wrap around does not occur if the bottom boot area is used for processor/user hex data file storage. the block addressing mode allows better control of flash memory allocation. you can allocate a specif ic flash memory region for each application configuration page. this allocation is done by specifying a block starting and block ending addres s. while selecting the size of the region, you should account for grow th in compressed configuration bitstream sizes due to design changes and additions. in local update mode, all configuration data is top ju stified within this allotted memory. in other words, the last byte of config uration data is stored such that it coincides with the highest byte address location within the allotted space. lower unused memory address locati ons within the allotted region are filled with 1's. these filler bits ar e transmitted during a configuration cycle using page 1, but are ignored by the stratix device. the memory map output file provides the exact byte address where real configuration data for page 1 begins. n ote that any partial update of page 1 should erase all allotted flash sectors before storing new configuration data. in the block addressing mode, hex in put files can be optionally added to the bottom boot and main flash data areas (one hex file per area is allowed). the hex file can be stored with relative addressing or absolute addressing. for more information on relative and absolute addressing, see the using altera enhanced configuration devices chapter of the configuration handbook . figures 12?14 and 12?15 , and the following steps illustrate generating an initial programming file with block addressing for local update mode. this example also illustr ates preloading user hex data into bottom boot and main flash sectors. 1. open the convert progra mming files window from the file menu. 2. select programmer object file (.pof) from the drop-down list titled programming file type . block start address end address option bits 0x00010000 0x0001003f page 0 0x00010040 0x00054cc8 page 1 0x001cb372 0x0000fffd wrapped around 12?26 altera corporation stratix device handbook, volume 2 september 2004 using enhanced configuration devices 3. select the enhanced configuration device (epc4, epc8, epc16), and the mode used (1-bit passive serial or fast passive parallel). only during the initial programming file generation can you specify the options , configuration device , or mode settings. while generating the partial programming file, all of these settings are grayed out and inaccessible. 4. in the input files to convert box, highlight sof data at page 0 and click add file . select input sof file(s) for this configuration page and insert them. 5. repeat step 4 for the page 1 application configuration page. 6. for enabling block addressing, select the sof data entry for page 1 , and click properties . this opens the sof data properties dialog box (see figure 12?15 ). 7. pick block from the address mode drop down selection, and enter 32-bit hexadecimal byte address for block starting address and ending address . note that for partial programming support, the block start and end addresses should be aligned to a flash sector boundary. this prevents two configuration pages from overlapping within the same flash boundary. s ee the flash memory datasheet for data sector boundary information. click ok to save sof data properties. 8. check the memory map file box to generate a memory map output file that specifies the start/end addresses of each configuration page and user data blocks. 9. save the cpf setup (optionally), by selecting save conversion setup ? and specifying a name for the cof output file. 10. click ok to generate initial programming and memory map files. altera corporation 12?27 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices figure 12?14. cpf setup for initial programm ing file generation (block addressing) 12?28 altera corporation stratix device handbook, volume 2 september 2004 using enhanced configuration devices figure 12?15. specifying bloc k addresses for applic ation configuration a sample memory map output file for the preceding example is shown below. note that the allocated memory for page 1 is between 0x00080000 and 0x001effff , while the actual re gion used by the current application configuration bitstream is between 0x001ab36c and 0x001efff7 . the configuration data is top justified within the allocated sof data region. also note that the hex data stored in the main data area uses absolute addressing. if relative addressing were to be used, the main data contents would be justified with the top (highe r address locations) of the memory. block start address end address bottom boot 0x00000000 0x000001ff option bits 0x00010000 0x0001003f page 0 0x00010040 0x00054cc8 page 1 0x001ab36c 0x001efff7 top boot/main 0x001f0000 0x001f01ff altera corporation 12?29 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices the initial programming file (pof) can be converted to an intel hexadecimal format file (*.hexout) using the quartus ii cpf utility. see figure 12?16 . figure 12?16. converting pof programmi ng file to intel hex format partial programming file generation the enhanced quartus ii cpf utility allows an existing application configuration page to be replaced with new data. partial programming files are generated to perform such configuration data updates. in order to generate a partial programming file, you have to input the initial programming file (pof) and new configuration data (sof) to the quartus ii cpf utility. in addition, you have to specify the addressing mode (auto or manual) that was used during initial pof creation. and if 12?30 altera corporation stratix device handbook, volume 2 september 2004 using enhanced configuration devices block addressing was used, you shou ld specify the block start and end addresses. with this information, quartus ii ensures that the partial programming file only updates th e flash region containing the application configuration. the fa ctory configuration (page 0) and configuration option bits are left unaltered during this process. figure 12?17 and the following steps illustr ate generation of a partial programming file: 1. open the convert progra mming files window from the file menu. 2. select programmer object file for local update (.pof) from the drop-down list titled programming file type , and specify an output file name . 3. in the input files to convert box , highlight pof data and click add file . select the initial programming pof file for this design and insert it. 4. in the input files to convert box , highlight sof data and click add file. select the new application configuration bitstream (sof) and insert it. 5. when using block addressing, select the sof data entry for page 1 , and click properties . this opens the sof data properties dialog box (see figure 12?18 ). 6. pick block from the address mode drop down selection, and enter 32-bit hexadecimal byte address for block starting address and ending address . these addresses should be identical to those used to generate the initial programming file. click ok to save sof data properties. 7. check the memory map file box to generate a memory map output file that specifies the start/end addresses of the new application configuration data in page 1. 8. pick a local update difference file from the remote/local update difference file drop-down menu. you can select between an intel hex, jam, jbc, and pof output file types. the output file name is the same as the pof output f ile name with a _dif suffix. 9. save the cpf setup (optionally), by selecting save conversion setup? and specifying a name for the cof output file. 10. click ok to generate initial programming and memory map files. altera corporation 12?31 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices figure 12?17. local update partial programming file generation 12?32 altera corporation stratix device handbook, volume 2 september 2004 using enhanced configuration devices figure 12?18. specifying bloc k addresses for applic ation configuration remote update progra mming file generation this section describes the programmi ng file generation process for performing remote system upgrad es. the quartus ii cpf utility generates the initial and partial programming files for configuration memory within the enhanced configuration devices. remote configuration mode uses a factory configuration stored at page 0, and up to seven application configurat ions stored at pages 1 through 7. the factory configuration cannot be updated after initial production programming. however, the most rece nt application configuration can be erased and reprogrammed after initial system deployment. alternatively, a new application configuration can be added provided adequate configuration memory availability. in remote update mode, you would first create the initial programming file with the factory configuration image and the application configuration(s). subsequently, you can generate partial programming files to update the most recent application configuration or add a new application configuration. quartus ii cpf can create partial programming files in hex, jam, jbc, and pof formats. in addition to the configuration pages, user data or processor code can also be pre-programmed in the bottom boot and main data areas of the enhanced configuration device memory. the cpf utility accepts a hex input file for the bottom and main data areas, and includes this data in the altera corporation 12?33 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices pof output file. however, this is only supported for initial programming file generation. partial programming file generation for updating user hex data is not supported, but can be performed using the enhanced configuration device external flash interface. initial programming file generation the initial programming file includes configuration data for both factory and application configuration pages. the enhanced configuration device option?s bits are always lo cated between byte addresses 0x00010000 and 0x0001003f . also, page 0 always starts at 0x00010040 while its end address is dependent on the size of the factory configuration data. two memory allocation op tions exist for application configurations: auto addressing and block addressing. in auto addressing mode, quartus ii packs all application configurations as close together as possible. this maximizes the number of application configurations that can be stored in memory. however, when auto addressing is used you cannot update existing application configurations. only new application configurations can be added to the memory. the following steps and screen shot (see figure 12?19 ) describe initial programming file generation with auto addressing mode. 1. open the convert progra mming files window from the file menu. 2. select programmer object file (*.pof) from the drop-down list titled programming file type . 3. select the enhanced configurat ion device used (epc4, epc8, epc16), and the mode used (1-bit passive serial or fast passive parallel). only during the initial programming file generation can you specify the options , configuration device , or mode settings. while generating the partial progra mming file, all of these settings are grayed out and inaccessible. 4. in the input files to convert box , highlight sof data at page 0 and click add file . select input sof file(s) for this configuration page and insert them. 5. repeat step 4 for all application configurations (up to 7 maximum). 6. check the memory map file box to generate a memory map output file that specifies the start/end addresses of each configuration page and user data blocks. 12?34 altera corporation stratix device handbook, volume 2 september 2004 using enhanced configuration devices 7. save the cpf setup (optionally), by selecting save conversion setup? and specifying a name for the cof output file. 8. click ok to generate initial programming and memory map files. figure 12?19. cpf setup for initial programm ing file generation (auto addressing) altera corporation 12?35 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices a sample memory map output file for the preceding setup is shown below. notice all configuration pages are packed such that two pages can share a flash data sector. this disallows partial programming of application configurations in auto addressing mode. f see the sharp lhf16j06 data sheet flash memory used in epc16 devices at www.altera.com to correlate memory addresses to the epc16 flash sectors. the block addressing mode allows better control of flash memory allocation. you can allocate a specif ic flash memory region for each application configuration page. this allocation is done by specifying a block starting and block ending addres s. while selecting the size of the region, you should account for grow th in compressed configuration bitstream sizes due to design changes and additions. in remote update mode, all configuration data is top ju stified within this allotted memory. in other words, the last byte of config uration data is stored such that it coincides with the highest byte address location within the allotted space. lower unused memory address locati ons within the allotted region are filled with 1's. these filler bits ar e transmitted during the application configuration cycle, but are ignored by the stratix device. the memory map output file provides the exact byte address where real application configuration data for each page begi ns. note that any partial update of the most recent application configur ation should erase all allotted flash sectors for that page before storing new configuration data. in the block addressing mode, hex in put files can be optionally added to the bottom boot and main flash data areas (one hex file per area is allowed). the hex file can be stored with relative addressing or absolute addressing. for more information on relative and absolute addressing, see the enhanced configuration devices (epc4, epc8 & epc16) data sheet chapter of the configuration handbook, volume 2 . figures 12?20 and 12?21 , and the following steps illustrate generating an initial programming file with block addressing for remote update mode. this example also illustr ates preloading user hex data into bottom boot and main flash sectors. 1. open the convert progra mming files window from the file menu. block start address end address option bits 0x00010000 0x0001003f page 0 0x00010040 0x00054efa page 1 0x00054efc 0x00099db6 page 2 0x00099db8 0x000dec72 12?36 altera corporation stratix device handbook, volume 2 september 2004 using enhanced configuration devices 2. select programmer object file (*.pof) from the drop-down list titled programming file type . 3. select the enhanced configurat ion device used (epc4, epc8, epc16), and the mode used (1-bit passive serial or fast passive parallel). only during the initial programming file generation can you specify the options , configuration device , or mode settings. while generating the partial progra mming file, all of these settings are grayed out and inaccessible. 4. in the input files to convert box, highlight sof data at page 0 and click add file . select input sof file(s) for this configuration page and insert them. 5. repeat step 4 for all the application configuration pages (pages 1 and 2 in this example). 6. for enabling block addressing, select the sof data entry for page 1 , and click properties . this opens the sof data properties dialog box (see figure 12?21 ). 7. pick block from the address mode drop down selection, and enter 32-bit hexadecimal byte address for block starting address and ending address . note that for partial programming support, the block start and end addresses should be aligned to a flash sector boundary. this prevents two configuration pages from overlapping within the same flash boundary. s ee the flash memory datasheet for data sector boundary information. click ok to save sof data properties. 8. check the memory map file box to generate a memory map output file that specifies the start/end addresses of each configuration page and user data blocks. 9. save the cpf setup (optionally), by selecting save conversion setup? and specifying a name for the cof output file. 10. click ok to generate initial programming and memory map files. altera corporation 12?37 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices figure 12?20. cpf setup for initial programm ing file generation (block addressing) 12?38 altera corporation stratix device handbook, volume 2 september 2004 using enhanced configuration devices figure 12?21. specifying block addresses for an application configuration a sample memory map output file for the preceding example is shown below. note that the allocated memory for page 1 is between 0x00070000 and 0x000bffff , while the actual re gion used by the current application configuration bitstream is between 0x0007b144 and 0x000bffff . the configuration data is top justified within the allocated sof data region. similarly, the allo cated memory for page 2 is between 0x000d0000 and 0x0012ffff , while the actual re gion used by the application configur ation is between 0x000eb13e and 0x0012fff9 . also note that the hex data stored in the main data area uses absolute addressing. if relative addressing were to be used, the main data contents would be justified with the top (highe r address locations) of the memory. the initial pof can be converted to an intel hexadecimal format file (*.hexout) using the quartus ii cpf utility. see figure 12?22 . block start address end address bottom boot 0x00000000 0x000001ff option bits 0x00010000 0x0001003f page 0 0x00010040 0x00054efa page 1 0x0007b144 0x000bffff page 2 0x000eb13e 0x0012fff9 top boot/main 0x001f0000 0x001f01ff altera corporation 12?39 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices figure 12?22. converting pof programmi ng file to intel hex format partial programming file generation in remote update mode, the quartus ii cpf utility allows an existing application configuration page to be replaced with new data, or a new application configuration to be added. partial programming files are generated to perform such configuration data updates. in order to generate a partial programming file, you have to input the initial pof and new configuration da ta (sof) to the quartus ii cpf utility. in addition, you have to specify the addressing mode (auto or manual) that was used during initial pof creation. and if block addressing was used, you should specify the block start and end 12?40 altera corporation stratix device handbook, volume 2 september 2004 using enhanced configuration devices addresses. with this information, qu artus ii ensures that the partial pof only updates the fl ash region containing the application configuration. the factory configuration (page 0) and configuration option bits are left unaltered during this process. th e only exception is when a new application configuration is added, the configuration options bits are updated to include start/end addresses for the new page. all existing page addresses and other configuration options bits remain unchanged. figure 12?23 and the following steps illustr ate generation of a partial programming file to replace the most recent application configuration. in this example, the initial programmin g file contained one factory and two application configurations. hence, the page 2 application configuration is being updated with new data. 1. open the convert progra mming files window from the file menu. 2. select programmer object file fo r remote update (*.pof) from the drop-down list titled programming file type , and specify an output file name. 3. in the input files to convert box, highlight pof data and click add file . select the initial programming pof file for this design and insert it. 4. in the input files to convert box , highlight sof data and click add file . select the new application configuration bitstream (sof) and insert it. 5. when using block addressing, select the sof data entry for page 2 , and click properties . this opens the sof data properties dialog box (see figure 12?24 on page 12?42 ). 6. pick block from the address mode drop down selection, and enter 32-bit hexadecimal byte address for block starting address and ending address . these addresses should be identical to those used to generate the initial programming file. click ok to save sof data properties. 7. check the memory map file box to generate a memory map output file that specifies the start/end addresses of the new application configuration data in page 1. 8. pick a remote update difference file from the remote/local update difference file drop-down menu. you can select between an intel hex, jam, jbc, and pof output file types. the output file name is the same as the pof output f ile name with a _dif suffix. altera corporation 12?41 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices 9. save the cpf setup (optionally), by selecting save conversion setup? and specifying a name for the cof output file. 10. click ok to generate initial programming and memory map files. figure 12?23. remote update partial programming file generation 12?42 altera corporation stratix device handbook, volume 2 september 2004 combining max devices & flash memory figure 12?24. specifying bloc k addresses for applic ation configuration for adding a new application configuration, follow the steps listed above with one modification. in step 5, select sof data and click on properties . in the sof data properties dialog box, select a new page (for example, page 3) and specify the addressing mode information. continue with steps 7 through 10. when a new page is added, the memory map output file lists the start/end addresses for this page. a sample is shown below: combining max devices & flash memory this section describes remote system configuration with the stratix or stratix gx device and the nios embe dded processor, using a combination of max ? devices and flash memory. you can use max 3000 or max 7000 devices and an industry-standard flash memory device instead of enhanced configuration devices. in this scheme, flash memory stores configuration data, and the max device controls reading and writing to th e flash memory, keeping track of address locations. the max device determines which address location and at what length to store configuration data in flash memory. the nios embedded processor, running in the stratix or stratix gx device, receives the block start address end address option bits 0x00010000 0x0001003f page 3 0x0012fffa 0x00174eb4 altera corporation 12?43 september 2004 stratix device handbook, volume 2 remote system configuration with stratix & stratix gx devices incoming data from the remote source and writes it to the address location in flash memory. the nios embedded processor initiates loading of factory configuration into the stratix or stratix gx device. figure 12?25 shows remote system configuration using a max device and flash memory combination. figure 12?25. remote system configurati on using a max device & flash memory you can use both remote and local configuration modes in this scheme. you should specify a default page for factory configuration and make sure it is not altered or removed at any time. in remote system configuration mode, ps, fpp, and ppa modes are supported when configuring with max and flash devices. using an external processor this section describes remote system configuration with stratix or stratix gx devices and the nios embedded processor, using an external processor and flash memory devices. in this scheme, the external proces sor and flash memory device replace the enhanced configuration device. flash memory stores configuration data, and the processor controls read ing and writing to the flash memory and also keeps track of the address lo cation. this type of remote system configuration supports ps, fpp, and ppa modes. the processor determines at which address which length to store the configuration data in flash memory. the nios embedded processor receives the incoming data from a remote source and writes it to the address location in the flash memory, and then initiates loading of factory remote source application configuration data stratix or stratix gx device max device max & flash memory nios processor application configuration data configuration control signals application/factory configuration data flash memory application data 1 application data 7 factory data selecting next application from factory data watchdog circuitry 12?44 altera corporation stratix device handbook, volume 2 september 2004 conclusion configuration data into the stratix or stratix gx device. figure 12?26 shows the remote system configuration using a nios embedded processor and flash memory. you can use both remote and local configuration modes in this scheme. you should specify a default page for factory configuration and make sure it is not altered or removed at any time. figure 12?26. remote system configuration us ing external processor & flash memory conclusion stratix and stratix gx devices are the first plds with dedicated support for remote system configuration. by allowing real-time system upgrades from a remote source, you can use stratix and stratix gx devices in a variety of applications that require automatic configuration updates. with the built-in watchdog timer circuitry, stratix and stratix gx devices avoid incorrect or erroneous states. using stratix and stratix gx devices with remote system configuration enhances design flexibility and reduces time to market. remote source application configuration data stratix or stratix gx device external processor external processor & flash memory nios processor application configuration data configuration control signals application/factory configuration data flash memory application data 1 application data 7 factory data selecting next application from factory data watchdog circuitry altera corporation section vii?1 section vii. pcb layout guidelines this section provides informatio n for board layout designers to successfully layout their boards for stratix ? devices. this section contains the required pcb layout guidelines and package specifications. this section contains the following chapters: chapter 13, package information for stratix devices chapter 14, designing with 1.5-v devices revision history the table below shows th e revision history for chapters 13 and 14 . chapter date/version changes made 13 july 2005, v3.0 updated packaging information. september 2004, v2.1 changed from chapter 8, volume 3 to chapter 13, volume 2. corrected spelling error. april 2003, v1.0 no new changes in stratix device handbook v2.0. 14 january 2005, v1.2 this chapter was formerly chapter 15. september 2004, v1.1 changed from chapter 10, volume 3 to chapter 15, volume 2. corrected spelling error. april 2003, v1.0 no new changes in stratix device handbook v2.0. section vii?2 altera corporation pcb layout guidelines stratix device handbook, volume 2 altera corporation 13?1 july 2005 13. package information for stratix devices introduction this data sheet provides package information for altera ? devices. it includes these sections: section page device & package cross reference . . . . . . . . . . . . . . . . . . . . . 13?1 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13?2 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13?3 in this data sheet, packages are li sted in order of ascending pin count. device & package cross reference table 13?1 shows which altera stratix ? devices are avai lable in bga, fineline bga and ultra fineline bga packages. table 13?1. stratix devices in bga, fineline bga & ultra fineline bga packages (part 1 of 2) device package pins ep1s10 flip-chip fineline bga 484 bga 672 fineline bga 672 flip-chip fineline bga 780 ep1s20 flip-chip fineline bga 484 bga 672 fineline bga 672 flip-chip fineline bga 780 ep1s25 bga 672 fineline bga 672 flip-chip fineline bga 780 flip-chip fineline bga 1,020 ep1s30 flip-chip fineline bga 780 flip-chip bga 956 flip-chip fineline bga 1,020 s53008-3.0 13?2 altera corporation stratix device handbook, volume 2 july 2005 thermal resistance thermal resistance table 13?2 provides ja (junction-to-ambient thermal resistance) and jc (junction-to-case thermal resistance) values for altera stratix devices. ep1s40 flip-chip fineline bga 780 flip-chip bga 956 flip-chip fineline bga 1,020 flip-chip fineline bga 1,508 ep1s60 flip-chip bga 956 flip-chip fineline bga 1,020 flip-chip fineline bga 1,508 ep1s80 flip-chip bga 956 flip-chip fineline bga 1,020 flip-chip fineline bga 1,508 table 13?1. stratix devices in bga, fineline bga & ultra fineline bga packages (part 2 of 2) device package pins table 13?2. thermal resistance of stratix devices (part 1 of 2) device pin count package jc ( c/w) ja ( c/w) still air ja ( c/w) 100 ft./min. ja ( c/w) 200 ft./min. ja ( c/w) 400 ft./min. ep1s10 484 fineline bga 0.38 11.9 9.8 8.4 7.2 672 bga 3.2 16.8 13.7 11.9 10.5 672 fineline bga 3.4 17.2 14 12.2 10.8 780 fineline bga 0.43 10.9 8.8 7.4 6.3 ep1s20 484 fineline bga 0.30 11.8 9.7 8.3 7.1 672 bga 2.5 15.5 12.4 10.7 9.3 672 fineline bga 2.7 16 12.8 11 9.6 780 fineline bga 0.31 10.7 8.6 7.2 6.1 altera corporation 13?3 july 2005 stratix device handbook, volume 2 package information for stratix devices package outlines the package outlines on the follow ing pages are listed in order of ascending pin count. altera package outlines meet the requirements of jedec publication no. 95. ep1s25 672 bga 2.2 14.8 11.7 10.0 8.7 672 fineline bga 2.3 15.3 12 10.4 9 780 fineline bga 0.25 10.5 8.5 7.1 6.0 1020 fineline bga 0.25 10.0 8.0 6.6 5.5 ep1s30 780 fineline bga 0.2 10.4 8.4 7.0 5.9 956 bga 0.2 9.1 7.1 5.8 4.8 1020 fineline bga 0.2 9.9 7.9 6.5 5.4 ep1s40 780 fineline bga 0.17 10.4 8.3 6.9 5.8 956 bga 0.18 9.0 7.0 5.7 4.7 1020 fineline bga 0.17 9.8 7.8 6.4 5.3 1508 fineline bga 0.18 9.1 7.1 5.8 4.7 ep1s60 956 bga 0.13 8.9 6.9 5.6 4.6 1020 fineline bga 0.13 9.7 7.7 6.3 5.2 1508 fineline bga 0.13 8.9 7.0 5.6 4.6 ep1s80 956 bga 0.1 8.8 6.8 5.5 4.5 1020 fineline bga 0.1 9.6 7.6 6.2 5.1 1508 fineline bga 0.1 8.8 6.9 5.5 4.5 table 13?2. thermal resistance of stratix devices (part 2 of 2) device pin count package jc ( c/w) ja ( c/w) still air ja ( c/w) 100 ft./min. ja ( c/w) 200 ft./min. ja ( c/w) 400 ft./min. 13?4 altera corporation stratix device handbook, volume 2 july 2005 package outlines 484-pin fineline bga - flip chip all dimensions and tolerances conform to asme y14.5m ? 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on the package surface. tables 13?3 and 13?4 show the package information and package outline figure references, respectively, fo r the 484-pin fineline bga packaging. table 13?3. 484-pin fineline bga package information description specification ordering code reference f package acronym fineline bga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aaj-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 5.8 g moisture sensitivity level p rinted on moisture barrier bag table 13?4. 484-pin fineline bga package outline dimensions symbol millimeter min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 23.00 bsc e 23.00 bsc b 0.50 0.60 0.70 e 1.00 bsc altera corporation 13?5 july 2005 stratix device handbook, volume 2 package information for stratix devices figure 13?1 shows a package outline for the 484-pin fineline bga packaging. figure 13?1. 484-pin fineline bga package outline d a1 a3 a2 a e e e b pin a1 id pin a1 corner bottom view top view 13?6 altera corporation stratix device handbook, volume 2 july 2005 package outlines 672-pin fineline bga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 13?5 and 13?6 show the package information and package outline figure references, respectively, fo r the 672-pin fineline bga packaging. table 13?5. 672-pin fineline bga package information description specification ordering code reference f package acronym fineline bga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aal-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 7.7 g moisture sensitivity level printed on moisture barrier bag table 13?6. 672-pin fineline bga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 27.00 bsc e 27.00 bsc b 0.50 0.60 0.70 e 1.00 bsc altera corporation 13?7 july 2005 stratix device handbook, volume 2 package information for stratix devices figure 13?2 shows a package outline for the 672-pin fineline bga packaging. figure 13?2. 672-pin fineline bga package outline e d e e a1 a2 b a3 a pin a1 id pin a1 corner bottom view top view 13?8 altera corporation stratix device handbook, volume 2 july 2005 package outlines 780-pin fineline bga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 13?7 and 13?8 show the package information and package outline figure references, respectively, fo r the 780-pin fineline bga packaging. table 13?7. 780-pin fineline bga package information description specification ordering code reference f package acronym fineline bga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aam-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 8.9 g moisture sensitivity level printed on moisture barrier bag table 13?8. 780-pin fineline bga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 29.00 bsc e 29.00 bsc b 0.50 0.60 0.70 e 1.00 bsc altera corporation 13?9 july 2005 stratix device handbook, volume 2 package information for stratix devices figure 13?3 shows a package outline for the 780-pin fineline bga packaging. figure 13?3. 780-pin fineline bga package outline pin a1 id pin a1 corner bottom view top view e d e e a1 a2 b a3 a 13?10 altera corporation stratix device handbook, volume 2 july 2005 package outlines 956-pin ball grid array (bga) - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 13?9 and 13?10 show the package information and package outline figure references, respecti vely, for the 956-pin bga packaging. table 13?9. 956-pin bga package information description specification ordering code reference b package acronym bga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: bau-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 14.6 g moisture sensitivity level printed on moisture barrier bag table 13?10. 956-pin bga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 40.00 bsc e 40.00 bsc b 0.60 0.75 0.90 e 1.27 bsc altera corporation 13?11 july 2005 stratix device handbook, volume 2 package information for stratix devices figure 13?4 shows a package outline fo r the 956-pin bga packaging. figure 13?4. 956-pin bga package outline d e b e a3 a1 a2 pin a1 corner a 16 24 31 29 27 25 28 30 26 23 21 19 17 20 22 18 ag ak al ah aj ad af ae ab ac y aa w t v u 8 15 13 11 9 12 14 10 7531 4 62 k n p r m l g h j f e b d c a e pin a1 id bottom view top view 13?12 altera corporation stratix device handbook, volume 2 july 2005 package outlines 1,020-pin fineline bga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 13?11 and 13?12 show the package information and package outline figure references, respecti vely, for the 1,020-pin fineline bga packaging. table 13?11. 1,020 fineline bga package information description specification ordering code reference f package acronym fineline bga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aap-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 11.5 g moisture sensitivity level printed on moisture barrier bag table 13?12. 1,020-pin fineline bga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 33.00 bsc e 33.00 bsc b 0.50 0.60 0.70 e 1.00 bsc altera corporation 13?13 july 2005 stratix device handbook, volume 2 package information for stratix devices figure 13?5 shows a package outline fo r the 1,020-pin fineline bga packaging. figure 13?5. 1,020-pin fineline bga package outline d e pin a1 id b e e a3 a1 a2 pin a1 corner a bottom view top view 13?14 altera corporation stratix device handbook, volume 2 july 2005 package outlines 1,508-pin fineline bga - flip chip all dimensions and tolerances conform to asme y14.5m - 1994. controlling dimension is in millimeters. pin a1 may be indicated by an id dot, or a special feature, in its proximity on package surface. tables 13?13 and 13?14 show the package information and package outline figure references, respecti vely, for the 1,508-pin fineline bga packaging. table 13?13. 1,508-pin fineline bga package information description specification ordering code reference f package acronym fineline bga substrate material bt solder ball composition regular: 63sn:37pb (typ.) pb-free: sn:3ag:0.5cu (typ.) jedec outline reference ms-034 variation: aau-1 maximum lead coplanarity 0.008 inches (0.20 mm) weight 14.6 g moisture sensitivity level printed on moisture barrier bag table 13?14. 1,508-pin fineline bga package outline dimensions symbol millimeters min. nom. max. a??3.50 a1 0.30 ? ? a2 0.25 ? 3.00 a3 ? ? 2.50 d 40.00 bsc e 40.00 bsc b 0.50 0.60 0.70 e 1.00 bsc altera corporation 13?15 july 2005 stratix device handbook, volume 2 package information for stratix devices figure 13?6 shows a package outline fo r the 1,508-pin fineline bga packaging. figure 13?6. 1,508-pin fineline bga package outline pin a1 corner b e e d pin a1 id a2 a3 a1 a e top view bottom view 13?16 altera corporation stratix device handbook, volume 2 july 2005 package outlines altera corporation 14?1 january 2005 14. designing with 1.5-v devices introduction the cyclone tm fpga family provides the be st solution for high-volume, cost-sensitive applications. stratix ? and cyclone devices are fabricated on a leading-edge 1.5-v, 0.13-m, all-layer copper sram process. using a 1.5-v operating voltage pr ovides the following advantages: lower power consumption compared to 2.5-v or 3.3-v devices. lower operating temperature. less need for fans and other temperature-control elements. since many existing designs are base d on 5.0-v, 3.3-v and 2.5-v power supplies, a voltage regulator may be required to lower the voltage supply level to 1.5-v. this document provides guidelines for designing with stratix and cyclone devices in mixed-voltage and single-voltage systems and provides examples using voltage regulators. this document also includes information on: power sequencing & hot socketing using multivolt i/o pins voltage regulators 1.5-v regulator application examples board layout power sequencing & hot socketing because 1.5-v cyclone fpgas can be used in a mixed-voltage environment, they have been design ed specifically to tolerate any possible power-up sequence. therefore, the v ccio and v ccint power supplies may be powered in any order. you can drive signals into cyclone fpgas before and during power up without damaging the device. in ad dition, cyclone fpgas do not drive out during power up since they are tr i-stated during power up. once the device reaches operating conditions and is configured, cyclone fpgas operate as specified by the user. f see the stratix fpga family data sheet and the cyclone fpga family data sheet for more information. c51012-1.1 14?2 altera corporation stratix device handbook, volume 2 january 2005 using multivolt i/o pins using multivolt i/o pins cyclone fpgas require a 1.5-v v ccint and a 3.3-v, 2.5-v, 1.8-v, or 1.5-v i/o supply voltage level (v ccio ). all pins, including dedicated inputs, clock, i/o, and jtag pins, are 3.3-v tolerant before and after v ccint and v ccio are powered. when v ccio is connected to 1.5-v, the outp ut is compatible with 1.5-v logic levels. the output pins can be ma de 1.8-v, 2.5-v, or 3.3-v compatible by using open-drain outputs pulled up with external resistors. you can use external resistors to pu ll open-drain outputs up with a 1.8-v, 2.5-v, or 3.3-v v ccio . table 14?1 summarizes cyclone multivolt i/o support. table 14?1. cyclone mul tivolt i/o support note (1) v ccio (v) input signal output signal 1.5-v 1.8-v 2.5-v 3.3-v 5.0-v 1.5-v 1.8-v 2.5-v 3.3-v 5.0-v 1.5-v vv v (2) v (2) v 1.8-v vvv v (3) v 2.5-v vv v (5) v (5) v 3.3-v v (4) v v (6) v (7) v (7) v (7) v v (8) notes to table 14?1 : (1) the pci clamping diode must be disabled to drive an input with voltages higher than v ccio . (2) when v ccio = 1.5-v and a 2.5-v or 3.3-v input signal feeds an input pin, higher pin leakage current is expected. (3) when v ccio = 1.8-v, a cyclone device can drive a 1.5-v device with 1.8-v tolerant inputs. (4) when v ccio = 3.3-v and a 2.5-v input signal feeds an input pin, the v ccio supply current will be slightly larger than expected. (5) when v ccio = 2.5-v, a cyclone device can drive a 1.5-v or 1.8-v device with 2.5-v tolerant inputs. (6) cyclone devices can be 5.0-v tolerant with the use of an external resistor and the internal pci clamp diode. (7) when v ccio = 3.3-v, a cyclone device can drive a 1.5-v, 1.8-v, or 2.5-v device with 3.3-v tolerant inputs. (8) when v ccio = 3.3-v, a cyclone device can drive a device with 5.0-v lvttl inputs but not 5.0-v lvcmos inputs. altera corporation 14?3 january 2005 stratix device handbook, volume 2 designing with 1.5-v devices figure 14?1 shows how cyclone fpgas interface with 3.3- -v and 2.5-v devices while operating with a 1.5-v v ccint to increase performance and save power. figure 14?1. cyclone fpgas interface with 3.3-v & 2.5-v devices voltage regulators this section explains how to generate a 1.5-v supply from another system supply. supplying power to the 1.5- v logic array and/or i/o pins requires a 5.0-v- or 3.3-v-to-1.5-v vo ltage regulator. a linear regulator is ideal for low-power applications because it minimizes device count and has acceptable efficiency for most applications. a switching voltage regulator provides optimal efficiency . switching regulators are ideal for high-power applications because of their high efficiency. this section will help you decide which regulator to use in your system, and how to implement the regulator in your design. there are several companies that provide vo ltage regulators for low-voltage devices, such as linear technology corporation, maxim integrated pr oducts, intersil corporation (elantec), and nati onal semiconductor corporation. 3.3 v 2.5 v 1.5 v 3.3-v ttl 3.3-v cmos 3.3-v device 2.5-v device cyclone device 2.5-v ttl 2.5-v cmos v ccint = 1.5 v v ccio1 = 2.5 v v ccio2 = 3.3 v 14?4 altera corporation stratix device handbook, volume 2 january 2005 voltage regulators table 14?2 shows the terminology and specifications commonly encountered with voltage regulators. symbols are shown in parentheses. if the symbols are different for linear and switching regulators, the linear regulator symbol is listed first. table 14?2. voltage regulator specifica tions & terminology (part 1 of 2) specification/ter minology description input voltage range (v in ,v cc ) minimum and maximum input voltages define the input voltage range, which is determined by the regulator process voltage capabilities. line regulation (line regulation, v out ) line regulation is the variation of the output voltage (v out ) with changes in the input voltage (v in ). error amplifier gain, pass transistor gain, and output impedance all influence line regulati on. higher gain results in better regulation. board layout and regulato r pin-outs are also important because stray resistance can introduce errors. load regulation (load regulation, v out ) load regulation is a variation in the output voltage caused by changes in the input supply current. linear technology regulators are designed to minimize load regulation, which is affected by erro r amplifier gain, pass transistor gain, and output impedance. output voltage selection output voltage selection is adjustable by resistor voltage divider networks, connected to the error amplifier input, t hat control the output voltage. there are multiple output regulators that cr eate 5.0-, 3.3-, 2.5-, 1.8- and 1.5-v supplies. quiescent current quiescent current is the suppl y current during no-load or quiescent state. this current is sometimes used as a general term for a supply current used by the regulator. dropout voltage dropout voltage is the difference between the input and output voltages when the input is low enough to cause the output to drop out of regulation. the dropout voltage should be as low as possible for better efficiency. current limiting voltage regulators are designed to limit the amount of output current in the event of a failing load. a short in the load causes the output current and voltage to decrease. this event cuts po wer dissipation in the regulator during a short circuit. thermal overload protection this feature limits power dissipation if the r egulator overheats. when a specified temperature is reached, t he regulator turns off the output drive transistors, allowing the regulator to cool. normal operation resumes once the regulator reaches a normal operating temperature. reverse current protection if the input power supply fa ils, large output capacitor s can cause a substantial reverse current to flow backward th rough the regulator, potentially causing damage. to prevent damage, protection di odes in the regulator create a path for the current to flow from v out to v in . stability the dominant pole placed by the output capacitor influences stability. voltage regulator vendors can assist yo u in output capacitor selection for regulator designs that diff er from what is offered. altera corporation 14?5 january 2005 stratix device handbook, volume 2 designing with 1.5-v devices linear voltage regulators linear voltage regulators generate a regulated output from a larger input voltage using current pass elements in a linear mode. there are two types of linear regulators available: one us ing a series pass element and another using a shunt element (e.g., a zener diode). altera recommends using series linear regulators because shunt regulators are less efficient. series linear regulators use a series pa ss element (i.e., a bipolar transistor or mosfet) controlled by a f eedback error amplifier (see figure 14?2 ) to regulate the output voltage by co mparing the output to a reference voltage. the error amplifier drives the transistor further on or off continuously to control the flow of current needed to sustain a steady voltage level across the load. figure 14?2. series linear regulator minimum load requirements a minimum load from the voltage divider network is required for good regulation, which also serves as the ground for the regulator?s current path. efficiency efficiency is the division of the output power by the input power. each regulator model has a specific effici ency value. the higher the efficiency value, the better the regulator. table 14?2. voltage regulator specifica tions & terminology (part 2 of 2) specification/ter minology description ? + reference error amplifier v out v in 14?6 altera corporation stratix device handbook, volume 2 january 2005 voltage regulators table 14?3 shows the advantages and disadvantages of linear regulators compared to switching regulators. you can minimize the difference betw een the input and output voltages to improve the efficiency of linear regulators. the dropout voltage is the minimum allowable difference between the regulator?s input and output voltage. linear regulators are available with fixed, variable, single, or multiple outputs. multiple-output regulators can generate multiple outputs (e.g., 1.5- and 3.3-v outputs). if the bo ard only has a 5.0-v power voltage supply, you should use multiple-output regulators. the logic array requires a 1.5-v power supply, and a 3.3-v power supply is required to interface with 3.3- and 5.0-v devices. however, fixed-output regulators have fewer supporting components, reducing board space and cost. figure 14?3 shows an example of a three-terminal, fixed-output linear regulator. figure 14?3. three-terminal, fix ed-output linear regulator adjustable-output regulators contain a voltage divider network that controls the regulator?s output. figure 14?4 shows how you can also use a three-terminal linear regulator in an adjustable-output configuration. table 14?3. linear regulator advantages & disadvantages advantages disadvantages requires few supporting components low cost requires less board space quick transient response better noise and drift characteristics no electromagnetic interference (emi) radiation from the switching components tighter regulation less efficient (typically 60 % ) higher power dissipation larger heat sink requirements linear regulator in out adj 1.5 v v in altera corporation 14?7 january 2005 stratix device handbook, volume 2 designing with 1.5-v devices figure 14?4. adjustable-ou tput linear regulator switching voltage regulators step-down switching regulators can provide 3.3-v-to-1.5-v conversion with up to 95 % efficiencies. this high efficiency comes from minimizing quiescent current, using a low-resist ance power mosfet switch, and, in higher-current applications, using a synchronous switch to reduce diode losses. switching regulators supply power by pulsing the output voltage and current to the load. table 14?4 shows the advantages and disadvantages of switching regulators compared to linear regulators. for more information on switching regulators, see application note 35: step down switching regulators from linear technology. there are two types of switching regulators, asynchronous and synchronous. asynchronous switching regulators have one field effect transistor (fet) and a diode to provide the current path while the fet is off (see figure 14?5 ). linear regulator in out adj v in + c 1 + v ref r 1 r 2 c 2 i adj v out = [v ref (1 + )] + (i adj r 1 ) r 1 r 2 table 14?4. switching regulator advantages & disadvantages advantages disadvantages highly efficient (typically >80 % ) reduced power dissipation smaller heat sink requirements wider input voltage range high power density generates emi complex to design requires 15 or more supporting components higher cost requires more board space 14?8 altera corporation stratix device handbook, volume 2 january 2005 voltage regulators figure 14?5. asynchronous switching regulator synchronous switching regulators have a voltage- or current-controlled oscillator that controls the on and off time of the two mosfet devices that supply the curren t to the circuit (see figure 14?6 ). figure 14?6. voltage-controlled sy nchronous switching regulator maximum output current select an external mosfet switching transistor (optional) based on the maximum output current that it ca n supply. use a mosfet with a low on-resistance and a voltage rating high enough to avoid avalanche breakdown. for gate-drive voltages less than 9-v, use a logic-level mosfet. a logic-level mosfet is only required for topologies with a controller ic and an external mosfet. high-frequency circulating path load switch node m osfet v out v in v in v out voltage-controlled oscillator (vco) altera corporation 14?9 january 2005 stratix device handbook, volume 2 designing with 1.5-v devices selecting voltage regulators your design requirements determine which voltage regulator you need. the key to selecting a voltage regula tor is understanding the regulator parameters and how they relate to the design. the following checklist can help you select the proper regulator for your design: do you require a 3.3-v, 2.5-v, and 1.5-v output (v out )? what precision is required on th e regulated 1.5-v supplies (line and load regulation)? what supply voltages (v in or v cc ) are available on the board? what voltage variance (input vo ltage range) is expected on v in or v cc ? what is the maximum i cc (i out ) required by your altera ? device? what is the maximum current surge (i out(max) ) that the regulator will need to suppl y instantaneously? choose a regulator type if required, select either a line ar, asynchronous switching, or synchronous switching regulator based on your output current, regulator efficiency, cost, and board-space re quirements. dc-to-dc converters have output current capabilities from 1 to 8 a. you can use a controller with an external mosfet rated for higher current for higher-output- current applications. calculate the maximum input current use the following equation to estima te the maximum input current based on the output power requirements at the maximum input voltage: where is nominal efficiency: typically 90 % for switching regulators, 60 % for linear 2.5-v-to- 1.5-v conversion, 45 % for linear 3.3-v-to-1.5-v conversion, and 30 % for linear 5.0-v- to-1.5-v conversion. once you identify the design requir ements, select the voltage regulator that is best for your design. tables 14?5 and 14?6 list a few linear technology and elantec regulators avai lable at the time this document i in,dc(max) = v out i out(max) v in(max) 14?10 altera corporation stratix device handbook, volume 2 january 2005 voltage regulators was published. there may be more regulators to choose from depending on your design specification. contact a regulator manufacturer for availability. voltage divider network design a voltage divider network if you are using an adjustable output regulator. follow the controller or co nverter ic?s instructions to adjust the output voltage. 1.5-v regulator circuits this section contains the circuit diagrams for the voltage regulators discussed in this chapter. you can use the voltage regulators in this section to generate a 1.5-v power supply. see the voltage regulator data sheet to find detailed specifications. if you require further information that is not shown in the data shee t, contact the regulator?s vendor. table 14?5. linear technology 1.5-v output voltage regulators voltage regulator regulator type total number of components v in (v) i out (a) special features lt1573 linear 10 2.5 or 3.3 (1) 6? lt1083 linear 5 5.0 7.5 ? lt1084 linear 5 5.0 5 ? lt1085 linear 5 5.0 3 inexpensive solution ltc1649 switching 22 3.3 15 selectable output ltc1775 switching 17 5.0 5 ? note to table 14?5 : (1) a 3.3-v v in requires a 3.3-v supply to the regulator?s input and 2.5-v supply to bias the transistors. table 14?6. elantec 1.5-v output voltage regulators voltage regulator regulator type total number of components v in (v) i out (a) special features el7551c switching 11 5.0 1 ? el7564cm switching 13 5.0 4 ? el7556bc switching 21 5.0 6 ? el7562cm switching 17 3.3 or 5.5 2 ? el7563cm switching 19 3.3 4 ? altera corporation 14?11 january 2005 stratix device handbook, volume 2 designing with 1.5-v devices figures 14?7 through 14?12 show the circuit diagrams of linear technology voltage regulators listed in table 14?5 . the lt1573 linear voltage regulator co nverts 2.5-v to 1.5-v with an output current of 6a (see figure 14?7 ). figure 14?7. lt1573: 2.5-v-to-1.5-v /6.0-a linear voltage regulator notes to figure 14?7 : (1) c in1 and c out are avx 100- f/10-v surface-mount tantalum capacitors. (2) use shdn (active high) to shut down the regulator. (3) c time is a 0.5- f capacitor for 100-ms time out at room temperature. (4) c in2 is an avx 15- f/10-v surface-mount tantalum capacitor. use adjustable 5.0- to 1.5-v regulators (shown in figures 14?8 through 14?10 ) for 3.0- to 7.5-a low-cost, low-device-count, board-space-efficient solutions. lt1573 fb latch shdn (2) gnd comp v out v in drive load v out r2 1k 1/8 w r1 186 1/8 w c time 0.5 f c out c in1 motorola d45h11 + + v 3.3 v in2 v 2.5 v 1.5 v in1 c in2 + r 6 1/2 w d r 200 1/8 w b + (1) (4) (3) (1) 14?12 altera corporation stratix device handbook, volume 2 january 2005 voltage regulators figure 14?8. lt1083: 5.0-v-to-1.5-v/7 .5-a linear voltage regulator note to figure 14?8 : (1) this capacitor is necessary to maintain the voltage level at the input regulator. there could be a voltage drop at the inpu t if the voltage supply is too far away. figure 14?9. lt1084: 5.0-v-to-1.5-v/5 .0-a linear voltage regulator note to figure 14?9 : (1) this capacitor is necessary to maintain the voltage level at the input regulator. there could be a voltage drop at the inpu t if the voltage supply is too far away. lt1083 adj out in c 1 v in + c 2 + r1 5 k r2 1 k 10 f 10 f (1) v out = 1.25 v (1 + ) r 2 r 1 lt1083 adj out in c 1 v in + c 2 + r1 5 k r2 1 k 10 f 10 f (1) v out = 1.25 v (1 + ) r 2 r 1 altera corporation 14?13 january 2005 stratix device handbook, volume 2 designing with 1.5-v devices figure 14?10. lt1085: 5.0-v-to-1.5-v /3-a linear voltage regulator note to figure 14?10 : (1) this capacitor is necessary to maintain the voltage level at the input regulator. there could be a voltage drop at the inpu t if the voltage supply is too far away. figure 14?11 shows a high-efficiency switch ing regulator circuit diagram. a selectable resistor network controls the output voltage. the resistor values in figure 14?11 are selected for 1.5-v output operation. figure 14?11. lt1649: 3.3-v-to-1.5-v/15- a asynchronous switching regulator notes to figure 14?11 : (1) mbr0530 is a motorola device. (2) irf7801 is a internat ional rectifier device. (3) see the panasonic 12ts-1r2hl device. lt1084 adj out in c 1 v in + c 2 + r1 5 k r2 1 k 10 f 10 f (1) v out = 1.25 v (1 + ) r 2 r 1 p vcc1 p vcc2 v cc i max shdn comp ss gnd g1 i fb g2 fb v in c + c ? cp out ltc1649 + + + + 0.33 f 10 f 1 f 1 f 1 k mbr0530 0.1 f 10 f 22 k r imax 50 k r 1 2.16 k r 2 12.7 k c out 4,400 f v out 1.5 v (15 a) shutdown mbr0530 (1) q3 irf7801 r c 7. 5 k c c 0 . 0 1 f c 1 22 0 pf q1, q2 irf7801 two in parallel (2) c in 3,300 f v in 3.3 v l ext (3) 1.2 h 14?14 altera corporation stratix device handbook, volume 2 january 2005 voltage regulators figure 14?12 shows synchronous switching regulator with adjustable outputs. figure 14?12. ltc1775: 5.0-v-to-1.5-v/5 -a synchronous sw itching regulator notes to figure 14?12 : (1) this is a kemett495x156m035as capacitor. (2) this is a sumida cdrh127-6r1 inductor. (3) this is a kemett510x687k004as capacitor. extv cc i th v osense v prog sgnd sync run/ss fcb v in boost bg pgnd intv cc tk sw tg c c2 220 pf c c1 2.2 nf intv cc open m1 1/2 fds8936a m2 1/2 fds8936a d b cmdsh-3 v in 5 v v out 1.5 v 5 a r f 1 r c 10 k r 2 2.6 k r 1 10 k c in (1) 15 f 35 v 3 c out (3 ) 680 f 4 v 2 c b 0.22 f c vcc 4.7 f c ss 0.1 f c f 0.1 f l 1 (2) 6.1 h d1 mbrs140 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 altera corporation 14?15 january 2005 stratix device handbook, volume 2 designing with 1.5-v devices figures 14?13 through 14?17 show the circuit diagrams of elantec voltage regulators listed in table 14?6 . figures 14?13 through 14?15 show the switching regulator that converts 5.0-v to 1.5-v with di fferent output current. figure 14?13. el7551c: 5.0-v-to-1.5-v/1-a synchronous switching regulator c 5 0.1 f c 6 0.1 f c 3 0.1 f c 1 10 f ceramic c 4 270 pf c 7 47 f v 0 1.5 v 1 a v in 5.0 v l 1 10 h r 2 539 r 3 39 k r 1 1 k pgnd pgnd fb lx lx v ref v drv v hi sgnd en v dd pgnd v in cosc pgnd v in el7551c 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 14?16 altera corporation stratix device handbook, volume 2 january 2005 voltage regulators figure 14?14. el7564cm: 5.0-v-to-1.5-v/4-a synchronous switching regulator c 3 0.22 f c 5 0.1 f c 4 390 pf c 2 2.2 nf c 1 330 f c 7 330 f v 0 1.5 v 4 a v in 5.0 v l 1 4.7 h r 4 22 r 1 1 k r 2 539 c 10 100 pf d 1 c 6 0.22 f pgnd lx pgnd pgnd v in stp stn fb v drv v hi en pg lx pgnd sgnd v dd v tj v ref cosc pgnd el7564cm 8 9 10 13 12 11 1 2 3 4 5 6 7 20 19 18 17 16 15 14 altera corporation 14?17 january 2005 stratix device handbook, volume 2 designing with 1.5-v devices figure 14?15. el7556bc: 5.0-v-to-1.5-v/6-a synchronous switching regulator notes to figures 14?13 to 14?15 : (1) these capacitors are ceramic capacitors. (2) these capacitors are cera mic or tantalum capacitor. (3) these are bat54s fast diodes. (4) d4 is only required for el7556acm. (5) this is a sprague 293d337x96r3 2x330 f capacitor. (6) this is a sprague 293d337x96r3 3x330 f capacitor. c 11 (2) 0.22 f c 10 ( 6 ) 1.0 mf c 5 (2) 1 f c 4 (1) 0.1 f c 6 (1) 0.1 f c 8 (1) 220 pf c 7 (1) 39 pf c 12 1.0 f c 9 ( 5 ) 660 f v in test pwrgd ot fb1 outen c slope v dd v ssp v ssp v ssp v ssp v ssp v cc2det v in v in c ref c osc fb2 c 2v v hi lx lx v ssp v ssp lx lx c p v ss el7556bc r 5 5.1 r 4 100 l 1 2.5 h r 6 39.2 r 1 20 d 4 optional (3) , (4) v out = 1.5 v (1 + ) r 3 50 v in d 3 (3) d 2 (3) d 1 (3) r 3 r 4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14?18 altera corporation stratix device handbook, volume 2 january 2005 voltage regulators figures 14?16 and 14?17 show the switching regulator that converts 3.3 v to 1.5 v with different output currents. figure 14?16. el7562cm: 3.3-v to 1.5-v/2-a synchronous switching regulator figure 14?17. el7563cm: 3.3-v to 1.5-v/4-a synchronous switching regulator v out 1.5 v 2 a v in 3.3 v sgnd v dd pgnd v in v in en c osc pgnd pgnd fb lx v hi lx pgnd v ref v drv el7562cm 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 r 3 39 c 5 0.1 f c 6 0.1 f c 8 0.1 f c 2 0.1 f c 3 0.1 f c 4 270 pf c 1 100 f c 9 0.1 f c 7 100 f l 1 2.5 h r 2 539 r 1 1 k d 2 d 3 d 4 v out 1.5 v 4 a v in 3.3 v v ref c osc v tj pgnd pgnd v in sgnd v dd en pg v hi lx lx pgnd fb v drv el7563cm 20 19 18 17 16 15 14 13 pgnd pgnd stp stn 12 11 9 10 1 2 3 4 5 6 7 8 r 4 22 c 7 330 f l 1 2.5 h r 2 513 r 1 1 k c 3 0.22 f c 6 0.22 f c 10 2.2 nf c 1 330 f c 9 0.1 f c 8 0.22 f c 2 2.2 nf c 4 390 pf c 5 0.1 f d 1 d 3 d 2 d 4 altera corporation 14?19 january 2005 stratix device handbook, volume 2 designing with 1.5-v devices 1.5-v regulator application examples the following sections show the proces s used to select a voltage regulator for three sample designs. the regulator selection is based on the amount of power that the cyclone device consumes. there are 14 variables to consider when selecting a voltage regulator. the following variables apply to cyclone device power consumption: f max output and bidirectional pins average toggle rate for i/o pins (tog io ) average toggle rate for logic elements (les) (tog lc ) user-mode i cc consumption maximum power-up i ccint requirement utilization v ccio supply level v ccint supply level the following variables apply to the voltage regulator: output voltage precision requirement supply voltage on the board voltage supply output current variance of board supply efficiency different designs have different power consumptions based on the variables listed. once you calculate the cyclone device?s power consumption, you must consider how much current the cyclone device needs. you can use the cyclone power calculator (available at www.altera.com ) or the powergauge tm tool in the quartus ii software to determine the current needs. also check the maximum power-up current requirement listed in the power consumption section of the cyclone fpga family data sheet because the power-up current requirement may exceed the user-mode current cons umption for a specific design. once you determine the minimum curr ent the cyclone device requires, you must select a voltage regulator that can generate the desired output current with the voltage and current su pply that is available on the board using the variables listed in this section. an example is shown to illustrate the voltage regulator selection process. 14?20 altera corporation stratix device handbook, volume 2 january 2005 1.5-v regulator application examples synchronous switching regulator example this example shows a worst-case sc enario for power consumption where the design uses all the les and ram. table 14?7 shows the design requirements for 1.5-v design using a cyclone ep1c12 fpga. table 14?8 uses the checklist on page 14?9 to help select the appropriate voltage regulator. table 14?7. design requirements for the example ep1c12f324c design requirement value output voltage precision requirement 5 % supply voltages available on the board 3.3 v voltage supply output current available for this section (i in, dc(max) ) 2 a variance of board supply (v in ) 5 % f max 150 mhz average tog io 12.5 % average tog lc 12.5 % utilization 100 % output and bidirectional pins 125 v ccio supply level 3.3 v v ccint supply level 1.5 v efficiency 90 % table 14?8. voltage regulator selection proc ess for ep1c12f324c design (part 1 of 2) output voltage requirements v out = 1.5 v supply voltages v in or v cc = 3.3 v supply variance from linear technolog y data sheet supply variance = 5 % estimated i ccint use cyclone power calculator i ccint = 620 ma estimated i ccio if regulator powers v ccio use cyclone power calculator (not applicable in this example because v ccio = 3.3 v) i ccio = n/a total user-mode current consumption i cc = i ccint + i ccio i cc = 620 ma altera corporation 14?21 january 2005 stratix device handbook, volume 2 designing with 1.5-v devices board layout laying out a printed circuit board (p cb) properly is extremely important in high-frequency ( 100 khz) switching regulator designs. a poor pcb layout results in increased emi and ground bounce, which affects the reliability of the voltage regulator by obscuring important voltage and current feedback signals. altera recommends using gerber files ? pre- designed layout files ? supplied by the regulator vendor for your board layout. if you cannot use the supplied layout files, contact the voltage regulator vendor for help on re-designing the board to fit your design requirements while maintaining the proper functionality. altera recommends that you use separa te layers for signals, the ground plane, and voltage supply planes. yo u can support separate layers by using multi-layer pcbs, assuming you are using two signal layers. ep1c12 maximum power-up current requirement see power consumption section of the cyclone fpga family data sheet for other densities i puc(max) = 900 ma maximum output current required compare i cc with i puc(max) i out(max) = 900 ma voltage regulator selection see linear technology ltc 1649 data sheet see intersil (elantec) el7562c data sheet ltc1649 i out(max) = el7562c i out(max) = 15 a 2 a ltc1649 nominal efficiency ( ) nominal efficiency ( ) = > 90 % line and load regulation line regulation + load regulation = (0.17 mv + 7 mv)/ 1.5 v 100 % line and load regulation = 0.478 % < 5 % minimum input voltage (v in(min) ) (v in(min) ) = v in (1 ? v in ) = 3.3v(1 ? 0.05) (v in(min) ) = 3.135 v maximum input current i in, dc(max) = (v out i out(max) )/( v in(min) ) i in, dc(max) = 478 ma < 2 a el7562c nominal efficiency ( ) nominal efficiency ( ) = > 95 % line and load regulation line regulation + load regulation = (0.17 mv + 7 mv)/ 1.5 v 100 % line and load regulation = 0.5 % < 5 % minimum input voltage (v in(min) ) (v in(min) ) = v in (1 ? v in ) = 3.3v(1 ? 0.05) (v in(min) ) = 3.135 v maximum input current i in, dc(max) = (v out i out(max) )/( v in(min) ) i in, dc(max) = 453 ma < 2 a table 14?8. voltage regulator selection proc ess for ep1c12f324c design (part 2 of 2) 14?22 altera corporation stratix device handbook, volume 2 january 2005 board layout figure 14?18 shows how to use regulators to generate 1.5-v and 2.5-v power supplies if the system needs two power supply systems. one regulator is used for each power supply. figure 14?18. two regulator solution for systems that require 5.0-v, 2.5-v & 1.5-v supply levels figure 14?19 shows how to use a single regulator to generate two different power supplies (1.5-v and 2. 5-v). the use of a single regulator to generate 1.5-v and 2.5-v supplies from the 5.0-v power supply can minimize the board size and thus save cost. figure 14?19. single regulator solution for systems that require 5.0-v, 2.5-v & 1.5-v supply levels regulator regulator 2.5-v device 1.5-v device altera cyclone fpga 1.5 v 5.0 v 2.5 v pcb regulator 2.5-v device 1.5-v device altera cyclone fpga 1.5 v 5.0 v 2.5 v pcb altera corporation 14?23 january 2005 stratix device handbook, volume 2 designing with 1.5-v devices split-plane method the split-plane design method reduces the number of planes required by placing two power supply pl anes in one plane (see figure 14?20 ). for example, the layout for this method can be structured as follows: one 2.5-v plane, covering the entire board one plane split between 5.0-v and 1.5-v this technique assumes that the majori ty of devices are 2.5-v. to support multivolt i/o, altera devices must ha ve access to 1.5-v and 2.5-v planes. figure 14?20. split board layout for 2.5-v systems with 5.0-v & 1.5-v devices conclusion with the proliferation of multiple vo ltage levels in systems, it is important to design a voltage syst em that can support a low-power device like cyclone devices. designers must consider key elements of the pcb, such as power supplies, regulators, power consumption, and board layout when successfully designing a system that incorporates the low- voltage cyclone family of devices. 2.5-v device 2.5-v device 2.5-v device 5.0-v device 5.0-v device 1.5-v device 1.5-v device 2.5-v device altera cyclone fpga (1.5 v) 1.5 v pcb 5.0 v regulator 14?24 altera corporation stratix device handbook, volume 2 january 2005 references references linear technology corporation. application note 35 (step down switching regulators) . milpitas: linear technology corporation, 1989. linear technology corporation. lt1573 data sheet (low dropout regulator driver) . milpitas: linear technology corporation, 1997. linear technology corporation. lt1083/lt1084/lt1085 data sheet (7.5 a, 5 a, 3 a low dropout positi ve adjustable regulators) . milpitas: linear technology corporation, 1994. linear technology corporation. ltc1649 data sheet (3.3v input high power step-down switchin g regulator controller) . milpitas: linear technology corporation, 1998. linear technology corporation. ltc1775 data sheet (high power no rsense current mode synchronous step-down switching regulator) . milpitas: linear tech nology corporation, 1999. intersil corporation. el7551c data sheet (monol ithic 1 amp dc:dc step- down regulator) . milpitas: intersil corporation, 2002. intersil corporation. el7564c data sheet (monol ithic 4 amp dc:dc step- down regulator) . milpitas: intersil corporation, 2002. intersil corporation. el7556bc data sheet (integrated adjustable 6 amp synchronous switcher) . milpitas: intersil corporation, 2001. intersil corporation. el7562c data sheet (monol ithic 2 amp dc:dc step- down regulator) . milpitas: intersil corporation, 2002. intersil corporation. el7563c data sheet (monol ithic 4 amp dc:dc step- down regulator) . milpitas: intersil corporation, 2002. |
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